The CYC_TO_TICK macro converts hardware cycles to
system ticks. Smartbond timers can be driven by XTAL32,
RC32K, or RCX sources. At the application level,
tests use milliseconds, which introduces rounding when
converting to hardware cycles.
Previously, CYC_TO_TICK rounded up, causing sys_clock_elapsed()
to sometimes report one extra tick. This value, propagated
through z_add_timeout() via elapsed(), was then used by tests
to determine the current time and the next wake-up point.
As a result, sleep duration was shortened by one tick,
leading to an unnecessary extra wake-up detected by the test.
With this fix, sys_clock_elapsed() no longer reports ticks
that have not fully elapsed, ensuring accurate sleep timing.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg.xr@bp.renesas.com>
Calibration interval was specified in Kconfig now
configuration is moved to device tree.
This allows to have different values for RCX and RC32K.
While calibration is vital for correct system timing, it
periodically schedules work that measures frequency of RCX or
RC32K.
Now it's also possible to set calibration interval to 0
to prevent calibration entirely. This may be useful for
scheduling tests that are sensitive to number of active
threads.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg.xr@bp.renesas.com>
`priv_pcd_prepare` now only consumes per-instance information or constants.
Instead of calling it indirectly through a function pointer, it could be
called directly, but since it is very shorted and used from only one place,
inline it instead.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Instead of consuming the DT property directly, save the USB controller base
address in the instance configuration block and retrieve it at runtime.
This makes the driver more instance-aware.
While at it, cleanup `priv_pcd_prepare` to always consume the property
(through the instance configuration) instead of sometimes using the base
address from CMSIS.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move the controller's IRQn from instance data to instance configuration,
and update all consumers accordingly. One instance which used the global
UDC_STM32_IRQ is also updated to consume the per-instance field instead.
While at it, add missing comments for certain fields of the configuration.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
This patch refactors the power management initialization for the Intel
ADSP power domain driver to align with the recommended practices
outlined in the documentation. The changes include:
1. Replacing the manual power management initialization sequence
(`pm_device_init_suspended` + `pm_device_runtime_enable`) with a call
to `pm_device_driver_init` in the `pd_intel_adsp_init` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the power
domain nodes in the device tree files for ACE15, ACE20, ACE30, and
ACE40.
These changes ensure that the power domain driver is initialized with
the appropriate power management state and that runtime power management
is automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
For devices like MCXE247, the LPIT instance hase multiple
interrupts, however the current driver code just support
one interrupt. This patch has improved the code for this
requirement.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
This is a follow-up to commit d1abe40fb0.
Function `qspi_wait_while_writing()` (and also `qspi_rdsr()` that is
called by it) is now always required for `qspi_erase()`, so it can no
longer be under `#if !IS_EQUAL(INST_0_QER, JESD216_DW15_QER_VAL_NONE)`.
Also definition of `dev_config` in `configure_chip()` needs to be moved,
as for QER set to NONE, it is not used and causes a compilation warning.
Add a test case that will ensure the driver can be built successfully
with `quad-enable-requirements = "NONE"`.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
When EC wakes by GPIO, it may fall back to SUSPEND_TO_IDLE
before the host or peripherals have a chance to take further action.
Add a lightweight delay-sleep mechanism to keep system awake
for as short period after a GPIO wake event.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
Add a new PM CPU ops driver for Arm Fixed Virtual Platform (FVP) that
enables bare metal SMP support without Arm Trusted Firmware (ATF).
The driver provides CPU power-on and system reset operations by directly
interfacing with FVP's power controller (PWRC) and V2M system registers.
The implementation includes RVBAR_EL3 configuration to redirect
secondary CPU reset vectors to Zephyr's image header, enabling
proper SMP initialization without firmware assistance.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Updates DMA includes from the modules needed for DMA PDL based driver
implementation.
Cleans up cmake to use only USE_INFINEON_DMA Kconfig option to select
dma files from PDL/HAL.
Signed-off-by: John Batch <john.batch@infineon.com>
Some FlexCAN devices have enhanced bit timing registers (EPRS ENCBT EDCBT)
with extended timing configuration ranges and different behavior compared
to standard bit timing registers.
This change adds proper support for these enhanced registers, utilize full
bit timing capabilities.
Key differences for enhanced bit timing registers:
- Extended timing ranges with larger maximum values for sjw, phase_seg1,
phase_seg2, and prescaler fields
- No propagation segment configuration support, so prop_seg must be 0
- prop_seg value is used directly without the typical 'minus 1' adjustment
The implementation adds conditional compilation based on the
`FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG` feature flag.
For Enhanced registers, use extended timing limits and prop_seg directly.
Test this commit on mimxrt1180_evk/mimxrt1189/cm33 drivers.can.timing
test case, and enable `TEST_ALL_BITRATES` Kconfig symbol.
Signed-off-by: William Tang <william.tang@nxp.com>
Depending on the IP's `IC_TX_CMD_BLOCK_DEFAULT` parameter, we
might have to clear the `TX_CMD_BLOCK` bit on init so that
Controller mode works.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This driver had a lot of regressions introduced by commits that were
clearly mixing up what values had units of bytes and what values had
units of words. Fix the issues in the DMA path of the driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The asserts are hard to debug and unrecoverable, they just say kernel
panicked but difficult to realize where and why, it's better to return
an error and log message clearly from spi driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
It is not illegal to provide an RX len with no buffer.
It just means the controller should clock out that many
words but not store them in memory. So remove the assert
and just avoid null dereference.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Refactor this function to return an error code, instead of assert.
Put the data into a pointed argument instead.
Refactor other functions to make sure to
propogate this error all the way up the call stack.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Enables Digital mode for both input and output GPIO
pins, in gpio_mcux_lpc_configure().
- Fixes#99255
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Use a local accumulator (`cfg`) to build the pin configuration and commit
it to `*pincfg` only once. This keeps intermediate values in registers,
reduces RAM write traffic.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
After trying out a few different approaches, I think having separate
nodes for each bank in devicetree and having a GPIO proxy node for the
controller is the best solution right now.
To be more specific, GPIO proxy solution still allows for bank level
GPIO toggling. The linux kernel GPIO davinci driver is currently limited
to single pin operations. This might not be a problem in Linux, but I
feel like embedded systems would prefer having support for bank level
operations.
This also does not pose a problem for the future implementation of
interrupts due to that fact that the interrupt router is separate device
and will require a separate driver. In fact, the GPIO interrupt router
is shared between main_gpio0 and main_gpio1.
This patch also reverts the previous bank offset related work on GPIO
davinci driver.
The patch has been tested on PocketBeagle 2.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
nRF91 Serial Modem application does not anymore start PPP automatically.
Update initialization script to request it.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
The file descriptor table is used in every area that expects to work on
files through descriptor indices. It can only be operated on through
functions whose names indicate a relationship with ZVFS (`zvfs_*fd*`).
The integer file descriptor mechanism shouldn't be separate from ZVFS.
This will make cooperation between different file access APIs much
simpler. This commit also makes preparations for the fdtable becoming
optional.
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Switch the Xilinx AXI I2C device driver to use the DEVICE_MMIO_...
macros instead of directly using the physical base address from the
device tree. This allows the driver to work on SoCs with an MMU,
such as the Zynq-7000.
Signed-off-by: Simon Maurer <mail@maurer.systems>
Fixes an issue with an unused function being defined if
CONFIG_DEVICE_DEINIT_SUPPORT was disabled
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes an issue with an unused function being defined if
CONFIG_DEVICE_DEINIT_SUPPORT was disabled
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes an issue with an unused function being defined if
CONFIG_DEVICE_DEINIT_SUPPORT was disabled
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This change introduces sai disable at the end of stream or
in an event of an error. It disables SD, FS and SCK.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Align all sensor drivers that are using stmemsc (STdC) HAL i/f
to new APIs of stmemsc v2.11.1
Requires https://github.com/zephyrproject-rtos/hal_st/pull/27
Signed-off-by: Armando Visconti <armando.visconti@st.com>
When CONFIG_UDC_DRIVER_HIGH_SPEED_SUPPORT_ENABLED is disabled, force
configure ehci controller to work as FS.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
A change was introduced in how stm32 timers clocks are defined
to have multiple clock definitions.
This change was not handled in the stm32u3 series driver
(which had no timers defined in the dts at all).
This fix ports the required code to the stm32u3 mcu.
Signed-off-by: Richard Skriwanek <richy@fnc.at>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
