Commit graph

23353 commits

Author SHA1 Message Date
Guillaume Gautier
2460e894e4 drivers: adc: stm32: remove unused cast
config->base is already defined as ADC_TypeDef so no there is no need to
cast it as such. Remove all occurrences throughout the file.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-12-18 15:32:35 +01:00
Guillaume Gautier
47b2bb7652 drivers: adc: stm32: listify some tables
Listify the content of the tables used for sequencer and oversampling.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-12-18 15:32:35 +01:00
Guillaume Gautier
420b2a053c drivers: adc: stm32: move define from dt-binding into driver
Now that clock source and sequencer are defined with strings in device
tree, move the old defines directly in the driver

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-12-18 15:32:35 +01:00
Guillaume Gautier
e0554aa453 drivers: adc: stm32: use a string for sequencer and clock source property
Now that st,adc-sequencer and st,adc_clock-source use a string, update the
ADC driver.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>

fu drv adc update driver with string
2024-12-18 15:32:35 +01:00
Guillaume Gautier
afa97d12ec drivers: adc: stm32: simplify adc dma enable function
Remove specific cases for H7 and U5: group them together and only call a
single function. ADC3 of H72x/H73x and ADC4 of U5 are different from other
ADC of their series, and have dedicated functions in the LL for enabling
DMA, but they're doing the exact same operation as
LL_ADC_REG_SetDataTransferMode.

Incidentally, this change allows H7A/H7B to use the DMA (it seems to have
been missed before).

Last, this change enables the DMA support for F1x ADC.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-12-18 15:32:35 +01:00
Guillaume Gautier
4cfbf78939 drivers: adc: stm32: simplify oversampling with new property
Use the new oversampler property to simplify the management of the
ADC oversampling.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-12-18 15:32:35 +01:00
Guillaume Gautier
fb5ff902e8 drivers: adc: stm32: better express f3 and h7 adc versions
STM32F3 and H7 have multiple ADC versions difficult to differentiate.
Use clearer macros to make code more readable.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-12-18 15:32:35 +01:00
Guillaume Gautier
e978164a6b drivers: adc: stm32: add log message when adc overrun
Displays an error log message when an ADC overrun occurs.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-12-18 15:32:35 +01:00
Yishai Jaffe
1b4cef325b shell: use shell_device_get_binding
Use shell_device_get_binding() instead of device_get_binding() so that
we get the device based on its name and in addition by its label.

Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
2024-12-18 15:32:10 +01:00
Hongquan Li
13ea58775b drivers/wifi/esp_at: Use mode 2 to connect when using as a UDP server
Mode 0 cannot establish a connection when used as a UDP server,
replace mode 0 with mode 2 to save the client's IP and port as
the communication address when a message is received.

Fixes #82898

Signed-off-by: Hongquan Li <hongquan.prog@gmail.com>
2024-12-18 15:31:55 +01:00
James Roy
3cf4347c15 drivers: gpio: Fix unchecked return value in gpio_pca_series
Fix unchecked return value scanned by Coverity.

Signed-off-by: James Roy <rruuaanng@outlook.com>
2024-12-18 15:31:33 +01:00
Guennadi Liakhovetski
6f1fc6e96c drivers: dai: ssp: remove unused variables
Fix compiler warnings
/zep_workspace/zephyr/drivers/dai/intel/ssp/ssp.c:2079:18: error: \
unused variable 'ssrsa' [-Werror=unused-variable]
 2079 |         uint32_t ssrsa = 0;
      |                  ^~~~~
/zep_workspace/zephyr/drivers/dai/intel/ssp/ssp.c:2078:18: error: \
unused variable 'sstsa' [-Werror=unused-variable]
 2078 |         uint32_t sstsa = 0;
      |                  ^~~~~

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-12-18 15:31:18 +01:00
Khoa Nguyen
e95d18587f drivers: adc: Add ADC properties in Renesas RA ADC node
- Add "channel-available-mask" property in ADC node
to detect which channels are available to use

- Add "add-average-count" property in ADC node to chose
number of count of the addition or average mode

- Change the source code of ADC to match with 2 new properties.

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2024-12-18 12:46:31 +01:00
Gerard Marull-Paretas
bcb2b3620e drivers: clock_control: nrf54h-fll16m: use values from BICR
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-18 12:46:20 +01:00
Gerard Marull-Paretas
f267c339f7 drivers: clock_control: nrf54h-lfclk: use values from BICR
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-18 12:46:20 +01:00
Gerard Marull-Paretas
d5041aecec drivers: clock_control: nrf54h-common: add utility to obtain LFOSC acc
Add a utility function to obtain LFOSC accuracy in PPM from BICR.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-18 12:46:20 +01:00
Gerard Marull-Paretas
5415c42dd4 drivers: clock_control: nrf54h-hfxo: use values from BICR
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-18 12:46:20 +01:00
Qingling Wu
dbc6a50698 drivers: wifi: nxp: add set RTS threshold command support
Add set RTS threshold command support for sta and sap in nxp driver.

Signed-off-by: Qingling Wu <qingling.wu@nxp.com>
2024-12-18 10:17:24 +01:00
Benjamin Bigler
f1087d2042 drivers: adc: tla202x: add support for tla2022 and tla2024
This extends the tla2021 driver to support tla2022 and tla2024

Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
2024-12-18 08:33:49 +01:00
Benjamin Bigler
7609ceadc4 drivers: adc: tla2021: rename everything from tla2021 to tla202x
Rename everything from tla2021 to tla202x (except dtcompatible)
in preparation to add support for tla2022 and tla2024

Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
2024-12-18 08:33:49 +01:00
Benjamin Bigler
25c210e8eb drivers: adc: tla2021: sleep until sampling is done
Sleep until sampling is done instead of polling. This avoids
blocking of other threads.

Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
2024-12-18 08:33:49 +01:00
Nathan Olff
42e7095d1e drivers: adc: adc_emul: implement raw func set function in adc_emul
allow setting a function as generator of raw adc values in adc_emul

Signed-off-by: Nathan Olff <nathan@kickmaker.net>
2024-12-18 08:33:26 +01:00
Nathan Olff
d793b86a82 drivers: adc: adc_emul: write function to set const raw value
implement storage and retrieval of raw value in adc_emul

Signed-off-by: Nathan Olff <nathan@kickmaker.net>
2024-12-18 08:33:26 +01:00
Xavier Ruppen
06b7dc81a5 drivers: ethernet: enc28j60: disable/enable interrupts to avoid races
Currently, there is a small race window where we can miss an interrupt.
Right after we're done reading the RX buffer but just before decrementing
the RX counter to zero, the ENC28J60 may receive a packet. The chip will
raise an interrupt, but the line is still asserted. That means that the
callback will not be invoked since it is edge-triggered.

To avoid that, disable interrupts on the chip itself before processing
the RX buffer.

In fact, the ENC28J60 datasheet specifically says:

	"After an interrupt occurs, the host controller should
	clear the global enable bit for the interrupt pin before
	servicing the interrupt. Clearing the enable bit will
	cause the interrupt pin to return to the non-asserted
	state (high). Doing so will prevent the host controller
	from missing a falling edge should another interrupt
	occur while the immediate interrupt is being serviced.
	After the interrupt has been serviced, the global enable
	bit may be restored. If an interrupt event occurred while
	the previous interrupt was being processed, the act of
	resetting the global enable bit will cause a new falling
	edge on the interrupt pin to occur."

This is also what is being done in the Linux driver [1].

[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1126

Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
2024-12-18 08:32:49 +01:00
Xavier Ruppen
7d95cc4ce3 drivers: ethernet: eth_enc28j60: do not check PKTIF on interrupt
The enc28j60 errata sheet says:

	"The Receive Packet Pending Interrupt Flag
	(EIR.PKTIF) does not reliably/accurately report
	the status of pending packets."

	"In the Interrupt Service Routine, if it is unknown if
	a packet is pending and the source of the interrupt
	is unknown, switch to Bank 1 and check the value
	in EPKTCNT.
	If polling to see if a packet is pending, check the
	value in EPKTCNT."

A workaround has already been implemented inside of eth_enc28j60_rx().
But checking PKTIF before calling eth_enc28j60_rx() completely defeats
the purpose of the workaround. Do not check it.

Moreover, clearing ENC28J60_BIT_EIR_PKTIF is useless since it is
automatically cleared once all packets are read. So remove that check
and clarify comment.

Also please refer to the Linux driver [1].

[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1090

Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
2024-12-18 08:32:49 +01:00
Robin-Charles Guihéneuf
3a2ac9aa64 drivers: i2c: Fix SMBus build with stm32f4 family chip
The build condition was only dealing with the new line of SoC.

Signed-off-by: Robin-Charles Guihéneuf <robin-charles@hotmail.fr>
2024-12-18 08:32:32 +01:00
Mikhail Siomin
36bbd67653 drivers: gpio_pca95xx: add pins initialization to default state
After a non-power reset (wdt) pins may remain in non-default state.
To ensure that a system initialization is the same after any reset,
it is necessary to initialize pins to the default state.

Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
2024-12-18 08:32:15 +01:00
Jiafei Pan
55f0b87143 drivers: gpio: mcux_igpio: add MMIO mapping support
Map MMIO memory by using DEVICE_MMIO_NAMED_x() APIs.

And some platforms has no soc.h, so use __has_include to check it
firstly.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-12-18 08:31:52 +01:00
Jordan Yates
06c29b1b61 i2c: nrfx_twim: mark as PM_DEVICE_ISR_SAFE
Mark the I2C instances as `PM_DEVICE_ISR_SAFE`, as the transition
operations are short, it saves RAM resources, and the spin-locking fixes
the non-atomic behaviour of the PM usage counter.

Signed-off-by: Jordan Yates <jordan@embeint.com>
2024-12-18 08:31:30 +01:00
Wei-Tai Lee
913fddb80e drivers: cache: andes: Decouple cache line size calculation
Eliminate the dependency on specific configuration options
for calculating the cache line size.

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2024-12-18 03:04:57 +01:00
Wei-Tai Lee
c351a0e044 drivers: cache: andes: Fix incorrect DT_PROP usage
Remove redundant quotation marks when parsing
cache line size from DTS properties.

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2024-12-18 03:04:57 +01:00
Wei-Tai Lee
b3d3c0f702 driver: cache: andes: Support enable/disable on CPUs lacking CCTL CSRs
For CPUs without CCTL CSRs, return ENOTSUP in cache operations.

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2024-12-18 03:04:57 +01:00
Wei-Tai Lee
5cf6137b38 drivers: cache: andes: Dynamically calculate L2 cache parameters
Enhance the driver to calculate the L2 cache line size and number
of ways at runtime. The L2 cache line size is assumed to match
the L1 cache line size, while the number of ways is determined
based on the total L2 cache size.

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2024-12-18 03:04:57 +01:00
Stoyan Bogdanov
92aeb787c7 drivers: gpio: max22190: Add MAX22190 octal input with diagnostics
Add max22190 gpio driver with input functionality, since device
support only input without output.

Implemented diagnostic functionality for all 8 channels
which include various check to over/under voltage and wire break.
Filtering configuration is done from devicetree on per channel
bases and is configured on chip start.

In case some fault condition occure FAULT pin drive LOW which
prop to FAULT registers to be read. Data is stored in data structure
for furter analizes and ERR message is printed in console.

Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
2024-12-18 03:04:46 +01:00
Aurelie Fontaine
8a0469dc4f drivers: sensor: icm42670: supports icm42670-P/-S
Prepare to use official TDK Invensense Inc. driver for icm42670-P/-S
sensor in tdk_hal module. Simplify I2C and SPI transport files.
Driver code moves in hal_tdk module.
Adds APEX features, such as Pedometer, Tilt detection, Wake on Motion
and Significant Motion Detector.

Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
2024-12-18 03:04:31 +01:00
Lucien Zhao
c0b21f4a30 drivers: sensor: nxp: add code judge whether read back correctly
find a sensor driver bug don't judge the data whether read back
correctly, deal with buffer data directly.

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-12-18 01:01:37 +01:00
Lucien Zhao
a831f7df6d drivers: clock_control: add i3c clock for clock_control_mcux_ccm_rev2.c
add i3c case to get i3c instance clock

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-12-18 01:01:37 +01:00
Immo Birnbaum
63b65299df drivers: ethernet: xlnx_gem: enable querying of HW checksum support
Add a get_config function for this driver as specified in the
Ethernet subsystem API. The implementation supports querying
the hardware checksum generation capabilities of the specified
GEM device instance. This prevents the transmission of packages
without a valid checksum for protocols such as ICMP, as the
hardware only supports IPv4/IPv6 TCP and UDP checksum generation.

Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
2024-12-18 01:01:22 +01:00
Piotr Pryga
233095c3f4 drivers: clock_control: nrf: hfxo: Remove redundad code
There were redundant code in full_irq_lock(), full_irq_unlock()
functions that supposed to be used when ZLI IRQs are disabled.
These functions are compiled in only when CONFIG_ZERO_LATENCY_IRQS
is set, hence the non-ZLI execution path was never included
in final binaries.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2024-12-18 01:00:56 +01:00
Mario Paja
9dde4b97c0 drivers: ethernet: lan9250: implement set_config
Implements set_config api to set mac address

Signed-off-by: Mario Paja <mariopaja@hotmail.com>
2024-12-18 01:00:00 +01:00
Teresa Zepeda Ventura
830fe6ec19 drivers: pwm: add a SAM0 TC based PWM driver
This runs the Timer/counter in 'normal' PWM mode (for 8-bits)
and in 'match' PWM mode (for 16-bits).

Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
2024-12-17 23:14:32 +01:00
Raffael Rostagno
b313344e22 drivers: mcpwm: esp32: Clock update for new devices
Update clock configuration to support newer devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-12-17 23:14:19 +01:00
Raffael Rostagno
15cb7d3d74 drivers: mcpwm: esp32: Driver update for new HAL
Remove deprecated functions to comply with new HAL versions.
Handle capture interrupts more appropriately by clearing status
bit for only one channel.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-12-17 23:14:19 +01:00
Derek Snell
b3d8766126 drivers: dma: dma_mcux_edma: fix previous TCD index
fixes issue calculating index of previous TCD in circular list.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2024-12-17 20:54:58 +01:00
Rafał Kuźnia
6f6402418a drivers: serial: nrfx_uarte: Fix bool endtx-stoptx prop check
The dt_nodelabel_bool_prop must be used to check for a boolean property,
not the dt_nodelabel_has_prop. Using the latter caused the
UART_X_ENHANCED_POLL_OUT condition to be not fulfilled, despite the
fact that the property was not set on nRF52840 and nRF91.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-12-17 17:52:26 +01:00
Raffael Rostagno
0d5c76a2b3 drivers: counter: esp32: Spinlocks cleanup
Remove unnecessary spinlock directives.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-12-17 15:23:38 +01:00
Raffael Rostagno
203c71d1f7 drivers: counter: esp32: Driver update
Cleanup and timer frequency management improvement to support
new devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-12-17 15:23:38 +01:00
Bjarki Arge Andreasen
7487eabd33 drivers: serial: nrfx_uarte: rm NRF_GPD_FAST_ACTIVE1 build assert
The assert BUILD_ASSERT(NRF_GPD_FAST_ACTIVE1 == 0); is not correct
given that NRF_GPD_FAST_ACTIVE1 is defined as 1U, and is not used
in the file anyway. Remove the build assert.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2024-12-17 15:22:37 +01:00
Bjarki Arge Andreasen
ef8bf34e61 drivers: clock_control: nrf2: add support for global hfsll clock
Add device driver support for global hsfll clock.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2024-12-17 15:22:37 +01:00
Bjarki Arge Andreasen
777adf4231 dts: bindings: update nrf-hsfll to nrf-hsfll-local
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.

Updates drivers and devicetree uses of HSFLL as well.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2024-12-17 15:22:37 +01:00