udc_ambiq was using USB test mode definition in dwc2 header, which
the include was removed, hence compilation now fails. This commit
fixes the compilation failure.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
Add support for 8-channel configurable DMA controller. The driver
supports the following features:
- memory to peripheral (ch0 to ch5)
- peripheral to memory (ch0 to ch5)
- memory to memory (ch6 and ch7)
Each DMA channel is multiplexed between two or more trigger sources:
- ch0 -> SPI0_TX or UART0_RX
- ch1 -> SPI0_RX or UART0_TX
- ch2 -> LRFD or UART0_TX
- ch3 -> ADC0 or UART0_RX
- ch4 -> AES_A or LRFD
- ch5 -> AES_B or ADC0
- ch6 -> Software Event Channel 0
- ch7 -> Software Event Channel 1
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The passive level of the clock does not change instanteneously when
it's set using function XMC_SPI_CH_ConfigureShiftClockOutput().
This means that the passive level of the clock can be in the wrong
state when the chip select goes low.
Fix this by adding a small delay when the polarity changes to allow
the clock to return to the proper level.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
This uses the network packet as is without the need for a copy all the
way till the packet is handed over to RPU.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
It is already ensured in the fpga logic, that there is only one
interrupt per liteeth dev at a time. So we can remove the irq_lock on rx.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This patch adds a mutex for the eth_tx() function to prevent multiple
threads from calling the function at the same time.
Also remove the unneded irq_lock in that function.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Convert z_clock_hw_cycles_per_sec to unsigned int to increase
supported frequency range.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Block the SoC from re-entering sleep modes while the RX line is active,
if the RX activity previously woke the device from the sleep states.
This stops the device from continuously transitioning between the two
modes and improves responsiveness.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Fix dropped `UART_TX_DONE` events when poll out and async APIs are used
on the same port. Clearing `tx_poll_stream_on` is required to prevent
`uart_stm32_isr` from prematurely clearing the TC status bit.
Signed-off-by: Jordan Yates <jordan@embeint.com>
- Add spaces around /* ... */
- Fix a typo and remove a stray space in the description of
renesas,rz-gpio.yaml to make it visible in doc html
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Fix STM32 I2C driver to not call cache management related functions
when DMA is not used. This change fixes an issue introduced by
commit 42c3a78148 ("i2c: stm32: Add cache memory support"). The issue
makes boards embedding this driver with both CONFIG_I2C_STM32_V2_DMA
and CONFIG_ARCH_MPU disabled to fail to build with an error trace message
like the below:
.../i2c_ll_stm32_v2.c:701: undefined reference to `mem_attr_check_buf'
Fixes: 42c3a78148
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add prompt to Kconfig NRF70_SYSTEM_WITH_RAW_MODES.
It is assigned in a configuration file, but is not directly
user-configurable (has no prompt). It gets its value
indirectly from other symbols.
Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
This commit provides an extension to the i2c_nrfx_twim driver.
It introduces possibility to acquire/release exclusive access to the
i2c bus. While the exclusive access to the i2c bus is acquired
you can access the underlying nrfx_twim driver directly.
Signed-off-by: Andrzej Kuros <andrzej.kuros@nordicsemi.no>
The MAX22199 is an IEC 61131-2 compliant industrial digital input device.
The MAX22199 translates eight 24V current-sinking industrial inputs to a
serialized SPI-compatible output that interfaces with 3V to 5.5V logic. It
can operate as eight Type 1/Type 3 digital inputs or four Type 2 digital
inputs. The device provides diagnostic functions, including thermal
shutdown, 24V under voltage alarm, 24V missing voltage alarm, and SPI and
CRC communication error detection.
Signed-off-by: Robert Budai <robert.budai@analog.com>
Fixes wait for completion problems where the ISR was not sending
out TX NOP's when needed causing the transfer to timeout
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The LSM6DSV32X part is nearly identical to the LSM6DSV16X but has different
sensitivity scales for the accelerometer (4-32G versus 2-16G). This commit
adds support for this part via the "st,lsm6dsv32x" compatible string.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Enable support for HCLK, PCLK1, PCLK2, PCLK4 and PCLK5 as subsystem
clock sources identifiers on STM32N6 SoCs. HCLKx relates to the AHBx
buses clock and PCLKx relate to the APBx buses clocks.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
SETUP data is unconditionally ACKed by the controller. Other DATA
packets sent to OUT control endpoint 0 (i.e. OUT Data Stage packets
and OUT Status Stage packet) are ACKed by the device only if the
endpoint was enabled with CNAK bit set.
In Buffer DMA mode controller will lock up in following scenario:
* OUT EP0 is not enabled, e.g. OUT Status Stage has finished
* Host starts Control Write transfer, i.e. sends SETUP DATA0 and
device ACKs (regardless if endpoint is enabled or not)
* host sends OUT Data Stage (OUT DATA1)
- software enables endpoint to be able to receive next SETUP data
while host is transmitting the OUT token. If CNAK bit is set
alongside the EPENA bit, the device will ACK the OUT Data Stage.
If CNAK bit is not set, the device will NAK the OUT Data Stage.
When the lockup occurs, from host perspective the OUT Data Stage packet
was successfully transmitted. This can result in host starting IN Status
Stage if there was only one OUT Data Stage packet. This in turn results
in device never getting the DOEPTINT0 SetUp interrupt. Besides just not
getting the SetUp interrupt, any subsequent control transfer won't be
noticed by device at all.
The lockup was first observed while stress testing. The host was issuing
endless sequence of Control Write, Control Read, Control Write, Control
Read, ... commands. When the controller did lock up in Buffer DMA mode,
from host perspective the device was timing out all control transfers.
Avoid the Buffer DMA lockup by setting CNAK bit only when necessary.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Implement the '.reset' interface in the nrfx-timer driver
to allow the upper layers to use the counter_reset
function.
Signed-off-by: James Roy <rruuaanng@outlook.com>
Implement the '.reset' interface in the native-posix driver
to allow the upper layers to use the counter_reset
function.
Signed-off-by: James Roy <rruuaanng@outlook.com>
The U-Blox M10 seems to interleave UBX and NMEA messages in a way that
confuses the M8 driver leading to missing the same message that directly
follows the UBX part every time (leading to no navigation updates).
As the driver does not parse the UBX blocks during normal operation anyways
it can just be disabled.
Signed-off-by: Jakob Riepler <jakob+zephyr@chaosfield.at>
The i3c group address support is rather very incomplete here. Remove
references to it. This could all easily come back when/if group support
comes in.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Make the zephyr,input-sdl-touch driver be multi instance and add the
possibility to associate it with a display. The input events are only
emitted if the events occured on this display.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Adds storing of the zephyr display device struct inside of the windows
user_data, so it can be used inside of the SDL touch driver context for
checking the origin window of a received event.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
MAX14917 is an eight high-side switch, specified to deliver up to 700mA
(min) continuous current per channel. The high-side switches have
on-resistance of 120mΩ (typ) at 25°C ambient temperature
Signed-off-by: Robert Budai <robert.budai@analog.com>
Moves the MPU6050 accel/gyro scale settings from KConfig to Devicetree.
Adds a new setting for the MPU6050 sample rate divider register and
transmits it to the sensor upon initialization.
This helps to reduce the interrupt firing rate when combined with the
data ready trigger.
A default division factor is provided which ensures compatibility with
existing applications.
The MPU6050 sample application is extended and used for hardware tests.
Signed-off-by: Tilmann Unte <unte@es-augsburg.de>
