The previous initialization sequence fails to configure the module
properly. Update the sequence using the code provided by vendor.
The update is verified using the FRDM-MCXN947 SmartDMA camera case
under samples/drivers/video/capture.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Fix timeout error that can occur in rare case.
When the thread writing to flash is pre-emptive it can be scheduled
out after reading the status register, but before checking if timeout
has expired. In this case it will report timeout without re-checking
the status register.
When writing a lot to flash, for example a firmware update process
then this situation is very likely to occur.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add the CONFIG_STM32_LTDC_FB_SMH_ALIGN option in order to
indicate the alignment required for the buffer allocated via
SMH.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This stupid errata will not leave me alone, here is another bandaid to
deal with an issue where an extra byte was being sent on version 1
LPSPIs due to the algorithm of filling NOPs when only RX is left was not
expecting the situation where the LPSPI actually consumed everything
from the fifo but is not sending it due to this ridiculous stalling errata.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The buf_len parameter of lpspi_fill_tx_fifo is supposed to be bytes, so
we do not need to convert it. This could cause an issue if the end of
the buffer is less bytes than the word size.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Fixing some issues with the TX fifo fill logic in two places:
First in the normal fill function, it didn't take into account a
situation where the TX fifo is already partially filled. This currently
doesn't cause a problem because the driver is written in a way that the
watermark is always 0 for TDF, but in case the watermark were anything
else it would cause a problem.
Second, when filling the TX fifo with NOPS in order to clock the rest of
the RX in from the bus, the calculation regarding the current TX fifo
length was just wrong and was leading to a bug in some cases where there
was a subtraction underflow and billions of NOPs were being filled.
Also, there could be a problem where a few extra NOPs are put in the TX
fifo if we don't count what we already have in the TX fifo, so fixing
that as well.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There is no need to update the tx context in interrupt instead of
directly after the fill, this just makes the code more complex. Also,
the spi context header already handled iterating over buffers so we can
remove that code too.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
For optimization purpose, remove calls to SDK. Since we know exactly
what we want, this results in smaller code size.
Also, this code calculates the SCK parameters more efficiently than the
SDK driver did it by using a binary (instead of linear) search.
Lastly, remove call to LPSPI_Reset in the init call and replace with
native driver code, and remove inclusion of SDK header.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Instead of waiting forever and potentially allowing infinite loop on
ISR, wait some arbitrary amount of cycles to error out if it isn't
happening. Still make this configurable for debugging purposes.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Since I expect that the drivers will need to read this version ID maybe
multiple times, instead of repeatedly doing so over the peripheral bus,
it is probably worth it to store a byte in RAM representing this
version. The behavior of the LPSPI is fairly significantly different
between versions. Not enough to warrant separate drivers but enough to
need a few workarounds or different code branches depending on this.
Also, the interrupt based driver is currently using a wrong macro to
read this, and that is a bug.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Clarify at the top of the common lpspi file what is the purpose of the
file to be clear to future developers that this file is not supposed to
make any assumption about a particular implementation of the zephyr API
using the LPSPI, because I imagine it could be very likely that more
lpspi implementation will be done in the future to make different
tradeoffs than the current two. Also the current two are different
enough that we should avoid making assumptions even if they currently
hold for both because they might not always, as things change.
We should disable interrupt events while configuring the LPSPI
regardless of implementation. The specific implementation should enable
the interrupts it needs on its own transceive implementation.
Also clarify and simplify some code in the configure function. Namely,
we no longer need to check if we are already configured to write to
registers because a recent commit made it so that we clock the
peripheral from the zephyr driver init instead of upon the MasterInit
call on the SDK. There is also a redundant CR write which I have removed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The sleep-output property is no longer used. This results in the sleep
bit to be always cleared. Delete this code so we can retain any sleep
mode configuration done.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Implement the HDLC over SPI adapter driver to support the Openthread RCP
with SPI communication.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Registers driver with pm_device_driver_init(); implements TURN_ON,
SUSPEND and RESUME. Sets ODR = 0 on suspend per datasheet
Signed-off-by: Van Petrosyan <van.petrosyan@sensirion.com>
Use the HWINFO API for getting the unique mac address, and use the
pre-existing hardcoded macros as fallbacks if hwinfo is not implemented
properly.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The DHT driver incorrectly assumes all sensor instances are the same
type as the first instance (dht@0). The data parsing logic uses a
hardcoded check of the devicetree property for instance 0, which
causes incorrect readings when different sensor models (e.g., DHT11
and DHT22) are used together.
This change stores the model type in each per-instance config struct
during initialization. The data parsing logic is updated to use this
per-instance flag, ensuring each sensor is handled correctly
according to its specific model.
Signed-off-by: John Shelton <moosery@gmail.com>
Fix radio IRQ priorities. With the Controller update from SiSDK,
its behavior changed so that it overwrites the IRQ priorities.
Reconfigure the priorities after the Controller is initialized.
Source interrupt numbers and priorities from devicetree.
Also set the SYNTH IRQ priority on all HW, and set either the
RDMAILBOX or HOSTMAILBOX IRQ depending on which one exists.
Signed-off-by: Jori Rintahaka <jori.rintahaka@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Refactor the controller init to use the new init routines the
controller now provides. Instead of using a hardcoded set of
features, the features are now initialized based on Kconfig
values that the application selects.
Add config files under modules/hal_silabs, used by the controller
init routines in the external module hal_silabs to determine which
features to enable based on Kconfig options. This brings the
controller feature configurability to roughly parity with the
Simplicity SDK.
Signed-off-by: Jori Rintahaka <jori.rintahaka@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add a missing break statement in the pm_action function to ensure that
PM_DEVICE_ACTION_RESUME is not treated as an error.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
To reduce low power current value, added host sleep handshake
enhancement. If CPU3 is wokenup by WLAN, do host sleep handshake with
CPU1 as before. For other wakeup sources, skip host sleep handshake.
Signed-off-by: Hui Bai <hui.bai@nxp.com>
The fractional part of the qdec sensor readout is set to zero (val2 =
0).
Changed the format of the run time data to Q26.6 and adjusted the
assignment of val1 and val2 accordingly.
Signed-off-by: Juraj Lieskovský <lieskovsky.juraj@gmail.com>
SHIM Nordic modification for the ADC driver controlling the SAADC
peripheral. Replaced HAL based implementation in favor of nrfx driver.
As a next step, it is planned to implement a feature that will allow
the peripheral SAADC timer to be used for sampling, and for this it is
necessary to use the nrfx driver in this SHIM.
This will allow more accurate and faster sampling than the kernel
mechanism currently provides.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
New control transfer is started prematurely from device perspective when
host timeout occurs. Any data transfer from previous control transfer
have to be cancelled prior to handling SETUP data. Unconditionally
disable control IN endpoint to prevent race for enqueued buffer between
udc_buf_get_all() called in dwc2_handle_evt_setup() and udc_buf_peek()
called in dwc2_handle_in_xfercompl().
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Texas Instruments MSPM0 series supports device id fields with
various part information and also resgister to hold reset reason.
Reset cause register will defaults to 0 after first read.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
The EDAC shell code previously contained a number of references to the
Intel IBECC driver. Make the shell code more generic to the defined EDAC
API, and make IBECC-specific code dependent on its config option.
Also make NMI control dependent on X86 as it is specific to that
platform.
Rather than looking for a node labeled "ibecc", the EDAC shell code
now simply requires that a chosen entry for "zephyr,edac" be present to
point to the desired device. The Intel Elkhart Lake DTS has been updated
to add this alias.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an EDAC driver for the Synopsys DDR memory controller, used in the
Xilinx MPSoC (ZynqMP) devices, to allow monitoring for ECC errors.
Note that currently only the compatible string used for the ZynqMP
(shared with Linux) is currently supported. Support for other Synopsys
core implementations can be added in the future.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
When reconfiguring the SSP, some changes do not immediately take effect
in particular changes to the clock polarity are not applied. Disabling
and re-enabling the SSP forces the new configuration to take effect
immediately.
Signed-off-by: George Norton <george_norton_uk@hotmail.com>
