The clock-frequency value in dtsi can be used to change
the bus frequency for rts5912 driver and
it support in the range between 15000 to 50000000.
Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
mcux_eps_interval is added as the new member of
uhc_mcux_data. It is used to save endpoint's
original interval value and can be compared
with xfer->interval.
Signed-off-by: Aiden Hu <weiwei.hu@nxp.com>
`choice STM32_LTDC_PIXEL_FORMAT` is already enclosed in an `if STM32_LTDC`
block - there is no need to add a `depends on` on this option.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
If several ADCs are used and share a common clock property (for example
ADC1/2 prescaler value on STM32U5), none of them should be enabled when
the clock is set.
To that end, make sure to disable ADC at the end of the initialization,
it will be enabled later when necessary anyway.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Ensure that data is transmitted before logging
as it could cause lockups in some setups.
Also update i2c_stm32_v2_rtio.c to match
this behavior to always send data in order to avoid
the I2C to lockup.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Add support for RTC calibration API by implementing set_calibration
and get_calibration functions. RV3028 RTC supports calibration to
adjust for errors from +243.2 ppm to -244.1 ppm in steps of 0.9537 ppm.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
When calculating the PLL output rate, take into account the fractional part
of the PLL multiplier N. This ensures that the calculated output frequency
is correct.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The bmm350_prep_reg_write_rtio_async() function was incorrectly using two
separate SQEs for register writes, creating two distinct I2C transactions:
Before: [START][ADDR+W][REG][RESTART] + [START][ADDR+W][DATA][STOP]
Change to use a single SQE for the entire write:
After: [START][ADDR+W][REG][DATA][STOP]
Signed-off-by: Trond F. Christiansen <trond.christiansen@nordicsemi.no>
Few functions have been corrected to the SSED attachment for the
MCXW72 as leader :
- mcxw_tx():
tx_frame.tx_delay corrected.
Adjusts the scheduled transmission start time to account for the SHR
duration (160us) as requested by the OpenThread radio API.
- mcxw_rx_thread():
Stores the frame counter and key ID from a
security-enabled enhanced ACK into the received packet's metadata
for cryptographic verification.
- mcxw_tx_started() added:
Notifies the registered event handler that a frame transmission has
started, passing the frame buffer as context.
- pd_mac_sap_handler(): timestamp corrected
- mcxw_configure(): IEEE802154_CONFIG_EVENT_HANDLER case updated
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
Add pwm driver using tc g1 peripheral.
Adds the support for generating pwm output.
Supports 8-bit, 16-bit and 32-bit mode of tc peripheral
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Add a simple function that exposes the airtime of a packet of a given
length.
Use the new internal implementations of the airtime function when
calculating TX durations inside the send functions to reduce code
duplication on a complex function.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The current implementation has a bug in the calculation of
tile offsets, causing them to be calculated incorrectly.
This is particularly evident when there are fractional rows or columns.
Also, there was an assertion that assumed vtiled.
The logic has become too complicated,
so we'll reimplement to simplify this.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Ensure that pins configured as inputs are driven high in the port
output register, consistent with open-drain operation. This prevents
inputs from being driven low unintentionally and aligns behavior
with hardware expectations.
Signed-off-by: Josia Strack <j.strack98@gmail.com>
Move the no propagation segment configuration and prop_seg must be 0
logic from the general timing configuration to only apply within the
CAN FD specific sections.
This ensures that for classic CAN mode or platfrom without enhanced
bit timing, prop_seg is always decremented by 1.
The previous implementation incorrectly applied the enhanced bit timing
logic to classic CAN mode, which could cause timing misconfiguration
on devices with enhanced bit timing register support when operating in
classic CAN mode.
Fixes#99746
Signed-off-by: William Tang <william.tang@nxp.com>
Using "pkt->out_len" as the output length of "psa_cipher_[en|de]crypt"
caused a crash in RISCV 64 bits platforms due to misaligned address
access.
The solution is to add a temporary value on the stack to store this lenght
and only after the [en|de]cryption copy it to "pkt->out_len".
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
The reset pin, like most reset pins, is active low. Fix the driver to
treat it as active low and simplify the pin control logic while at it.
Fix all current boards using the wrong pin definition and add a note for
out of tree users.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Support CRC16 and CRC32 variants; return -ENOTSUP for unsupported types.
Use kCrcBits16/kCrcBits32 and complementChecksum for IEEE CRC-32.
Stream data via CRC_WriteData() and fetch results via
CRC_Get16bitResult()/CRC_Get32bitResult().
Provide simple thread-safety with a semaphore.
Work around the name clash between Zephyr's typedef crc_result_t and the
MCUX enum name by temporarily redefining crc_result_t around fsl_crc.h
include in this TU.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Most of Espressif drivers ISRs are already running in IRAM area, except
those in this PR. Move ISRs accordingly so we avoid any
interrupt miss when cache is disabled.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Call pm_policy_device_power_lock_put/pm_policy_device_power_lock_get
to coordinate with system level power modes.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Adds mag-gain-correction DT property, which sets the magnetic gain
correction value. Previously a property to select the channel for gain
correction existed, but there was no way to configure the correction
value itself.
Signed-off-by: Marek Maškarinec <marek.maskarinec@hardwario.com>
The original driver is only feasible for M-Core, but for Cortex-A Core,
it need to do MMU mapping to map physical address to virtual address,
to the main update is to add MMIO mapping in this driver, and all the
register access should use virtual address.
Replace direct base address access with DEVICE_MMIO_NAMED_* macros
to provide better memory mapping abstraction and improve platform
portability.
This change:
- Adds DEVICE_MMIO_NAMED_ROM/RAM to config and data structures
- Maps the register base address during driver pre-initialization
- Updates all base address references to use DEVICE_MMIO_NAMED_GET
- Maintains backward compatibility with existing functionality
The DEVICE_MMIO API provides a standardized way to handle memory-mapped
registers across different platforms and memory protection schemes.
Signed-off-by: Jason He <jason.he_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jony Zhang <jony.zhang@nxp.com>
Support device tree specified clock rates for USB controller and PHY.
Signed-off-by: Jason He <jason.he_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jony Zhang <jony.zhang@nxp.com>
Add USB_CLK and USB_PHY_CLK support for NXP EHCI controller on MIMX9352.
Signed-off-by: Jason He <jason.he_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jony Zhang <jony.zhang@nxp.com>
If the modem reboots or stops responding to AT commands while in
RUN_DIAL, AWAIT_REGISTERED, or CARRIER_ON, the modem_cellular state
machine could previously dead-end. Applications had to recover by
manually issuing device PM suspend/resume.
This change adds an internal recovery path: after repeated chat/script
failures in the states above, the driver resets the state to INIT, and
posts an immediate RESUME event. This allows the initialization sequence
to run again and restores connectivity, including after unexpected modem
reboots.
No API changes; behavior only differs in failure scenarios.
Signed-off-by: Tomas Gudelevičius <tomas.gudelevicius@draeger.com>
Add Kconfig option to skip or execute the verification of the ic
type. This adds a delay of 100ms to the initialization.
Signed-off-by: Matthias Alleman <matthias.alleman@basalte.be>
The sensor requires at least 94ms of delay before starting
communication after a reset. This is not mentioned in the
datasheet but is arbitrarily defined.
Signed-off-by: Matthias Alleman <matthias.alleman@basalte.be>
The GRTC timer, typically used as sys clock on newer nordic chips,
is currently tightly coupled to the CLOCK_CONTROL_NRF drivers though
not being dependent on it. The GRTC and its device driver is
independent from CLOCK_CONTROL, its clock requirements are managed
by hardware, based on its clock source selection.
This commit moves the clock source selection to the GRTC driver, and
removes the hard coupling to the CLOCK_CONTROL drivers. To preserve
backwards compatibility, if CLOCK_CONTROL_NRF_K32SRC_RC is selected,
GRTC will default to LFLPRC.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When EC reboot, pwm pins go back to default GPI mode.
After we set pin mode to pwm mode at init(), it would
output low, so LED will be light (LED is low-activated).
And until set_cycles() is called to set output high,
then LED will be turn off the light (PWM-LED flicker).
So add the property to set PWM channel init output level.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Currently, clk_div_factor is force to 1 if user request more than 110MHz.
However, in this case, gspi_siwx91x_get_divider() will never return 2 or
more, unless the input clock is >= 220MHz. The si91x is not designed for
such high clock frequency. So, this case has never been tested.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
In gspi_siwx91x_config(), clk_div_factor can't be < 1. Therefore, we can
remove the dead code.
This code has been tested with tests/drivers/spi/spi_loopback, with a PLL
clock configured to 160MHz and a bus clock to 80MHz with success. I have
not found the case where change in GSPI_CLK_CONFIG are required.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Until now, GSPI_DATA_SAMPLE_EDGE was enabled as soon as the user requested
> 40Mhz (even if the actual frequency was in fact 40Mhz). However, at 40MHz
and at 80MHz, use of GSPI_DATA_SAMPLE_EDGE generated read errors on the
last bit of the transaction:
Buffer contents are different:
[...],0xaa,0xaa,0xaa,0xaa,
vs:
[...],0xaa,0xaa,0xaa,0xab,
I have not found any case where GSPI_DATA_SAMPLE_EDGE is useful, so this
patch just remove this parameter.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
In functions requiring to lock/release resources, it is less error prone to
have only one exit point and user goto to manage errors.
The behavior of the new code is exactly identical to the initial one.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
