drivers: clock: add stm32n6 clock
Add STM32N6 clock driver. Supported clocks are LSE, LSI, HSE, HSI, PLL1-4, IC1-20, peripheral clock and CPU clock. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier
Benjamin Cabé
parent
bcad9cb891
commit
daeb2a8377
6 changed files with 1337 additions and 1 deletions
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@ -59,6 +59,8 @@ elseif(CONFIG_SOC_SERIES_STM32H7RSX)
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zephyr_library_sources(clock_stm32_ll_h7.c)
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elseif(CONFIG_SOC_SERIES_STM32H5X)
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zephyr_library_sources(clock_stm32_ll_h5.c)
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elseif(CONFIG_SOC_SERIES_STM32N6X)
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zephyr_library_sources(clock_stm32_ll_n6.c)
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elseif(CONFIG_SOC_SERIES_STM32U5X)
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zephyr_library_sources(clock_stm32_ll_u5.c)
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elseif(CONFIG_SOC_SERIES_STM32WB0X)
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@ -10,7 +10,8 @@ menuconfig CLOCK_CONTROL_STM32_CUBE
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default y
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select USE_STM32_LL_UTILS
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select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32H7X || \
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SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X)
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SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || \
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SOC_SERIES_STM32N6X)
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select RUNTIME_NMI if ($(dt_nodelabel_enabled,clk_hse) && \
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$(dt_nodelabel_has_prop,clk_hse,css-enabled))
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help
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950
drivers/clock_control/clock_stm32_ll_n6.c
Normal file
950
drivers/clock_control/clock_stm32_ll_n6.c
Normal file
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@ -0,0 +1,950 @@
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <stm32_ll_system.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/sys/util.h>
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/* Macros to fill up prescaler values */
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#define z_ic_src_pll(v) LL_RCC_ICCLKSOURCE_PLL ## v
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#define ic_src_pll(v) z_ic_src_pll(v)
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#define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v
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#define hsi_divider(v) z_hsi_divider(v)
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#define z_ahb_prescaler(v) LL_RCC_AHB_DIV_ ## v
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#define ahb_prescaler(v) z_ahb_prescaler(v)
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#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
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#define apb1_prescaler(v) z_apb1_prescaler(v)
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#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
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#define apb2_prescaler(v) z_apb2_prescaler(v)
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#define z_apb4_prescaler(v) LL_RCC_APB4_DIV_ ## v
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#define apb4_prescaler(v) z_apb4_prescaler(v)
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#define z_apb5_prescaler(v) LL_RCC_APB5_DIV_ ## v
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#define apb5_prescaler(v) z_apb5_prescaler(v)
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#define PLL1_ID 1
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#define PLL2_ID 2
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#define PLL3_ID 3
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#define PLL4_ID 4
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static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
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{
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return clock / prescaler;
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}
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__unused
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/** @brief returns the pll source frequency of given pll_id */
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static uint32_t get_pllsrc_frequency(int pll_id)
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{
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if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) ||
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(IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) ||
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(IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID) ||
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(IS_ENABLED(STM32_PLL4_SRC_HSI) && pll_id == PLL4_ID)) {
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return STM32_HSI_FREQ;
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} else if ((IS_ENABLED(STM32_PLL_SRC_HSE) && pll_id == PLL1_ID) ||
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(IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) ||
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(IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID) ||
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(IS_ENABLED(STM32_PLL4_SRC_HSE) && pll_id == PLL4_ID)) {
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return STM32_HSE_FREQ;
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}
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__ASSERT(0, "No PLL Source configured");
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return 0;
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}
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static uint32_t get_pllout_frequency(int pll_id)
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{
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uint32_t pllsrc_freq = get_pllsrc_frequency(pll_id);
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int pllm_div;
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int plln_mul;
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int pllout_div1;
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int pllout_div2;
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switch (pll_id) {
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#if defined(STM32_PLL1_ENABLED)
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case PLL1_ID:
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pllm_div = STM32_PLL1_M_DIVISOR;
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plln_mul = STM32_PLL1_N_MULTIPLIER;
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pllout_div1 = STM32_PLL1_P1_DIVISOR;
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pllout_div2 = STM32_PLL1_P2_DIVISOR;
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break;
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#endif /* STM32_PLL1_ENABLED */
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#if defined(STM32_PLL2_ENABLED)
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case PLL2_ID:
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pllm_div = STM32_PLL2_M_DIVISOR;
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plln_mul = STM32_PLL2_N_MULTIPLIER;
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pllout_div1 = STM32_PLL2_P1_DIVISOR;
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pllout_div2 = STM32_PLL2_P2_DIVISOR;
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break;
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#endif /* STM32_PLL2_ENABLED */
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#if defined(STM32_PLL3_ENABLED)
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case PLL3_ID:
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pllm_div = STM32_PLL3_M_DIVISOR;
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plln_mul = STM32_PLL3_N_MULTIPLIER;
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pllout_div1 = STM32_PLL3_P1_DIVISOR;
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pllout_div2 = STM32_PLL3_P2_DIVISOR;
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break;
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#endif /* STM32_PLL3_ENABLED */
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#if defined(STM32_PLL4_ENABLED)
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case PLL4_ID:
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pllm_div = STM32_PLL4_M_DIVISOR;
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plln_mul = STM32_PLL4_N_MULTIPLIER;
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pllout_div1 = STM32_PLL4_P1_DIVISOR;
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pllout_div2 = STM32_PLL4_P2_DIVISOR;
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break;
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#endif /* STM32_PLL4_ENABLED */
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default:
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__ASSERT(0, "No PLL configured");
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return 0;
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}
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__ASSERT_NO_MSG(pllm_div && pllout_div1 && pllout_div2);
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return (pllsrc_freq / pllm_div) * plln_mul / (pllout_div1 * pllout_div2);
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}
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__unused uint32_t get_icout_frequency(uint32_t icsrc, int div)
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{
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if (icsrc == LL_RCC_ICCLKSOURCE_PLL1) {
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return get_pllout_frequency(PLL1_ID) / div;
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} else if (icsrc == LL_RCC_ICCLKSOURCE_PLL2) {
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return get_pllout_frequency(PLL2_ID) / div;
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} else if (icsrc == LL_RCC_ICCLKSOURCE_PLL3) {
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return get_pllout_frequency(PLL3_ID) / div;
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} else if (icsrc == LL_RCC_ICCLKSOURCE_PLL4) {
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return get_pllout_frequency(PLL4_ID) / div;
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}
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__ASSERT(0, "No IC Source configured");
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return 0;
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}
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static uint32_t get_sysclk_frequency(void)
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{
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#if defined(STM32_SYSCLK_SRC_HSE)
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return STM32_HSE_FREQ;
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#elif defined(STM32_SYSCLK_SRC_HSI)
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return STM32_HSI_FREQ;
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#elif defined(STM32_SYSCLK_SRC_IC2)
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return get_icout_frequency(LL_RCC_IC2_GetSource(), STM32_IC2_DIV);
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#else
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__ASSERT(0, "No SYSCLK Source configured");
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return 0;
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#endif
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}
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/** @brief Verifies clock is part of active clock configuration */
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static int enabled_clock(uint32_t src_clk)
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{
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if ((src_clk == STM32_SRC_SYSCLK) ||
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((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
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((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
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((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
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((src_clk == STM32_SRC_HSI) && IS_ENABLED(STM32_HSI_ENABLED)) ||
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((src_clk == STM32_SRC_PLL1) && IS_ENABLED(STM32_PLL1_ENABLED)) ||
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((src_clk == STM32_SRC_PLL2) && IS_ENABLED(STM32_PLL2_ENABLED)) ||
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((src_clk == STM32_SRC_PLL3) && IS_ENABLED(STM32_PLL3_ENABLED)) ||
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((src_clk == STM32_SRC_PLL4) && IS_ENABLED(STM32_PLL4_ENABLED)) ||
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((src_clk == STM32_SRC_CKPER) && IS_ENABLED(STM32_CKPER_ENABLED)) ||
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((src_clk == STM32_SRC_IC1) && IS_ENABLED(STM32_IC1_ENABLED)) ||
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((src_clk == STM32_SRC_IC2) && IS_ENABLED(STM32_IC2_ENABLED)) ||
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((src_clk == STM32_SRC_IC3) && IS_ENABLED(STM32_IC3_ENABLED)) ||
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((src_clk == STM32_SRC_IC4) && IS_ENABLED(STM32_IC4_ENABLED)) ||
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((src_clk == STM32_SRC_IC5) && IS_ENABLED(STM32_IC5_ENABLED)) ||
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((src_clk == STM32_SRC_IC6) && IS_ENABLED(STM32_IC6_ENABLED)) ||
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((src_clk == STM32_SRC_IC7) && IS_ENABLED(STM32_IC7_ENABLED)) ||
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((src_clk == STM32_SRC_IC8) && IS_ENABLED(STM32_IC8_ENABLED)) ||
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((src_clk == STM32_SRC_IC9) && IS_ENABLED(STM32_IC9_ENABLED)) ||
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((src_clk == STM32_SRC_IC10) && IS_ENABLED(STM32_IC10_ENABLED)) ||
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((src_clk == STM32_SRC_IC11) && IS_ENABLED(STM32_IC11_ENABLED)) ||
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((src_clk == STM32_SRC_IC12) && IS_ENABLED(STM32_IC12_ENABLED)) ||
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((src_clk == STM32_SRC_IC13) && IS_ENABLED(STM32_IC13_ENABLED)) ||
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((src_clk == STM32_SRC_IC14) && IS_ENABLED(STM32_IC14_ENABLED)) ||
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((src_clk == STM32_SRC_IC15) && IS_ENABLED(STM32_IC15_ENABLED)) ||
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((src_clk == STM32_SRC_IC16) && IS_ENABLED(STM32_IC16_ENABLED)) ||
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((src_clk == STM32_SRC_IC17) && IS_ENABLED(STM32_IC17_ENABLED)) ||
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((src_clk == STM32_SRC_IC18) && IS_ENABLED(STM32_IC18_ENABLED)) ||
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((src_clk == STM32_SRC_IC19) && IS_ENABLED(STM32_IC19_ENABLED)) ||
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((src_clk == STM32_SRC_IC20) && IS_ENABLED(STM32_IC20_ENABLED))) {
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return 0;
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}
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return -ENOTSUP;
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}
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static inline int stm32_clock_control_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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/* Set Run clock */
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
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pclken->enr);
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/* Set Low Power clock */
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus + STM32_CLOCK_LP_BUS_SHIFT,
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pclken->enr);
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return 0;
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}
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static inline int stm32_clock_control_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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/* Clear Run clock */
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
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pclken->enr);
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/* Clear Low Power clock */
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus + STM32_CLOCK_LP_BUS_SHIFT,
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pclken->enr);
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return 0;
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}
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static inline int stm32_clock_control_configure(const struct device *dev,
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clock_control_subsys_t sub_system,
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void *data)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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int err;
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ARG_UNUSED(dev);
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ARG_UNUSED(data);
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err = enabled_clock(pclken->bus);
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if (err < 0) {
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/* Attempt to configure a src clock not available or not valid */
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return err;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
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STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
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STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sys,
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uint32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sys);
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uint32_t sys_clock = get_sysclk_frequency();
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uint32_t ahb_clock = get_bus_clock(sys_clock, STM32_AHB_PRESCALER);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_SRC_SYSCLK:
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*rate = get_sysclk_frequency();
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break;
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case STM32_CLOCK_BUS_AHB1:
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case STM32_CLOCK_BUS_AHB2:
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case STM32_CLOCK_BUS_AHB3:
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case STM32_CLOCK_BUS_AHB4:
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case STM32_CLOCK_BUS_AHB5:
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*rate = ahb_clock;
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break;
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case STM32_CLOCK_BUS_APB1:
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case STM32_CLOCK_BUS_APB1_2:
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*rate = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
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break;
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case STM32_CLOCK_BUS_APB2:
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*rate = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
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break;
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case STM32_CLOCK_BUS_APB4:
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case STM32_CLOCK_BUS_APB4_2:
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*rate = get_bus_clock(ahb_clock, STM32_APB4_PRESCALER);
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break;
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case STM32_CLOCK_BUS_APB5:
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*rate = get_bus_clock(ahb_clock, STM32_APB5_PRESCALER);
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break;
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#if defined(STM32_LSE_ENABLED)
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case STM32_SRC_LSE:
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*rate = STM32_LSE_FREQ;
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break;
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#endif /* STM32_LSE_ENABLED */
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#if defined(STM32_LSI_ENABLED)
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case STM32_SRC_LSI:
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*rate = STM32_LSI_FREQ;
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break;
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#endif /* STM32_LSI_ENABLED */
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#if defined(STM32_HSE_ENABLED)
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case STM32_SRC_HSE:
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*rate = STM32_HSE_FREQ;
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break;
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#endif /* STM32_HSE_ENABLED */
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#if defined(STM32_HSI_ENABLED)
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case STM32_SRC_HSI:
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*rate = STM32_HSI_FREQ;
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break;
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#endif /* STM32_HSI_ENABLED */
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case STM32_SRC_PLL1:
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*rate = get_pllout_frequency(PLL1_ID);
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break;
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case STM32_SRC_PLL2:
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*rate = get_pllout_frequency(PLL2_ID);
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break;
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case STM32_SRC_PLL3:
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*rate = get_pllout_frequency(PLL3_ID);
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break;
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case STM32_SRC_PLL4:
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*rate = get_pllout_frequency(PLL4_ID);
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break;
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#if defined(STM32_CKPER_ENABLED)
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case STM32_SRC_CKPER:
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*rate = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
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break;
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#endif /* STM32_CKPER_ENABLED */
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#if defined(STM32_IC1_ENABLED)
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case STM32_SRC_IC1:
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*rate = get_icout_frequency(LL_RCC_IC1_GetSource(), STM32_IC1_DIV);
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break;
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#endif /* STM32_IC1_ENABLED */
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#if defined(STM32_IC2_ENABLED)
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case STM32_SRC_IC2:
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*rate = get_icout_frequency(LL_RCC_IC2_GetSource(), STM32_IC2_DIV);
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break;
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#endif /* STM32_IC2_ENABLED */
|
||||
#if defined(STM32_IC3_ENABLED)
|
||||
case STM32_SRC_IC3:
|
||||
*rate = get_icout_frequency(LL_RCC_IC3_GetSource(), STM32_IC3_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC3_ENABLED */
|
||||
#if defined(STM32_IC4_ENABLED)
|
||||
case STM32_SRC_IC4:
|
||||
*rate = get_icout_frequency(LL_RCC_IC4_GetSource(), STM32_IC4_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC4_ENABLED */
|
||||
#if defined(STM32_IC5_ENABLED)
|
||||
case STM32_SRC_IC5:
|
||||
*rate = get_icout_frequency(LL_RCC_IC5_GetSource(), STM32_IC5_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC5_ENABLED */
|
||||
#if defined(STM32_IC6_ENABLED)
|
||||
case STM32_SRC_IC6:
|
||||
*rate = get_icout_frequency(LL_RCC_IC6_GetSource(), STM32_IC6_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC6_ENABLED */
|
||||
#if defined(STM32_IC7_ENABLED)
|
||||
case STM32_SRC_IC7:
|
||||
*rate = get_icout_frequency(LL_RCC_IC7_GetSource(), STM32_IC7_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC7_ENABLED */
|
||||
#if defined(STM32_IC8_ENABLED)
|
||||
case STM32_SRC_IC8:
|
||||
*rate = get_icout_frequency(LL_RCC_IC8_GetSource(), STM32_IC8_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC8_ENABLED */
|
||||
#if defined(STM32_IC9_ENABLED)
|
||||
case STM32_SRC_IC9:
|
||||
*rate = get_icout_frequency(LL_RCC_IC9_GetSource(), STM32_IC9_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC9_ENABLED */
|
||||
#if defined(STM32_IC10_ENABLED)
|
||||
case STM32_SRC_IC10:
|
||||
*rate = get_icout_frequency(LL_RCC_IC10_GetSource(), STM32_IC10_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC10_ENABLED */
|
||||
#if defined(STM32_IC11_ENABLED)
|
||||
case STM32_SRC_IC11:
|
||||
*rate = get_icout_frequency(LL_RCC_IC11_GetSource(), STM32_IC11_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC11_ENABLED */
|
||||
#if defined(STM32_IC12_ENABLED)
|
||||
case STM32_SRC_IC12:
|
||||
*rate = get_icout_frequency(LL_RCC_IC12_GetSource(), STM32_IC12_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC12_ENABLED */
|
||||
#if defined(STM32_IC13_ENABLED)
|
||||
case STM32_SRC_IC13:
|
||||
*rate = get_icout_frequency(LL_RCC_IC13_GetSource(), STM32_IC13_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC13_ENABLED */
|
||||
#if defined(STM32_IC14_ENABLED)
|
||||
case STM32_SRC_IC14:
|
||||
*rate = get_icout_frequency(LL_RCC_IC14_GetSource(), STM32_IC14_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC14_ENABLED */
|
||||
#if defined(STM32_IC15_ENABLED)
|
||||
case STM32_SRC_IC15:
|
||||
*rate = get_icout_frequency(LL_RCC_IC15_GetSource(), STM32_IC15_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC15_ENABLED */
|
||||
#if defined(STM32_IC16_ENABLED)
|
||||
case STM32_SRC_IC16:
|
||||
*rate = get_icout_frequency(LL_RCC_IC16_GetSource(), STM32_IC16_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC16_ENABLED */
|
||||
#if defined(STM32_IC17_ENABLED)
|
||||
case STM32_SRC_IC17:
|
||||
*rate = get_icout_frequency(LL_RCC_IC17_GetSource(), STM32_IC17_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC17_ENABLED */
|
||||
#if defined(STM32_IC18_ENABLED)
|
||||
case STM32_SRC_IC18:
|
||||
*rate = get_icout_frequency(LL_RCC_IC18_GetSource(), STM32_IC18_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC18_ENABLED */
|
||||
#if defined(STM32_IC19_ENABLED)
|
||||
case STM32_SRC_IC19:
|
||||
*rate = get_icout_frequency(LL_RCC_IC19_GetSource(), STM32_IC19_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC19_ENABLED */
|
||||
#if defined(STM32_IC20_ENABLED)
|
||||
case STM32_SRC_IC20:
|
||||
*rate = get_icout_frequency(LL_RCC_IC20_GetSource(), STM32_IC20_DIV);
|
||||
break;
|
||||
#endif /* STM32_IC20_ENABLED */
|
||||
default:
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
if (pclken->div) {
|
||||
*rate /= (pclken->div + 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static DEVICE_API(clock_control, stm32_clock_control_api) = {
|
||||
.on = stm32_clock_control_on,
|
||||
.off = stm32_clock_control_off,
|
||||
.get_rate = stm32_clock_control_get_subsys_rate,
|
||||
.configure = stm32_clock_control_configure,
|
||||
};
|
||||
|
||||
/*
|
||||
* Unconditionally switch the system clock source to HSI.
|
||||
*/
|
||||
__unused
|
||||
static void stm32_clock_switch_to_hsi(void)
|
||||
{
|
||||
/* Enable HSI if not enabled */
|
||||
if (LL_RCC_HSI_IsReady() != 1) {
|
||||
/* Enable HSI */
|
||||
LL_RCC_HSI_Enable();
|
||||
while (LL_RCC_HSI_IsReady() != 1) {
|
||||
/* Wait for HSI ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Set HSI as SYSCLCK source */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
|
||||
}
|
||||
|
||||
LL_RCC_SetCpuClkSource(LL_RCC_CPU_CLKSOURCE_HSI);
|
||||
while (LL_RCC_GetCpuClkSource() != LL_RCC_CPU_CLKSOURCE_STATUS_HSI) {
|
||||
}
|
||||
}
|
||||
|
||||
static int set_up_ics(void)
|
||||
{
|
||||
#if defined(STM32_IC1_ENABLED)
|
||||
LL_RCC_IC1_SetSource(ic_src_pll(STM32_IC1_PLL_SRC));
|
||||
LL_RCC_IC1_SetDivider(STM32_IC1_DIV);
|
||||
LL_RCC_IC1_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC2_ENABLED)
|
||||
LL_RCC_IC2_SetSource(ic_src_pll(STM32_IC2_PLL_SRC));
|
||||
LL_RCC_IC2_SetDivider(STM32_IC2_DIV);
|
||||
LL_RCC_IC2_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC3_ENABLED)
|
||||
LL_RCC_IC3_SetSource(ic_src_pll(STM32_IC3_PLL_SRC));
|
||||
LL_RCC_IC3_SetDivider(STM32_IC3_DIV);
|
||||
LL_RCC_IC3_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC4_ENABLED)
|
||||
LL_RCC_IC4_SetSource(ic_src_pll(STM32_IC4_PLL_SRC));
|
||||
LL_RCC_IC4_SetDivider(STM32_IC4_DIV);
|
||||
LL_RCC_IC4_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC5_ENABLED)
|
||||
LL_RCC_IC5_SetSource(ic_src_pll(STM32_IC5_PLL_SRC));
|
||||
LL_RCC_IC5_SetDivider(STM32_IC5_DIV);
|
||||
LL_RCC_IC5_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC6_ENABLED)
|
||||
LL_RCC_IC6_SetSource(ic_src_pll(STM32_IC6_PLL_SRC));
|
||||
LL_RCC_IC6_SetDivider(STM32_IC6_DIV);
|
||||
LL_RCC_IC6_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC7_ENABLED)
|
||||
LL_RCC_IC7_SetSource(ic_src_pll(STM32_IC7_PLL_SRC));
|
||||
LL_RCC_IC7_SetDivider(STM32_IC7_DIV);
|
||||
LL_RCC_IC7_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC8_ENABLED)
|
||||
LL_RCC_IC8_SetSource(ic_src_pll(STM32_IC8_PLL_SRC));
|
||||
LL_RCC_IC8_SetDivider(STM32_IC8_DIV);
|
||||
LL_RCC_IC8_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC9_ENABLED)
|
||||
LL_RCC_IC9_SetSource(ic_src_pll(STM32_IC9_PLL_SRC));
|
||||
LL_RCC_IC9_SetDivider(STM32_IC9_DIV);
|
||||
LL_RCC_IC9_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC10_ENABLED)
|
||||
LL_RCC_IC10_SetSource(ic_src_pll(STM32_IC10_PLL_SRC));
|
||||
LL_RCC_IC10_SetDivider(STM32_IC10_DIV);
|
||||
LL_RCC_IC10_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC11_ENABLED)
|
||||
LL_RCC_IC11_SetSource(ic_src_pll(STM32_IC11_PLL_SRC));
|
||||
LL_RCC_IC11_SetDivider(STM32_IC11_DIV);
|
||||
LL_RCC_IC11_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC12_ENABLED)
|
||||
LL_RCC_IC12_SetSource(ic_src_pll(STM32_IC12_PLL_SRC));
|
||||
LL_RCC_IC12_SetDivider(STM32_IC12_DIV);
|
||||
LL_RCC_IC12_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC13_ENABLED)
|
||||
LL_RCC_IC13_SetSource(ic_src_pll(STM32_IC13_PLL_SRC));
|
||||
LL_RCC_IC13_SetDivider(STM32_IC13_DIV);
|
||||
LL_RCC_IC13_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC14_ENABLED)
|
||||
LL_RCC_IC14_SetSource(ic_src_pll(STM32_IC14_PLL_SRC));
|
||||
LL_RCC_IC14_SetDivider(STM32_IC14_DIV);
|
||||
LL_RCC_IC14_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC15_ENABLED)
|
||||
LL_RCC_IC15_SetSource(ic_src_pll(STM32_IC15_PLL_SRC));
|
||||
LL_RCC_IC15_SetDivider(STM32_IC15_DIV);
|
||||
LL_RCC_IC15_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC16_ENABLED)
|
||||
LL_RCC_IC16_SetSource(ic_src_pll(STM32_IC16_PLL_SRC));
|
||||
LL_RCC_IC16_SetDivider(STM32_IC16_DIV);
|
||||
LL_RCC_IC16_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC17_ENABLED)
|
||||
LL_RCC_IC17_SetSource(ic_src_pll(STM32_IC17_PLL_SRC));
|
||||
LL_RCC_IC17_SetDivider(STM32_IC17_DIV);
|
||||
LL_RCC_IC17_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC18_ENABLED)
|
||||
LL_RCC_IC18_SetSource(ic_src_pll(STM32_IC18_PLL_SRC));
|
||||
LL_RCC_IC18_SetDivider(STM32_IC18_DIV);
|
||||
LL_RCC_IC18_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC19_ENABLED)
|
||||
LL_RCC_IC19_SetSource(ic_src_pll(STM32_IC19_PLL_SRC));
|
||||
LL_RCC_IC19_SetDivider(STM32_IC19_DIV);
|
||||
LL_RCC_IC19_Enable();
|
||||
#endif
|
||||
|
||||
#if defined(STM32_IC20_ENABLED)
|
||||
LL_RCC_IC20_SetSource(ic_src_pll(STM32_IC20_PLL_SRC));
|
||||
LL_RCC_IC20_SetDivider(STM32_IC20_DIV);
|
||||
LL_RCC_IC20_Enable();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int set_up_plls(void)
|
||||
{
|
||||
#if defined(STM32_PLL1_ENABLED)
|
||||
/* TODO: Do not switch systematically on HSI if not needed */
|
||||
stm32_clock_switch_to_hsi();
|
||||
|
||||
LL_RCC_PLL1_Disable();
|
||||
|
||||
/* Configure PLL source : Can be HSE, HSI, MSI */
|
||||
if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_HSE);
|
||||
} else if (IS_ENABLED(STM32_PLL_SRC_MSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_MSI);
|
||||
} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_HSI);
|
||||
} else {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Disable PLL1 modulation spread-spectrum */
|
||||
LL_RCC_PLL1_DisableModulationSpreadSpectrum();
|
||||
|
||||
/* Disable bypass to use the PLL VCO */
|
||||
if (LL_RCC_PLL1_IsEnabledBypass()) {
|
||||
LL_RCC_PLL1_DisableBypass();
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL1_SetM(STM32_PLL1_M_DIVISOR);
|
||||
LL_RCC_PLL1_SetN(STM32_PLL1_N_MULTIPLIER);
|
||||
LL_RCC_PLL1_SetP1(STM32_PLL1_P1_DIVISOR);
|
||||
LL_RCC_PLL1_SetP2(STM32_PLL1_P2_DIVISOR);
|
||||
|
||||
/* Disable fractional mode */
|
||||
LL_RCC_PLL1_SetFRACN(0);
|
||||
LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum();
|
||||
|
||||
LL_RCC_PLL1_AssertModulationSpreadSpectrumReset();
|
||||
|
||||
/* Enable post division */
|
||||
if (!LL_RCC_PLL1P_IsEnabled()) {
|
||||
LL_RCC_PLL1P_Enable();
|
||||
}
|
||||
|
||||
LL_RCC_PLL1_Enable();
|
||||
while (LL_RCC_PLL1_IsReady() != 1U) {
|
||||
}
|
||||
#endif /* STM32_PLL1_ENABLED */
|
||||
|
||||
#if defined(STM32_PLL2_ENABLED)
|
||||
LL_RCC_PLL2_Disable();
|
||||
|
||||
/* Configure PLL source : Can be HSE, HSI, MSI */
|
||||
if (IS_ENABLED(STM32_PLL2_SRC_HSE)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL2_SetSource(LL_RCC_PLLSOURCE_HSE);
|
||||
} else if (IS_ENABLED(STM32_PLL2_SRC_MSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL2_SetSource(LL_RCC_PLLSOURCE_MSI);
|
||||
} else if (IS_ENABLED(STM32_PLL2_SRC_HSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL2_SetSource(LL_RCC_PLLSOURCE_HSI);
|
||||
} else {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Disable PLL2 modulation spread-spectrum */
|
||||
LL_RCC_PLL2_DisableModulationSpreadSpectrum();
|
||||
|
||||
/* Disable bypass to use the PLL VCO */
|
||||
if (LL_RCC_PLL2_IsEnabledBypass()) {
|
||||
LL_RCC_PLL2_DisableBypass();
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR);
|
||||
LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
|
||||
LL_RCC_PLL2_SetP1(STM32_PLL2_P1_DIVISOR);
|
||||
LL_RCC_PLL2_SetP2(STM32_PLL2_P2_DIVISOR);
|
||||
|
||||
/* Disable fractional mode */
|
||||
LL_RCC_PLL2_SetFRACN(0);
|
||||
LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum();
|
||||
|
||||
LL_RCC_PLL2_AssertModulationSpreadSpectrumReset();
|
||||
|
||||
/* Enable post division */
|
||||
if (!LL_RCC_PLL2P_IsEnabled()) {
|
||||
LL_RCC_PLL2P_Enable();
|
||||
}
|
||||
|
||||
LL_RCC_PLL2_Enable();
|
||||
while (LL_RCC_PLL2_IsReady() != 1U) {
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32_PLL3_ENABLED)
|
||||
LL_RCC_PLL3_Disable();
|
||||
|
||||
/* Configure PLL source : Can be HSE, HSI, MSIS */
|
||||
if (IS_ENABLED(STM32_PLL3_SRC_HSE)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL3_SetSource(LL_RCC_PLLSOURCE_HSE);
|
||||
} else if (IS_ENABLED(STM32_PLL3_SRC_MSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL3_SetSource(LL_RCC_PLLSOURCE_MSI);
|
||||
} else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL3_SetSource(LL_RCC_PLLSOURCE_HSI);
|
||||
} else {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Disable PLL3 modulation spread-spectrum */
|
||||
LL_RCC_PLL3_DisableModulationSpreadSpectrum();
|
||||
|
||||
/* Disable bypass to use the PLL VCO */
|
||||
if (LL_RCC_PLL3_IsEnabledBypass()) {
|
||||
LL_RCC_PLL3_DisableBypass();
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR);
|
||||
LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
|
||||
LL_RCC_PLL3_SetP1(STM32_PLL3_P1_DIVISOR);
|
||||
LL_RCC_PLL3_SetP2(STM32_PLL3_P2_DIVISOR);
|
||||
|
||||
/* Disable fractional mode */
|
||||
LL_RCC_PLL3_SetFRACN(0);
|
||||
LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum();
|
||||
|
||||
LL_RCC_PLL3_AssertModulationSpreadSpectrumReset();
|
||||
|
||||
/* Enable post division */
|
||||
if (!LL_RCC_PLL3P_IsEnabled()) {
|
||||
LL_RCC_PLL3P_Enable();
|
||||
}
|
||||
|
||||
LL_RCC_PLL3_Enable();
|
||||
while (LL_RCC_PLL3_IsReady() != 1U) {
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32_PLL4_ENABLED)
|
||||
LL_RCC_PLL4_Disable();
|
||||
|
||||
/* Configure PLL source : Can be HSE, HSI, MSIS */
|
||||
if (IS_ENABLED(STM32_PLL4_SRC_HSE)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL4_SetSource(LL_RCC_PLLSOURCE_HSE);
|
||||
} else if (IS_ENABLED(STM32_PLL4_SRC_MSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL4_SetSource(LL_RCC_PLLSOURCE_MSI);
|
||||
} else if (IS_ENABLED(STM32_PLL4_SRC_HSI)) {
|
||||
/* Main PLL configuration and activation */
|
||||
LL_RCC_PLL4_SetSource(LL_RCC_PLLSOURCE_HSI);
|
||||
} else {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Disable PLL4 modulation spread-spectrum */
|
||||
LL_RCC_PLL4_DisableModulationSpreadSpectrum();
|
||||
|
||||
/* Disable bypass to use the PLL VCO */
|
||||
if (LL_RCC_PLL4_IsEnabledBypass()) {
|
||||
LL_RCC_PLL4_DisableBypass();
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL4_SetM(STM32_PLL4_M_DIVISOR);
|
||||
LL_RCC_PLL4_SetN(STM32_PLL4_N_MULTIPLIER);
|
||||
LL_RCC_PLL4_SetP1(STM32_PLL4_P1_DIVISOR);
|
||||
LL_RCC_PLL4_SetP2(STM32_PLL4_P2_DIVISOR);
|
||||
|
||||
/* Disable fractional mode */
|
||||
LL_RCC_PLL4_SetFRACN(0);
|
||||
LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum();
|
||||
|
||||
LL_RCC_PLL4_AssertModulationSpreadSpectrumReset();
|
||||
|
||||
/* Enable post division */
|
||||
if (!LL_RCC_PLL4P_IsEnabled()) {
|
||||
LL_RCC_PLL4P_Enable();
|
||||
}
|
||||
|
||||
LL_RCC_PLL4_Enable();
|
||||
while (LL_RCC_PLL4_IsReady() != 1U) {
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void set_up_fixed_clock_sources(void)
|
||||
{
|
||||
if (IS_ENABLED(STM32_HSE_ENABLED)) {
|
||||
/* Check if need to enable HSE bypass feature or not */
|
||||
if (IS_ENABLED(STM32_HSE_BYPASS)) {
|
||||
LL_RCC_HSE_EnableBypass();
|
||||
} else {
|
||||
LL_RCC_HSE_DisableBypass();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_HSE_DIV2)) {
|
||||
LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
|
||||
} else {
|
||||
LL_RCC_HSE_SelectHSEAsDiv2Clock();
|
||||
}
|
||||
|
||||
/* Enable HSE */
|
||||
LL_RCC_HSE_Enable();
|
||||
while (LL_RCC_HSE_IsReady() != 1) {
|
||||
/* Wait for HSE ready */
|
||||
}
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_HSI_ENABLED)) {
|
||||
/* Enable HSI oscillator */
|
||||
LL_RCC_HSI_Enable();
|
||||
while (LL_RCC_HSI_IsReady() != 1) {
|
||||
}
|
||||
/* HSI divider configuration */
|
||||
LL_RCC_HSI_SetDivider(hsi_divider(STM32_HSI_DIVISOR));
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_LSE_ENABLED)) {
|
||||
/* Enable the power interface clock */
|
||||
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
|
||||
|
||||
if (!LL_PWR_IsEnabledBkUpAccess()) {
|
||||
/* Enable write access to Backup domain */
|
||||
LL_PWR_EnableBkUpAccess();
|
||||
while (!LL_PWR_IsEnabledBkUpAccess()) {
|
||||
/* Wait for Backup domain access */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure driving capability */
|
||||
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_LSECFGR_LSEDRV_Pos);
|
||||
|
||||
if (IS_ENABLED(STM32_LSE_BYPASS)) {
|
||||
/* Configure LSE bypass */
|
||||
LL_RCC_LSE_EnableBypass();
|
||||
}
|
||||
|
||||
/* Enable LSE Oscillator */
|
||||
LL_RCC_LSE_Enable();
|
||||
/* Wait for LSE ready */
|
||||
while (!LL_RCC_LSE_IsReady()) {
|
||||
}
|
||||
|
||||
LL_PWR_DisableBkUpAccess();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_LSI_ENABLED)) {
|
||||
/* Enable LSI oscillator */
|
||||
LL_RCC_LSI_Enable();
|
||||
while (LL_RCC_LSI_IsReady() != 1) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int stm32_clock_control_init(const struct device *dev)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
/* For now, enable clocks (including low_power ones) of all RAM */
|
||||
uint32_t all_ram = LL_MEM_AXISRAM1 | LL_MEM_AXISRAM2 | LL_MEM_AXISRAM3 | LL_MEM_AXISRAM4 |
|
||||
LL_MEM_AXISRAM5 | LL_MEM_AXISRAM6 | LL_MEM_AHBSRAM1 | LL_MEM_AHBSRAM2 |
|
||||
LL_MEM_BKPSRAM | LL_MEM_FLEXRAM | LL_MEM_CACHEAXIRAM | LL_MEM_VENCRAM;
|
||||
LL_MEM_EnableClock(all_ram);
|
||||
LL_MEM_EnableClockLowPower(all_ram);
|
||||
|
||||
/* Set up individual enabled clocks */
|
||||
set_up_fixed_clock_sources();
|
||||
|
||||
/* Set up PLLs */
|
||||
r = set_up_plls();
|
||||
if (r < 0) {
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Preset the prescalers prior to chosing SYSCLK */
|
||||
/* Prevents APB clock to go over limits */
|
||||
/* Set buses (AHB, APB1, APB2, APB4 & APB5) prescalers */
|
||||
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER));
|
||||
LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
|
||||
LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));
|
||||
LL_RCC_SetAPB4Prescaler(apb4_prescaler(STM32_APB4_PRESCALER));
|
||||
LL_RCC_SetAPB5Prescaler(apb5_prescaler(STM32_APB5_PRESCALER));
|
||||
|
||||
if (IS_ENABLED(STM32_CKPER_ENABLED)) {
|
||||
LL_MISC_EnableClock(LL_PER);
|
||||
LL_MISC_EnableClockLowPower(LL_PER);
|
||||
while (LL_MISC_IsEnabledClock(LL_PER) != 1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* Set up ICs */
|
||||
r = set_up_ics();
|
||||
if (r < 0) {
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Set up sys clock */
|
||||
if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {
|
||||
/* Set sysclk source to HSE */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
|
||||
while (LL_RCC_GetSysClkSource() !=
|
||||
LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
|
||||
}
|
||||
} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
|
||||
/* Set sysclk source to HSI */
|
||||
stm32_clock_switch_to_hsi();
|
||||
} else if (IS_ENABLED(STM32_SYSCLK_SRC_IC2)) {
|
||||
/* Set sysclk source to IC2 */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11);
|
||||
while (LL_RCC_GetSysClkSource() !=
|
||||
LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11) {
|
||||
}
|
||||
} else {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Update CMSIS variable */
|
||||
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCC device, note that priority is intentionally set to 1 so
|
||||
* that the device init runs just after SOC init
|
||||
*/
|
||||
DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
|
||||
&stm32_clock_control_init,
|
||||
NULL,
|
||||
NULL, NULL,
|
||||
PRE_KERNEL_1,
|
||||
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
|
||||
&stm32_clock_control_api);
|
||||
|
|
@ -53,6 +53,8 @@
|
|||
#include <zephyr/dt-bindings/clock/stm32h7_clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
|
||||
#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_STM32N6X)
|
||||
#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_STM32U0X)
|
||||
#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_STM32U5X)
|
||||
|
|
@ -72,6 +74,7 @@
|
|||
#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
|
||||
#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
|
||||
#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
|
||||
#define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
|
||||
#define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
|
||||
#define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
|
||||
#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
|
||||
|
|
@ -141,6 +144,9 @@
|
|||
#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
|
||||
#define STM32_SYSCLK_SRC_CSI 1
|
||||
#endif
|
||||
#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
|
||||
#define STM32_SYSCLK_SRC_IC2 1
|
||||
#endif
|
||||
|
||||
|
||||
/** PLL node related symbols */
|
||||
|
|
@ -252,6 +258,38 @@
|
|||
#define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
|
||||
#define STM32_PLL1_ENABLED 1
|
||||
#define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
|
||||
#define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
|
||||
#define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
|
||||
#define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
|
||||
#define STM32_PLL2_ENABLED 1
|
||||
#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
|
||||
#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
|
||||
#define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1)
|
||||
#define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
|
||||
#define STM32_PLL3_ENABLED 1
|
||||
#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
|
||||
#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
|
||||
#define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1)
|
||||
#define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
|
||||
#define STM32_PLL4_ENABLED 1
|
||||
#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
|
||||
#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
|
||||
#define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1)
|
||||
#define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2)
|
||||
#endif
|
||||
|
||||
/** PLL/PLL1 clock source */
|
||||
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
|
||||
DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
|
||||
|
|
@ -281,6 +319,9 @@
|
|||
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
|
||||
DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
|
||||
#define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
|
||||
#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
|
||||
#define STM32_PLL2_SRC_MSI 1
|
||||
#endif
|
||||
#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
|
||||
#define STM32_PLL2_SRC_MSIS 1
|
||||
#endif
|
||||
|
|
@ -297,6 +338,9 @@
|
|||
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
|
||||
DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
|
||||
#define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
|
||||
#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
|
||||
#define STM32_PLL3_SRC_MSI 1
|
||||
#endif
|
||||
#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
|
||||
#define STM32_PLL3_SRC_MSIS 1
|
||||
#endif
|
||||
|
|
@ -309,6 +353,22 @@
|
|||
|
||||
#endif
|
||||
|
||||
/** PLL4 clock source */
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
|
||||
DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
|
||||
#define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
|
||||
#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
|
||||
#define STM32_PLL4_SRC_MSI 1
|
||||
#endif
|
||||
#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
|
||||
#define STM32_PLL4_SRC_HSI 1
|
||||
#endif
|
||||
#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
|
||||
#define STM32_PLL4_SRC_HSE 1
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/** Fixed clocks related symbols */
|
||||
|
||||
|
|
@ -414,6 +474,11 @@
|
|||
#define STM32_HSE_ENABLED 1
|
||||
#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
|
||||
#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
|
||||
#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
|
||||
#define STM32_HSE_ENABLED 1
|
||||
#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
|
||||
#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
|
||||
#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
|
||||
#else
|
||||
#define STM32_HSE_FREQ 0
|
||||
#endif
|
||||
|
|
@ -431,6 +496,130 @@
|
|||
#define STM32_CKPER_ENABLED 1
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
|
||||
#define STM32_CPUSW_ENABLED 1
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC1_ENABLED 1
|
||||
#define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src)
|
||||
#define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC2_ENABLED 1
|
||||
#define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src)
|
||||
#define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC3_ENABLED 1
|
||||
#define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src)
|
||||
#define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC4_ENABLED 1
|
||||
#define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src)
|
||||
#define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC5_ENABLED 1
|
||||
#define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src)
|
||||
#define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC6_ENABLED 1
|
||||
#define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src)
|
||||
#define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC7_ENABLED 1
|
||||
#define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src)
|
||||
#define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC8_ENABLED 1
|
||||
#define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src)
|
||||
#define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC9_ENABLED 1
|
||||
#define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src)
|
||||
#define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC10_ENABLED 1
|
||||
#define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src)
|
||||
#define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC11_ENABLED 1
|
||||
#define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src)
|
||||
#define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC12_ENABLED 1
|
||||
#define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src)
|
||||
#define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC13_ENABLED 1
|
||||
#define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src)
|
||||
#define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC14_ENABLED 1
|
||||
#define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src)
|
||||
#define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC15_ENABLED 1
|
||||
#define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src)
|
||||
#define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC16_ENABLED 1
|
||||
#define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src)
|
||||
#define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC17_ENABLED 1
|
||||
#define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src)
|
||||
#define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC18_ENABLED 1
|
||||
#define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src)
|
||||
#define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC19_ENABLED 1
|
||||
#define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src)
|
||||
#define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div)
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
|
||||
#define STM32_IC20_ENABLED 1
|
||||
#define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src)
|
||||
#define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div)
|
||||
#endif
|
||||
|
||||
/** Driver structure definition */
|
||||
|
||||
struct stm32_pclken {
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#define STM32_CLOCK_BUS_APB5 12
|
||||
#define STM32_CLOCK_BUS_AXI 13
|
||||
#define STM32_CLOCK_BUS_MLAHB 14
|
||||
#define STM32_CLOCK_BUS_APB4_2 15
|
||||
|
||||
#define STM32_CLOCK_DIV_SHIFT 12
|
||||
|
||||
|
|
|
|||
193
include/zephyr/dt-bindings/clock/stm32n6_clock.h
Normal file
193
include/zephyr/dt-bindings/clock/stm32n6_clock.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* Copyright (c) 2024 STMicroelectronics
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
|
||||
|
||||
#include "stm32_common_clocks.h"
|
||||
|
||||
/** Domain clocks */
|
||||
|
||||
/* RM0468, Table 56 Kernel clock distribution summary */
|
||||
|
||||
/** System clock */
|
||||
/* defined in stm32_common_clocks.h */
|
||||
/** Fixed clocks */
|
||||
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
|
||||
#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
|
||||
#define STM32_SRC_MSI (STM32_SRC_HSI + 1)
|
||||
/** PLL outputs */
|
||||
#define STM32_SRC_PLL1 (STM32_SRC_MSI + 1)
|
||||
#define STM32_SRC_PLL2 (STM32_SRC_PLL1 + 1)
|
||||
#define STM32_SRC_PLL3 (STM32_SRC_PLL2 + 1)
|
||||
#define STM32_SRC_PLL4 (STM32_SRC_PLL3 + 1)
|
||||
/** Clock muxes */
|
||||
#define STM32_SRC_CKPER (STM32_SRC_PLL4 + 1)
|
||||
#define STM32_SRC_IC1 (STM32_SRC_CKPER + 1)
|
||||
#define STM32_SRC_IC2 (STM32_SRC_IC1 + 1)
|
||||
#define STM32_SRC_IC3 (STM32_SRC_IC2 + 1)
|
||||
#define STM32_SRC_IC4 (STM32_SRC_IC3 + 1)
|
||||
#define STM32_SRC_IC5 (STM32_SRC_IC4 + 1)
|
||||
#define STM32_SRC_IC6 (STM32_SRC_IC5 + 1)
|
||||
#define STM32_SRC_IC7 (STM32_SRC_IC6 + 1)
|
||||
#define STM32_SRC_IC8 (STM32_SRC_IC7 + 1)
|
||||
#define STM32_SRC_IC9 (STM32_SRC_IC8 + 1)
|
||||
#define STM32_SRC_IC10 (STM32_SRC_IC9 + 1)
|
||||
#define STM32_SRC_IC11 (STM32_SRC_IC10 + 1)
|
||||
#define STM32_SRC_IC12 (STM32_SRC_IC11 + 1)
|
||||
#define STM32_SRC_IC13 (STM32_SRC_IC12 + 1)
|
||||
#define STM32_SRC_IC14 (STM32_SRC_IC13 + 1)
|
||||
#define STM32_SRC_IC15 (STM32_SRC_IC14 + 1)
|
||||
#define STM32_SRC_IC16 (STM32_SRC_IC15 + 1)
|
||||
#define STM32_SRC_IC17 (STM32_SRC_IC16 + 1)
|
||||
#define STM32_SRC_IC18 (STM32_SRC_IC17 + 1)
|
||||
#define STM32_SRC_IC19 (STM32_SRC_IC18 + 1)
|
||||
#define STM32_SRC_IC20 (STM32_SRC_IC19 + 1)
|
||||
|
||||
/** Bus clocks */
|
||||
#define STM32_CLOCK_BUS_AHB1 0x250
|
||||
#define STM32_CLOCK_BUS_AHB2 0x254
|
||||
#define STM32_CLOCK_BUS_AHB3 0x258
|
||||
#define STM32_CLOCK_BUS_AHB4 0x25C
|
||||
#define STM32_CLOCK_BUS_AHB5 0x260
|
||||
#define STM32_CLOCK_BUS_APB1 0x264
|
||||
#define STM32_CLOCK_BUS_APB1_2 0x268
|
||||
#define STM32_CLOCK_BUS_APB2 0x26C
|
||||
#define STM32_CLOCK_BUS_APB3 0x270
|
||||
#define STM32_CLOCK_BUS_APB4 0x274
|
||||
#define STM32_CLOCK_BUS_APB4_2 0x278
|
||||
#define STM32_CLOCK_BUS_APB5 0x27C
|
||||
|
||||
#define STM32_CLOCK_LP_BUS_SHIFT 0x40
|
||||
|
||||
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
|
||||
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB5
|
||||
|
||||
#define STM32_CLOCK_REG_MASK 0xFFFU
|
||||
#define STM32_CLOCK_REG_SHIFT 0U
|
||||
#define STM32_CLOCK_SHIFT_MASK 0x1FU
|
||||
#define STM32_CLOCK_SHIFT_SHIFT 12U
|
||||
#define STM32_CLOCK_MASK_MASK 0x7U
|
||||
#define STM32_CLOCK_MASK_SHIFT 17U
|
||||
#define STM32_CLOCK_VAL_MASK 0x7U
|
||||
#define STM32_CLOCK_VAL_SHIFT 20U
|
||||
|
||||
/**
|
||||
* @brief STM32U5 clock configuration bit field.
|
||||
*
|
||||
* - reg (1/2/3) [ 0 : 11 ]
|
||||
* - shift (0..31) [ 12 : 16 ]
|
||||
* - mask (0x1, 0x3, 0x7) [ 17 : 19 ]
|
||||
* - val (0..7) [ 20 : 22 ]
|
||||
*
|
||||
* @param reg RCC_CCIPRx register offset
|
||||
* @param shift Position within RCC_CCIPRx.
|
||||
* @param mask Mask for the RCC_CCIPRx field.
|
||||
* @param val Clock value (0, 1, ... 7).
|
||||
*/
|
||||
#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
|
||||
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
|
||||
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
|
||||
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
|
||||
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
|
||||
|
||||
/** @brief RCC_CCIPRx register offset (RM0468.pdf) */
|
||||
#define CCIPR1_REG 0x144
|
||||
#define CCIPR2_REG 0x148
|
||||
#define CCIPR3_REG 0x14C
|
||||
#define CCIPR4_REG 0x150
|
||||
#define CCIPR5_REG 0x154
|
||||
#define CCIPR6_REG 0x158
|
||||
#define CCIPR7_REG 0x15C
|
||||
#define CCIPR8_REG 0x160
|
||||
#define CCIPR9_REG 0x164
|
||||
#define CCIPR12_REG 0x170
|
||||
#define CCIPR13_REG 0x174
|
||||
#define CCIPR14_REG 0x178
|
||||
|
||||
/** @brief Device domain clocks selection helpers */
|
||||
/** CCIPR1 devices */
|
||||
#define ADF1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR1_REG)
|
||||
#define ADC12_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR1_REG)
|
||||
#define DCMIPP_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 20, CCIPR1_REG)
|
||||
/** CCIPR2 devices */
|
||||
#define ETH1PTP_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR2_REG)
|
||||
#define ETH1CLK_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 12, CCIPR2_REG)
|
||||
#define ETH1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR2_REG)
|
||||
#define ETH1REFCLK_SEL(val) STM32_DOMAIN_CLOCK((val), 1, 20, CCIPR2_REG)
|
||||
#define ETH1GTXCLK_SEL(val) STM32_DOMAIN_CLOCK((val), 1, 24, CCIPR2_REG)
|
||||
/** CCIPR3 devices */
|
||||
#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR3_REG)
|
||||
#define FMC_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR3_REG)
|
||||
/** CCIPR4 devices */
|
||||
#define I2C1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR4_REG)
|
||||
#define I2C2_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR4_REG)
|
||||
#define I2C3_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR4_REG)
|
||||
#define I2C4_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR4_REG)
|
||||
#define I3C1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR4_REG)
|
||||
#define I3C2_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR4_REG)
|
||||
#define LTDC_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 24, CCIPR4_REG)
|
||||
/** CCIPR5 devices */
|
||||
#define MCO1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR5_REG)
|
||||
#define MCO2_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR5_REG)
|
||||
#define MDF1SEL(val) STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR5_REG)
|
||||
/** CCIPR6 devices */
|
||||
#define XSPI1_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR6_REG)
|
||||
#define XSPI2_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR6_REG)
|
||||
#define XSPI3_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 8, CCIPR6_REG)
|
||||
#define OTGPHY1_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 12, CCIPR6_REG)
|
||||
#define OTGPHY1CKREF_SEL(val) STM32_DOMAIN_CLOCK((val), 1, 16, CCIPR6_REG)
|
||||
#define OTGPHY2_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 20, CCIPR6_REG)
|
||||
#define OTGPHY2CKREF_SEL(val) STM32_DOMAIN_CLOCK((val), 1, 24, CCIPR6_REG)
|
||||
/** CCIPR7 devices */
|
||||
#define PER_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR7_REG)
|
||||
#define PSSI_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR7_REG)
|
||||
#define RTC_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 8, CCIPR7_REG)
|
||||
#define SAI1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR7_REG)
|
||||
#define SAI2_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR7_REG)
|
||||
/** CCIPR8 devices */
|
||||
#define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR8_REG)
|
||||
#define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR8_REG)
|
||||
/** CCIPR9 devices */
|
||||
#define SPDIFRX1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR9_REG)
|
||||
#define SPI1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR9_REG)
|
||||
#define SPI2_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR9_REG)
|
||||
#define SPI3_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR9_REG)
|
||||
#define SPI4_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR9_REG)
|
||||
#define SPI5_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR9_REG)
|
||||
#define SPI6_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR9_REG)
|
||||
/** CCIPR12 devices */
|
||||
#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR12_REG)
|
||||
#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR12_REG)
|
||||
#define LPTIM3_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR12_REG)
|
||||
#define LPTIM4_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR12_REG)
|
||||
#define LPTIM5_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR12_REG)
|
||||
/** CCIPR13 devices */
|
||||
#define USART1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR13_REG)
|
||||
#define USART2_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR13_REG)
|
||||
#define USART3_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR13_REG)
|
||||
#define UART4_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR13_REG)
|
||||
#define UART5_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR13_REG)
|
||||
#define USART6_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR13_REG)
|
||||
#define UART7_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR13_REG)
|
||||
#define UART8_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 28, CCIPR13_REG)
|
||||
/** CCIPR14 devices */
|
||||
#define UART9_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR14_REG)
|
||||
#define USART10_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR14_REG)
|
||||
#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR14_REG)
|
||||
|
||||
/** @brief RCC_ICxCFGR register offset (RM0468.pdf) */
|
||||
#define ICxCFGR_REG(ic) (0xC4 + ((ic) - 1) * 4)
|
||||
|
||||
/** @brief Divider ICx source selection */
|
||||
#define ICx_PLLy_SEL(ic, pll) STM32_DOMAIN_CLOCK((pll) - 1, 3, 28, ICxCFGR_REG(ic))
|
||||
|
||||
/** @brief RCC_CFGR1 register offset (RM0468.pdf) */
|
||||
#define CFGR1_REG 0x20
|
||||
|
||||
/** @brief CPU clock switch selection */
|
||||
#define CPU_SEL(val) STM32_DOMAIN_CLOCK((val), 3, 16, CFGR1_REG)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue