In the update to hal_rpi_pico,
POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_PSM macros name were corrected
from POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM.
Update this driver accordingly.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
if() guard in disk CMakeLists file was redundant since the file will
only be included by the parent CMakeLists if CONFIG_DISK_DRIVERS is
already set. Drop it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@analog.com>
The async completion timeout returned while still holding the
access mutex and the PM runtime reference, wedging the controller
for every subsequent request. Unlock and drop the reference before
returning.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The buffer check ran before active_channels was computed, so it
validated against zero required bytes and always passed, letting
undersized buffers through. Compute the channel count first.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
MIN_DELAY is the floor of the SysTick LOAD register: the closest-in
timeout the driver will program. It must exceed the longest the SysTick
interrupt can stay masked, otherwise the 24-bit counter can wrap more than
once between elapsed() reads and lose a LOAD's worth of cycles. That is a
wall-clock property, but the default was a fixed cycle count:
MAX(1024, CYC_PER_TICK/16)
A fixed cycle count is a different wall-clock time on every clock. On a
32 kHz SysTick the 1024-cycle floor is ~31 ms (31 ticks), so the driver
could never schedule a timeout shorter than 31 ticks and every such board
had to override zephyr,min-timeout-cycles by hand.
Compute it instead as a fixed wall-clock budget scaled to the actual
frequency (min_delay = SYSTICK_MIN_DELAY_US * HW_CYCLES_PER_SEC), resolved
at init and refreshed on a runtime frequency change, so it also works when
the frequency is only known at runtime. At ~10 us this matches the old
1024 cycles near 100 MHz and scales sensibly elsewhere. The tick rate is
not involved; if the budget exceeds a tick on some clock, sub-tick timeouts
are simply unavailable there. A dts override still takes precedence.
Floor the result at two cycles: LOAD is programmed as (cycles - 1) and a
LOAD of zero stops the counter, so the smallest usable reload is two cycles
(LOAD 1). On a slow clock such as a 32 kHz SysTick the 10 us budget rounds
below that, so the hardware floor is what applies and the board still needs
no override.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Convert cmd->response_type from a Zephyr enum sd_rsp_type value to the
Ambiq HAL's MMC_RSP_* bitmask via a new helper
ambiq_sdio_resp_type_to_hal(). The helper returns false on an
unrecognized response type and the caller propagates -EINVAL to fail
fast at the API boundary.
Remove the redundant CMD-index based ui32RespType overrides, keeping
only the bCheckBusyCmd handling for CMD6 and CMD38, which is a real
HAL-specific semantic not covered by the response type enum.
Also change the helper parameter type from enum sd_rsp_type to
uint32_t to match cmd->response_type, and add an explicit (int) cast
in the LOG_ERR format call.
Fixes zephyrproject-rtos#112220
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
The default MCUX_OS_TIMER_MIN_DELAY of 1000 cycles is too large
relative to CYC_PER_TICK (100) on platforms clocked at 1 MHz with
SYS_CLOCK_TICKS_PER_SEC=10000. Because MIN_DELAY exceeds CYC_PER_TICK
by 10x, nearly every sys_clock_set_timeout() call adds an extra tick,
inflating short delays and causing the kernel timer_behavior test
(timer_ramp) to fail for low delay values.
Reduce the default to 50 cycles (50 us at 1 MHz), which provides
sufficient hardware setup margin for the match register without
interfering with normal tick scheduling.
Verified on frdm_mcxa344 and frdm_mcxa156 hardware:
- tests/kernel/timer/timer_behavior: all cases pass
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
Implements the new per-bus timeout mechanism for the I2C bus that was
introduced in PR #107827.
Assisted-by: Github Copilot:Claude Opus 5
Signed-off-by: John Batch <john.batch@infineon.com>
`select SYSCON` in `OTP_RTS5817` creates a circular Kconfig dependency
loop (`SYSCON -> OTP -> ... -> DCACHE -> SYSCON`) that breaks kconfig.py
in downstream builds.
Change `select SYSCON` to `depends on SYSCON` to break the loop.
Signed-off-by: Al Semjonovs <asemjonovs@google.com>
Align the public UART async API with its microsecond-based implementation.
Update the wide-data (u16 variant) TX and RX API documentation to
specify microseconds and SYS_FOREVER_US.
Replace millisecond-named forever sentinels in the serial test driver and
asynchronous UART callers, while retaining existing microsecond timeout
values in drivers, tests, and samples.
Assisted-by: Copilot:GPT-5.6 Terra
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add `CONFIG_ST67W611M1_WIFI_AUTO_CONNECT` to control persistent
auto-connect setting `AT+CWAUTOCONN`.
During init the driver reads `AT+CWAUTOCONN?` and only issues
`AT+CWAUTOCONN=<0|1>` when the module's current value differs,
so the module's flash is not rewritten on every boot.
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
The init sequence never put the coprocessor into station mode, so on a
freshly flashed module the first AT+CWJAP is rejected with ERROR and
wifi connect always fails.
Issue AT+CWMODE=1,1 during initialization. This matches ST's ST67W6X
SDK, which sets station mode in W61_WiFi_Station_Start(), called early in
W6X_WiFi_Init() (before auto-connect, country code and DTIM setup). The
auto-connect field is left at the firmware default (1) so mode changes
rely on the saved flash configuration.
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
Add AES and SHA-256 crypto drivers for Realtek Bee SoCs. The AES
supports 128-bit and 256-bit keys with ECB, CBC, CFB, OFB, and CTR
modes.
The SHA-256 driver supports one-shot hash operations. Add devicetree
bindings and disabled nodes for RTL8752H and RTL87x2G, so boards can
enable the accelerators explicitly.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
This driver needs the nsi_errno conversion component.
Let's make sure we build it by selecting it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This driver needs the nsi_errno conversion component.
Let's make sure we build it by selecting it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This driver needs the nsi_errno conversion component.
Let's make sure we build it by selecting it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This driver needs the nsi_errno conversion component.
Let's make sure we build it by selecting it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
According to Table 6 in the reference manual, the system memory ranging
from 0x1ff00000 to 0x1ff1ffff on STM32H7 SoCs may be accessed only by
the Cortex-M7. Notably, this range includes the 96 bit UID located at
0x1ff1e800. Attempting to access this address from the Cortex-M4 results
in a HardFault.
Simply omit the z_impl_hwinfo_get_device_id function entirely on the
Cortex-M4 and rely on the weak default symbol to return an error.
Signed-off-by: Vilhelm Engström <vilhelm.engstrom@tuta.io>
To avoid assuming that ZVFS_O_RDONLY matches O_RDONLY, compile the
Linux file access code directly with the host libc.
This also removes the need for the nsi_host file operation wrappers and
makes the host-side code easier to read.
Signed-off-by: Bayrem Gharsellaoui <bayrem.gharsellaoui@gmail.com>
Add a native_sim driver to read a Linux host temperature using the
Zephyr sensor API.
Signed-off-by: Bayrem Gharsellaoui <bayrem.gharsellaoui@gmail.com>
The BLE receive thread runs the connect-time settings store
(CCC, keys, GATT database hash), which on Espressif SoCs goes
through the flash driver and PSA crypto and overflows the 1200
byte host default. Raise BT_RX_STACK_SIZE to 2048 when
BT_SETTINGS is enabled.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use store-and-forward mode instead of cut-through mode to
allow for offloading of checksum calculation to the hardware.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Cores with multiple queues need to have queue 0 setup explicitly,
otherwise no queue will be available for RX/TX. As only a single
queue is used in this driver, setup queue 0 and assign the whole
fifo to it.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The driver was incorrectly using 'oob_addr' instead of 'addr' as the
PECI index during transactions. Update the assignment to use the correct
target address.
Additionally, add the missing definitions in the header file to complete
the PECI over eSPI implementation.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
The I2C master transfer waited on the transfer semaphore with K_FOREVER,
so a target that never completed a transfer would block the calling
thread indefinitely with no recovery mechanism.
Wait on the transfer semaphore using I2C_TRANSFER_TIMEOUT. On a timeout,
abort the asynchronous operation and reset the shared state with the SCB
interrupt masked so a late completion cannot corrupt the teardown, then
return -ETIMEDOUT.
Assisted-by: Github Copilot:claude-opus-4.8
Signed-off-by: John Batch <john.batch@infineon.com>
A write-read transfer to a target that NACKs its address sometimes
returns stale data on alternating attempts. This is caused by the read
phase being chained from the interrupt handler whenever the master goes
idle. After a write is aborted by an address NACK, the read is still
being issued, which causes an extra completion to be signalled. The
following transfer then erroneously acts on this, causing the driver to
report a successful transfer erroneously.
Chain the read phase from the event handler on write completion so it is
only issued after the write phase is successful. Clear the async
transfer state on the error path so the interrupt handler doesn't start
a spurious read after a failed write.
Assisted-by: Github Copilot:claude-opus-4.8
Signed-off-by: John Batch <john.batch@infineon.com>
Add a new pm_cpu_ops backend implementing the ARM64 spin-table
boot protocol for bringing up secondary CPUs, as an alternative
to PSCI on platforms that don't support it.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
The LDO branch of configure_active_discharge() wrote the reg
variable, which is always UINT8_MAX for LDOs, into the pull-down
field, enabling the pull-down even when active discharge was
explicitly disabled. Use the requested active_discharge value like
the BUCK and load switch branches do.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The renesas,regulator-v30-vbus property was multiplied by the VBAT
mode bit and renesas,regulator-v30-vbat by the VBUS mode bit, so
each property enabled the opposite supply source. Swap the mode
constants so each property programs its own bit.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The Solomon Systech SSD1683 is a Gen2 SSD16xx EPD controller (functionally
equivalent to the SSD1619A, 400 sources x 300 gates). It uses the same
command set as the already-supported SSD1680/SSD1681, and loads its refresh
waveforms from OTP, so support is a new devicetree binding plus a quirks
entry with the correct maximum resolution.
Used by e.g. the WeAct Studio 4.2" and GoodDisplay GDEY042T81 400x300
mono panels.
Signed-off-by: Marcus Voß <meav33@gmail.com>
Stream Sensor HUB data in FIFO and decode them properly.
Currently two channels are handled:
- SENSOR_CHAN_MAGN_XYZ
- SENSOR_CHAN_PRESS
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Set the read number of operation to 0 at the end of
lsm6dsv16x_shub_read_target_reg(), just to avoid issues
when reading data from FIFO.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Some SPI devices need the CS pin to be deasserted between multiple
transceive calls (e.g. the Microchip LAN8651). The MCSPI driver didn't do
this until now and kept the CS pin asserted for hardware controlled CS
pins, except if the channel changed.
This has been changed and additionally during init the GPIO pins are now
also being initialized.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Fix an issue reported by Copilot during review of another I2C RTIO
driver PM integration [1] that showed pm_device_runtime_get() failure
in i2c_rtio_submit handler could leave queued messages that will
never be proceeded and would stall the I2C RTIO transfer for the related
I2C bus.
Address that by flushing queued messages upon pm_device_runtime_get()
failure in iodev_submit handler.
Link: https://github.com/zephyrproject-rtos/zephyr/pull/110623#discussion_r3362750827 [1]
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Factorize the loop sequence for processing synchronous I2C operations
until an async operation is started or there are no more queued
operations.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct an issue in NFRX TWIM I2C RTIO driver that made the bus PM
resources not released once all synchronous operations are proceeded
(by i2c_nrfx_twim_rtio_start_next_async()) and no asynchronous operation
followed in the RTIO queue.
For sake of simplicity, fix that by syncing with other I2C RTIO drivers
implementation, moving calls to i2c_rtio_complete() into an the
synchronous message processing loop and adding the missing call to
pm_device_runtime_put() from that loop.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
I2C RTIO operation that are synchronous (failure to start a message
transfer, bus configuration/recovery and unsupported or invalid RTIO I2C
operations) do call i2c_rtio_complete() but do not start next message
processing if the latter return true. Fix that and clarify the meaning
of i2c_nrfx_twi_rtio_start() return value.
For this purpose, move the call to i2c_rtio_complete() out of
i2c_nrfx_twi_rtio_msg_start() and i2c_nrfx_twi_rtio_start() functions
(the caller takes care of) and make i2c_nrfx_twi_rtio_msg_start() to
return a status error code.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
I2C RTIO operation that are synchronous (failure to start a message
transfer, bus configuration and unsupported or invalid RTIO I2C
operations) do call i2c_rtio_complete() but do not start next message
processing if the latter return true. Fix that and clarify the meaning
of mcux_lpi2c_start() return value. For this purpose, change
mcux_lpi2c_msg_start() not call i2c_rtio_complete() and to return an
errno code.
While at it, remove forward declaration of mcux_lpi2c_complete() this
is not needed and remove a '\n' character from error log message.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
I2C RTIO operation that are synchronous (failure to start a message
transfer, bus configuration and unsupported or invalid RTIO I2C
operations) do call i2c_rtio_complete() but do not start next message
processing if the latter return true. Fix that and clarify the meaning
of max32_start() return value.
While at line, remove a nearby unexpected empty line.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Some gpio controller do not support GPIO_DISCONNECTED, or at least when
the dt flag also includes pullup/pulldowns. Add an option to allow using
GPIO_INPUT instead, that'll always work.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add SOC_ESP32_APPCPU_TARGET, a hidden symbol set whenever the
build targets the APPCPU image of a dual-core SoC. Replace all
places that checked SOC_ESP32_APPCPU and SOC_ESP32S3_APPCPU
together with the new symbol.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There is no need to limit this functionality to when we build the
embedded code with the host libC.
It is better to just move the host dependent code into its own
file that is built in the runner context.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Deconfigure: i2s_configure() with frame_clk_freq == 0 is defined by the
API as a request to deconfigure the stream, but the driver rejected it
with -EINVAL. Release the queued buffers and move the stream to
NOT_READY. The state check is now made on the stream being configured
instead of on both directions at once, so one direction can be
configured while the other one is running, and config_get() returns
NULL for an unconfigured stream as the API requires.
Restart: reset the FIFO pointers via the FR bit before enabling DMA
requests, so words left over from a previous run are not replayed.
Bit clock source: the SAI_Get*Config helpers overwrite bclkSource with
the master clock divider, leaving SoCs without an internal divider or
MCLK routing with no bit clock at all. Add an nxp,bclk-source binding
property (TCR2/RCR2 MSEL value) applied after those calls; it defaults
to the master clock divider so existing users are unaffected.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add SAI gate and rate table entries, guarded by CONFIG_I2S_MCUX_SAI
and FSL_FEATURE_SOC_I2S_COUNT like the other per-IP entries, so the
I2S (SAI) driver can gate the peripheral clock and query its rate
through the standard clock_control API.
Verified with tests/drivers/i2s/i2s_speed on frdm_mcxe31b: the SAI
module clock gates on and reports the AIPS_SLOW rate used for the
bit clock dividers.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
