Add a Zephyr ADC driver for the Microchip G1 ADC peripheral
with support for differential mode, multi-channel sequencing,
oversampling, and NVM-based factory calibration.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Supporting irqsteer using NXP HAL becomes increasingly harder with new
SoCs.
For example now there are two incompatible HAL drivers for IRQ steer
(mcux-sdk-ng/drivers/irqsteer and mcux-sdk-ng/drivers/irqsteer_1).
In order to avoid overcomplicating code and better scaling code for
newer SoCs just drop using the NXP HAL and implement an IRQ Steer native
Zephyr driver
Use irqsteer node of imx943 as example.
New features:
- Support multiple irqsteer instances.
- Indroduce new properties(nxp,irq-offset, nxp,num-irqs).
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Zephyr's current ADC API only supports 32 logical channels,
which is inadequate for SAR ADCs on certain SoCs. For instance,
the ADC on the MCXE31B has 64 hardware channels. The previous
implementation used a one-to-one mapping between logical and
hardware channels. In the new SAR ADC driver version, we bind
hardware channels to logical channels via the zephyr,input-positive
property, enabling us to access any channel.
Currently, only imx93 uses this ADC. To maintain the bisectability
of Zephyr commits, in this commit we will also modify the imx93-related
files, inlcuding:
1. Update the clock_control_mcux_ccm_rev2.c to use the new Kconfig
option 'CONFIG_ADC_NXP_SAR_ADC'.
2. Add properties to the imx93_evk_mimx9352_m33.overlay of the adc_api
testcase.
Now the sar adc is native driver, so, remove
CONFIG_MCUX_COMPONENT_driver.sar_adc from the glue cmake.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Replace K_SYSCALL_OBJ() with K_SYSCALL_DRIVER_AUXDISPLAY() in syscall
handlers to validate that the requested driver operation is actually
implemented before invoking it.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add missing K_SYSCALL_MEMORY_WRITE and K_SYSCALL_MEMORY_READ
verifications in syscall handlers for pointer parameters.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Fixed the sys_clock_announce to be outside of spinlock context to
resolve the issues related to invalid spinlock when CONFIG_PM is
enabled
Signed-off-by: Merin George <merin.george@infineon.com>
- Include the enable, m0, and m1 microstep to the common init config.
- Refactor drivers that manually init these pins to use the pins
from the common config.
Signed-off-by: Hong Nguyen <hong.nguyen.k54@gmail.com>
Now that VIDEO_BUFFER_POOL_HEAP_SIZE is available is used
in all projects, VIDEO_BUFFER_POOL_SZ_MAX can be removed.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Update video common code and applications to rely on the
CONFIG_VIDEO_BUFFER_POOL_HEAP_SIZE instead of
CONFIG_VIDEO_BUFFER_POOL_SZ_MAX.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Clarify the size of the video buffer pool by having a
dedicated CONFIG for it. Until now the size of the
video buffer pool was equal to VIDEO_BUFFER_POOL_SZ_MAX
multiply by VIDEO_BUFFER_POOL_NUM_MAX.
This commit only add the description, the config doesn't
have yet any effect. Change will be added after all configs
are updated to define it in order to avoid breaking
platforms between 2 commits.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Allow usage of either Shared-Multi-Heap based internal memory pool
allocation or allocation from a HEAP located optional in a
Zephyr region.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Addition of two options in order to select the Zephyr region
into which the video buffer pool should be placed.
CONFIG_VIDEO_BUFFER_POOL_ZEPHYR_REGION allows to indicate that the
video video pool should be placed in a specific ZEPHYR region which
name is CONFIG_VIDEO_BUFFER_POOL_ZEPHYR_REGION_NAME
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This adds support for clock_control_get_rate/clock_control_set_rate
API, so that module clock rate can fetch or modify via them in Hz.
Note only CANFD support is added as an reference example and other
module support will be added as-needed.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
1. Enable MCXA/MCXN platforms' LPCMP clock control through
the clock driver (syscon).
2. Enable MCXE platform's LPCMP clock control through the
clock driver (mc_cgm).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
We are planning to implement a new lpcmp driver based on the
comparator API and deprecate the current sensor-based driver.
We now mark the mcux_lpcmp as deprecated.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
We are planning to implement a new LPCMP driver based on the
comparator API and deprecate the current sensor-based driver.
We would like to use the nxp,lpcmp binding for the new
comparator-based driver implementation. To avoid naming conflicts,
we are renaming the current sensor binding to nxp,sensor-lpcmp.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Split device initialization into two phases across all LBM drivers:
1. Boot-time init: Minimal device initialization
2. First config: Radio hardware initialization
This deferred initialization approach provides full control over the
radio hardware, allowing applications to perform any necessary setup
before the radio is initialized. The radio init is automatically
triggered on the first call to lora_config().
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add functions to register and unregister user GPIO callbacks for DIO1
interrupts on LBM lora radio devices. This allows external code (e.g., the
LoRa Basics Modem HAL) to receive notifications when DIO1 fires.
The driver configures the pin mask automatically based on the DIO1 pin
from devicetree.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Refactor the Infineon TCPWM counter driver to use the TCPWM block base
address instead of the counter instance base address. This change aligns
with the standard Infineon PDL API which requires the TCPWM block base
and counter index as separate parameters.
This modification maintains functional compatibility while providing
better alignment with the underlying hardware abstraction layer.
This also aligns with PR feedback to move the ifx_tcpwm.h header file
from the include folder (public APIs) to the drivers folder. Instead,
this refactoring prepares to remove that header file entirely.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
This is a follow-up to commit 59d8fbc0a9.
Add missing brackets in mask definitions that use `COND_CODE_1()`.
Without those, the call to `__DEBRACKET()` that is done inside
`COND_CODE_1()` removes the outer brackets provided by `GENMASK()`,
what causes problems when the mask is directly used with another
operator like `~`.
Remove also no longer needed brackets added in `start_next_packet()`
by the commit mentioned above as a workaround for this problem,
the root cause of which was not identified at that time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Implement set_orientation api
Inverting segment_remap and com_invdir at the same time, rotates the
screen by 180 degrees.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
Implement `disk_access_erase` by setting all bytes to 0x00, with the
same bounds checking as `disk_access_write`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
These SoCs don't have LL_PKA_IsEnabled() due to the PKA IP being different.
Since PKA can operate without RNG clock on entire STM32WB0 series, skip
the check on the entire series which avoids the call to non-existent
function on STM32WB06/07 and fixes build.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Restore the clock source and exception bits in the CTRL register after
waking from low-power modes that reset SysTick. Also reconfigure the
interrupt priority.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The z_vrfy_uart_configure function was incorrectly checking for the
existence of the 'config_get' handler instead of 'configure'.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
According to the reference manual, 'When the BYPSHAD control bit is set
in the RTC_CR register [...] the value of one of the registers may be
incorrect if an RTCCLK edge occurs during the read operation'. We need
to read te subseconds register until two successive reads are equal.
Signed-off-by: Adrien Lessard <adrien.lessard.42@gmail.com>
According to the reference manual, 'When the BYPSHAD control bit is set
in the RTC_CR register [...] the value of one of the registers may be
incorrect if an RTCCLK edge occurs during the read operation'. We need
to read te subseconds register until two successive reads are equal.
Signed-off-by: Adrien Lessard <adrien.lessard.42@gmail.com>
