make the part that is needed for the esp32 to
change the offsets for the mac and base registers
more generic and use the devicetree for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
pcf8523_get_calibration() decodes the offset register with
(offset << 1U) >> 1U, intended to clear the mode bit and sign
extend the signed 7-bit offset field. Under C integer promotion
the expression operates on a 32-bit int, so it is a no-op: the
MODE bit is not cleared and acts as the sign bit of the int8_t
register value instead of the actual field sign at bit 6.
In fast offset mode every readback is decoded through the set MODE
bit, e.g. a stored offset of +9 (register 0x89) reads back as -119
steps. In slow mode, with the offset field now written correctly
masked, a stored offset of -9 (register 0x77) would read back as
+119 steps. Mask the offset field and decode it with
sign_extend().
Built tests/drivers/build_all/rtc (i2c_devices.overlay) for
qemu_cortex_m3 with CONFIG_RTC_CALIBRATION=y. No hardware run;
register-level analysis against the PCF8523 data sheet.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
pcf8523_set_calibration() converts the requested frequency
correction into a period offset and writes it to the offset
register without masking. A positive calibration request becomes a
negative period offset, and bit 7 of its two's complement
representation lands in the MODE bit of the offset register: with
the default slow offset mode, every positive calibration request
silently switches the device into fast mode, where the hardware
applies a 4069 ppb step while the driver computed the value with
the 4340 ppb step (about 6.7% scale error and a different
correction cadence).
Mask the value with the signed 7-bit offset field so the MODE bit
is controlled only by the configured offset mode. The unused
PCF8523_OFFSET_MASK define matches the field exactly.
Built tests/drivers/build_all/rtc (i2c_devices.overlay) for
qemu_cortex_m3 with CONFIG_RTC_CALIBRATION=y. No hardware run;
register-level analysis against the PCF8523 data sheet (offset
register, table 29).
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add an I2C driver for the Analog Devices ADXL313 3-axis accelerometer
with classic sensor API support for range and ODR configuration.
Use i2c_reg_update_byte_dt for register read-modify-write, reconfigure
range/ODR in standby, and add build_all coverage plus a release-notes
entry.
Signed-off-by: Leo Li <leo.li@rakwireless.com>
Fix for RTIO streaming. When stream is canceled
with rtio_sqe_cancel before IRQ or when sequence
for getting data from FIFO, data->sqe is set to NULL.
This will result with early exit from some functions.
Because data->fifo_watermark_irq remain set, it was
not possible to start new stream.
Signed-off-by: Vladislav Pejic <vladislav.pejic@orioninc.com>
The BMP581 SPI protocol requires every data byte in a multi-byte write
to be preceded by its register address. The driver currently submits
one address followed by all data bytes, so the second data byte is
interpreted as another register address.
Build one two-byte RTIO SQE for each register-address/data pair and
chain the SQEs as one transaction to keep CSB asserted. Leave the I2C
and I3C paths unchanged.
Update the SPI emulator to parse address/data pairs independently of
SPI buffer boundaries. This supports the corrected transaction layout
and rejects the previous malformed write sequence.
This allows OSR_CONFIG and ODR_CONFIG to be programmed correctly
during initialization and prevents the data registers from remaining
at their reset values.
Tested by building samples/sensor/pressure_polling for an STM32F407
target.
Assisted-by: Codex:gpt-5.6-sol
Signed-off-by: Yu He <auhy@mail.scut.edu.cn>
After a soft reset, BMP581 returns to its power-up I2C/I3C mode.
The first SPI transaction selects SPI mode and returns invalid data.
The driver performs the post-reset dummy read only after soft_reset()
returns. However, soft_reset() reads INT_STATUS first, so the status read
is consumed as the SPI activation transaction and initialization fails
with -EFAULT.
Move the dummy read into soft_reset(), after the reset delay and before
reading INT_STATUS. The I2C and I3C paths remain unchanged.
Tested by building samples/sensor/sensor_shell for
arcap/stm32f407xx.
Link: https://github.com/zephyrproject-rtos/zephyr/pull/109240
Link: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmp581-ds004.pdf
Assisted-by: Codex:gpt-5.6-sol
Signed-off-by: Yu He <auhy@mail.scut.edu.cn>
these drivers are already conditionally
included/added in drivers/CMakeLists.txt
so we dont' need another if.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
the hal based stm32 ethernet driver has no support
for PTP on the stm32f1, f2 and f4, so use the dwc_mac
driver when PTP support is needed.
Signed-off-by: Fin Maaß <info@finmaass.de>
the hal based esp32 ethernet driver has no support
for PTP, so use the dwc_mac driver when PTP
support is needed.
Signed-off-by: Fin Maaß <info@finmaass.de>
Describe the EMAC PTP reference clock as a second clock on the
esp32p4 Ethernet node so it can be enabled and queried through
the clock control driver.
The rate is resolved from the PTP reference clock source, so
Ethernet PTP support does not need to assume a fixed frequency.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
After a read the cache invalidation only covered one block even
for multi-block transfers, leaving the remaining blocks to be read
from stale cache lines. Invalidate the full transfer size, which
matches the range flushed when the DMA descriptors are prepared.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
In the processor 1 macro block, every helper maps to the LL_C1
variant except IPCC_DisableReceiveChannel, which used the LL_C2
function and therefore masked the other core's receive channel.
Disabling reception was a no-op on the local core and corrupted
the remote core's mask instead.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This patch fixes the initialization of Affinity Routing if Zephyr is ran
as a Non-secure software. The layout of the Distributor Control register
is different, when accessed from Secure or Non-secure world.
Signed-off-by: Mateusz Karlic <mkarlic@antmicro.com>
Add a driver for Espressif's analog comparator (ana_cmpr) peripheral
against the generic comparator API, for ESP32-P4, ESP32-C5 and
ESP32-H2.
This IP revision only latches edge-cross events; there is no register
reflecting the instantaneous comparison result, so get_output() is not
supported and returns -ENOTSUP. Source and reference GPIO pads are
fixed per SoC/unit and configured as pure analog inputs during init.
Units whose interrupt source is shared with another unit (ESP32-P4) or
another peripheral (ESP32-H2's GPIO driver) use
esp_intr_alloc_intrstatus() with a per-instance status register/mask
so the interrupt controller can dispatch to each handler
independently.
The ISR is the only code that ever touches the hardware status
registers: it clears whatever int_st reports (already masked to the
armed trigger by int_ena) and either invokes the user callback or
latches a software pending flag, which trigger_is_pending() then just
reads and clears.
Hardware-validated on ESP32-C5-DevKitC-1, ESP32-H2-DevKitM and
ESP32-P4-Function-EV-Board via the gpio_loopback comparator test (see
next commits).
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
On ESP32-H2, the analog comparator (ana_cmpr) unit shares its
interrupt source (GPIO_INTR_SOURCE) with the GPIO peripheral, but uses
its own separate status/enable/clear registers (GPIO_EXT.*). Register
the GPIO driver's own interrupt via esp_intr_alloc_intrstatus() with
ESP_INTR_FLAG_SHARED, scoped to the GPIO status register/mask, so both
drivers can coexist on the same line independently.
Only takes effect when the new ana_cmpr driver is enabled, so this is
a no-op otherwise.
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
Convert the RV3028 driver from an RTC-only driver into a
multi-function device driver.
The RV3028 provides multiple functional blocks including RTC,
EEPROM, RAM and timestamp functionality. Split the existing
driver into an MFD parent and RTC child driver to allow the
additional features to be supported through their respective
Zephyr subsystems.
The existing RTC functionality remains unchanged.
Signed-off-by: Janez Ugovsek <janez@ugovsek.info>
Capture the timestamp at GPIO callback time (IRQ time) rather than
in the RTIO completion callback after the data has been read. Add odr
to the encoded header, fix base_timestamp_ns to reflect the time of
the first FIFO sample, and add timestamp_delta per sample, matching
the lsm6dsv16x reference implementation.
Fixes: #98720
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
(cherry picked from commit 8cdcdeb189e63e0fed1cc06b2eb7a74fd9e9ce5d)
Add a MUX controller backend for the Analog Devices ADGM3121 DPDT MEMS
switch (DC-24GHz). The four switches are modeled as a single control line
whose state is a 4-bit switch bitmask (bit i = SW(i+1), 1 = closed):
mux_control_set() drives all four at once, mux_control_disconnect() opens
them all, and mux_state_get() reads the mask back. Both SPI (adi,adgm3121)
and parallel GPIO (adi,adgm3121-gpio) control modes are supported.
Co-authored-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a generic GPIO-backed mux controller: the selected state value is
binary-encoded LSB-first across the GPIO lines listed in the mux-gpios
property (bit N -> mux-gpios[N]). Useful for board-level analog/digital
muxes that are simply wired to MCU GPIOs.
Single-channel by design, so the binding pins #mux-control-cells = 0
and #mux-state-cells = 1. The driver plugs into the existing mux
subsystem (set / get_state ops) and reuses CONFIG_MUX_INIT_PRIORITY, so
consumers reference it through the generic mux-controls / mux-states
model.
Co-authored-by: Felix Wang <fei.wang_3@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The mux subsystem redefines the "nxp,inputmux" binding as a mux
controller (#mux-control-cells / #mux-state-cells). The SCTimer PWM
capture path still programmed the INPUTMUX directly through the
fsl_inputmux HAL using two parallel "input-channels" /
"inputmux-connections" arrays, so on SoCs that expose the mux
controller node the two models conflicted. Move SCTimer capture onto
the generic mux model:
- nxp,lpc55S3x: add the INPUTMUX mux controller node (disabled by
default) so capture consumers can reference it; enabled per board.
- nxp,sctimer-pwm.yaml: drop the input-channels / inputmux-connections
arrays and include mux-consumer.yaml; the capture routing is now a
single "mux-states" phandle-array carrying <&inputmuxN index
connection>.
- pwm_mcux_sctimer: drop the direct fsl_inputmux HAL calls and apply
the routing through mux_state_apply(), guarded by device_is_ready().
The mux controllers init at priority 40, before PWM at 50, so they
are ready at SCTimer init time.
- Migrate the lpcxpresso55s36 pwm_loopback overlay to the mux-states
syntax and enable the INPUTMUX node.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The mux subsystem redefines the "nxp,inputmux" binding as a mux
controller (#mux-control-cells / #mux-state-cells), which collided with
the EQDC driver's use of the same compatible through a
"specifier-space: inputmux" phandle-array. Reconcile the two by moving
the EQDC PHASEA/PHASEB input routing onto the generic mux model:
- nxp,mcxa156 / nxp,mcxa344 / nxp,mcxaxx6: switch the inputmux node
from #inputmux-cells to #mux-control-cells / #mux-state-cells so it
validates against the new binding (nxp,mcxa153 was already done).
- nxp,mcux-eqdc.yaml: drop the local inputmux-connections property and
include mux-consumer.yaml; routing is now described with "mux-states".
- eqdc_mcux: drop the direct fsl_inputmux HAL calls and apply the
routing through mux_state_apply(), guarded by device_is_ready(). The
mux controllers init at priority 40, before the sensor at 90, so they
are ready at EQDC init time.
- Migrate the frdm_mcxa153/156/266/344/346/366 QDEC sample overlays to
the mux-states syntax.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The mux subsystem redefines the "nxp,inputmux" binding as a mux
controller (#mux-control-cells / #mux-state-cells), which collided with
the previous ctimer PWM-capture use of the same compatible through a
"specifier-space: inputmux" phandle-array. Reconcile the two by moving
ctimer PWM capture onto the generic mux model:
- nxp,mcxa153: switch the inputmux node from #inputmux-cells to
#mux-control-cells / #mux-state-cells.
- nxp,ctimer-pwm.yaml: drop the local inputmux-connections property and
include mux-consumer.yaml; routing is now described with "mux-states".
- pwm_mcux_ctimer: drop the direct fsl_inputmux HAL calls and apply the
routing through mux_state_apply() guarded by device_is_ready(). The
route is applied when capture is configured, where all devices are
ready. Update the test overlay to the mux-states syntax.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Drop the direct MCUX_XBARA HAL coupling in the QDEC driver in
favour of the new generic mux subsystem: the driver now selects
CONFIG_MUX, defines mux states from a "mux-states" devicetree
property and applies them at init time via mux_state_apply(),
which makes it agnostic to the underlying mux hardware.
Update the nxp,mcux-qdec binding to include mux-consumer.yaml,
augment the i.MX RT10xx XBAR nodes with CCM clock phandles plus
the new #mux-control-cells / #mux-state-cells declarations, and
migrate the MIMXRT1050-EVK QDEC overlay to the mux-states syntax.
Add the matching XBAR clock support to the i.MX CCM clock driver
(IMX_CCM_XBAR1_CLK / IMX_CCM_XBAR2_CLK gate/ungate, guarded by
CONFIG_MUX_NXP_XBAR) so the XBAR controllers referenced by those
nodes can be clocked.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Drop the direct INPUTMUX_AttachSignal() coupling in the QDC driver
in favour of the new generic mux subsystem: the driver now selects
CONFIG_MUX, defines mux states from a "mux-states" devicetree
property, and applies them at init time via mux_state_apply().
This makes the driver mux-hardware-agnostic.
Update the nxp,mcux-qdc binding to use mux-consumer.yaml, expose
the inputmux0 node on the MCXNx4x family DTSI, and migrate the
FRDM-MCXN947 / MCXN5xx-EVK QDC overlays to the new mux-states
syntax.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a mux controller driver for the NXP MCUX XBAR (Crossbar
Switch) peripheral, supporting both 16-bit and 32-bit SEL register
layouts via DEVICE_MMIO. Update the nxp,mcux-xbar binding to also
declare the mux-controller interface (#mux-control-cells and
documenting the legacy xbar-maps property for as-yet-unmigrated
consumers (e.g. qdec_mcux).
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a mux controller driver for the NXP TRGMUX peripheral, used to
multiplex trigger signals between on-chip peripherals. The
controller exposes two address cells (trgmux instance / output id)
and supports register-level lock so that an applied routing can be
frozen for the lifetime of the system.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a mux controller driver for the NXP INPUTMUX peripheral.
Wraps the HAL INPUTMUX_AttachSignal() routine to route a
peripheral input signal onto a destination channel through the
unified mux_state_apply() API.
Co-Authored-By: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Introduce a new generic multiplexer (MUX) controller subsystem
modeled on the Linux mux framework. Provides a unified API for
software- and hardware-level signal routers via mux_control_set()
and mux_state_apply(), with userspace syscall handlers and common
devicetree bindings (mux-controller / mux-consumer) for downstream
consumers.
Co-Authored-By: Felix Wang <fei.wang_3@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add UART driver support for the CH5xx.
This enables the hello_world and the drivers/uart/echo_bot samples.
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
Add GPIO driver support for the CH5xx series with the required bindings.
This enables the blinky sample to run by default, and the basic/button
sample when a device tree overlay is provided.
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
Add a pin controller driver for the WCH CH570 SoC.
Implements `pinctrl_configure_pins` to enable GPIO initialization and
alternate function configuration.
Update hal_wch revision in west.yml and hal_ch32fun.h to sync with
changes merged in zephyrproject-rtos/hal_wch#6
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
Rework the esp32 pcnt driver to expose every counting unit of a
single device. The read-and-decode api threads the unit index
through sensor_chan_spec.chan_idx so sensor_read returns an
encoded buffer that the driver's decoder unpacks per unit. The
legacy sensor_channel_get path is kept on unit 0 for backward
compatibility.
The new sensor_chan_pcnt_esp32_unit(n) helper (in a public
header) packs the unit index into the legacy sensor_channel
field so sensor_attr_set and sensor_trigger_set can target a
specific unit. A new sensor_attr_pcnt_esp32_reset attribute
clears the hardware counter.
Dt binding gains counts-per-revolution (enables degrees output
on sensor_chan_rotation), high-limit and low-limit watchpoints
(counter auto-resets on reach and raises the trigger), and
zero-cross-event. Filter is documented in apb cycles with the
correct 1023 clamp.
Threshold trigger demultiplexes per unit in the isr and fixes
the old behaviour that silently re-allocated the isr on every
trigger_set. Interrupt alloc moves to init.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
regulator_common_init() calls the .get_voltage() API.
So instead of not doing anything in the fake (not updating the voltage)
and therefore having regulator_common_init() continue with a random
value, let's update it to a relatively sensible constant (1V).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a Process Call command for validating driver functionality and
debugging SMBus devices. The command accepts a command code and write
word data, then read the word data response returned by the target device.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The driver supports up to nine SMBus controllers and implements the
standard SMBus protocols, except for Block Process Call.
It also supports an optional FIFO mode that uses the controller's
dedicated 32-byte FIFOs to reduce the interval between transferred
bytes and improve clock stretching during SMBus transactions.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
esp32_wifi_connect() sets data->state = ESP32_STA_CONNECTING before
validating the security parameters and before the synchronous calls
into the ESP Wi-Fi library. Every synchronous error return after that
point leaves the state at CONNECTING: the entry gate then rejects all
subsequent connect attempts with -EALREADY, and since no connection
was ever initiated, no Wi-Fi event will arrive to reset the state.
One failed connect (unsupported security mode, enterprise
configuration failure, esp_wifi_set_config() or esp_wifi_connect()
error) permanently wedges the interface until reboot.
Restore ESP32_STA_STARTED on all synchronous error paths so the
driver is ready for the next attempt.
Observed in the field on ESP32-C6: a provisioning request carrying an
SAE security mode on a build without CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE
returned -EINVAL once and the interface could never reconnect again
without a power cycle. Fix carried as a downstream patch on v4.3.1 and
v4.4.1 and validated on hardware there.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Signed-off-by: Linus Rüttimann <linus@noxblanc.com>
Add support for the Texas Instruments ADS7828 12-bit and ADS7830
8-bit 8-channel I2C ADCs. The two parts share one command byte and
channel permutation and differ only in resolution, so one source file
covers both. ADS7828-Q1 reuses the ADS7828 compatible.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
channel holds the last zero-based channel index an LED occupies,
so a value equal to max_channels is already one past the last
valid channel. Reject it, matching the count-based check in
write_channels.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
