DT_INST_0_ST_LPS22HH_CS_GPIO_CONTROLLER should be
DT_INST_0_ST_LPS22HH_CS_GPIOS_CONTROLLER, which is the name generated by
gen_defines.py.
Discovered while working on unrelated removing of special-casing for
clocks.
Co-authored-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
By this commit user gets possibility to register USB
device satutus callback. This callback represents device state
and is added so user could know what happend to USB device.
Callback is registered by providing it to usb_enable()
USB api is extended by this callback handler.
Samples using using USB are by default provide no callback
and the usb_enable() is called with NULL parameter.
Status callback registered by hid class is deleted as now
USB device has global callback for all classes within device.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
The SPI SERCOM peripheral found on the SAMD5x/SAME5x is very much alike
the one found in previous SAM0 MCUs.
Only the clock setup is different.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
The conversion of struct cipher_ctx * to mtls_aes_context * happens in
a bunch of places. Add a macro MTLS_GET_CTX() to simplify this.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
Add support for AES CBC mode of operation in mbedTLS shim driver.
Refactor mtls_session_setup() to allow multiple cipher modes to
co-exist.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
Add support for the ST STM32G0316-DISCO development board. This board
features an ST STM32G031J6 MCU on a breakable SO8 to DIL8 module, a user
LED and a button.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
The STM32G0 series of MCUs only has one APB, but two reset and clock
enable registers. Fix enabling/disabling the clock and getting the rate
for peripherals in the second register.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
If possible, allow sending 16bits at once instead of 8bits. I found
large delays (up to 3us) between sending bytes due to Zephyr SPI
overhead, so allowing 16bits at a time if possible helps save that
time.
Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
net_pkt_write() function returns 0 on success. But in this driver a
warning is thrown when zero is returned. Hence fix the driver to throw
the warning only when the negative value is returned.
Signed-off-by: NavinSankar Velliangiri <navin@linumiz.com>
sam0 and stm32 specific interrupt controller headers are meant to be
public, and as such should be found in
include/drivers/interrupt_controller and not in
drivers/interrupt_controllers.
Fixing documentation issues as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If it is such a thing (a CAVT intc), it will not be targeting Intel
s1000 SoC only. UP squarde ADSP use the same intc. So renaming it to
CAVS. Though CAVS name might be wrong (CAVS being an overall
architecture name, and not an IP block specification).
Reducing the amount of lines by using if/endif as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Pattern being <domain>_<model>.<c/h>.
Here interrupt_controller as a domain would be far too long so
shortening it to "intc", as DTS does actually.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
wdt_install_timeout() was skipped as it installs an ISR-context
callback handler function. The rest are simple wrappers.
Added myself as the maintainer of the syscall handlers. WDT
subsystem appears to not currently have an owner.
Fixes: #21432
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.
Changes:
- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test
Test: spi_loopback test passed
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
The GPT based counter is a count up timer.
This fixes counter_basic_api tests.
Fix over 80 chars coding style issue.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Cleanup around COND_CODE_1 usage and replacing with
IF_ENABLED if applicable.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Low frequency and high frequency clocks had separate devices
while they are actually handled by single peripheral with single
interrupt. The split was done probably because opaque subsys
argument in the API was used for other purposes and there was
no way to pass the information which clock should be controlled.
Implementation changes some time ago and subsys parameter was
no longer used. It now can be used to indicate which clock should
be controlled.
Change become necessary when nrf5340 is taken into account where
there are more clocks and current approach would lead to create
multiple devices - mess.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
OpenThread recently introduced CMake build system into its repostiory
so we no longer need autotools to build OpenThread libraries and can
integrate them natively.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
NRF devices hardware has flash protection which doesn't
reflect flash API definition well. So fare protection
mechanism was emulated by the software and the driver deals
with hardware flash protection on its own.
Recent change to protection behavior requirement allows
to remove flash API behavior emulation at all.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Setting EEPROM_STM32 with `default y` under `if SOC_FAMILY_STM32`
overrides `depends on SOC_SERIES_STM32L1X` in EEPROM_STM32
definition.
Then, if ever EEPROM is set in any file (as in
tests/drivers/build_all`), EEPROM_STM32 will be indeed set,
with potential issues on series where driver is not yet correctly
handled.
Fix this by removing EEPROM_STM32 definition in STM32 generic
file and set `default y` along with the `depends on` to keep
it effective.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Uses the generated device tree macros, DT_NXP_LPC_USART_USART_*, in the
mcux flexcomm driver and removes the now unused dts fixups from the
lpc54xxx and lpc55xxx socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Renames the lpc usart shim driver to more accurately reflect the
flexcomm hardware IP and to prepare for instantiating it on an SoC
outside the LPC family.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add initial Atmel at86rf2xx transceiver driver. This driver uses device
tree to configure the physical interface. The driver had capability to
use multiple transceiver and systems with multiple bands can be used.
With this, 2.4GHz ISM and Sub-Giga can be used simultaneous.
Below a valid DT example. This samples assume same SPI port with two
transceivers.
&spi0 {
status = "okay";
label = "SPI_RF2XX";
cs-gpios = <&porta 31 0 &porta 30 0>;
rf2xx@0 {
compatible = "atmel,rf2xx";
reg = <0x0>;
label = "RF2XX_0";
spi-max-frequency = <7800000>;
irq-gpios = <&portb 2 0>;
reset-gpios = <&porta 3 0>;
slptr-gpios = <&portb 3 0>;
status = "okay";
};
rf2xx@1 {
compatible = "atmel,rf2xx";
reg = <0x1>;
label = "RF2XX_1";
spi-max-frequency = <7800000>;
irq-gpios = <&portb 4 0>;
reset-gpios = <&porta 4 0>;
slptr-gpios = <&portb 4 0>;
status = "okay";
};
};
At the moment driver assume two transceiver are enouth for majority of
appications. Sub-Giga band will be enabled in future.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
It is possible that the network interface is not yet initialized
when status of the PHY changes. In this case we must not call
net_eth_carrier_on() as that will cause a crash.
This was noticed with mimxrt1050_evk board.
Fixes: #21257
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Enable ESPI OOB channel by default in XEC driver.
Enable OOB channel transmit interrupt and handle OOB up/down correctly.
Change interrupt clearing, clear low level interrupt bits in subhandlers
and high level interrupt in aggregate handlers at the end.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
MCHP I2C spec recommends that for repeated start update control register
De-assert ACK in preparation for NACK to end transfer.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Newer SoCs like SAME54 provide dedicated registers to store
the USB trim configuration.
Use those registers if they are defined in ASF to access the
calibration data.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
On newer sam0 SoCs peripherals are enabled through the MCLK
instead of the PM register.
Use the MCLK register if it's availiable.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Newer SoCs like SAME54 have multiple IRQs for the USB peripheral.
Automatically enable all IRQs configured in the DTS.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Adds a shim layer around the mcux lpc flexcomm driver to adapt it to the
zephyr spi interface. It leverages heavily from the existing mcux dspi
shim driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
