Make sure that when e.g. CONFIG_SERIAL is set, CONFIG_UART_SAM0 is
selected automatically when the sam0 SoC family is used.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Add GPIO support to stm32wb series.
Only ABCDE and H ports are available for now on this series.
Accordingly, update series dtsi file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support to stm32wb series in stm32 clock_control driver.
Ip is similar to stm32l4 one but AHB bus presacler is renamed
to "CPU1" and CPU2 and AHB4 prescalers should be defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Implementation of AMS (Austria Micro Systems) ENS210 temperature and
relative humidity sensor.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
In order to generalize the currently specialized nRF51 IC setup hook,
make the following changes:
- Generalize the hook to bt_ic_setup()
- Use a weak NOP version by default
- Move the currently existing one to the board folder
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
nRF9160 can't provide FICR data while operation in non-secure
domain.
This patch start using flash layout properties provides by
nrfx API for get flash properties, which resolves problem
described above.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Introduce nrfx_nvmc driver into nordic flash driver implementation.
Thanks to that nrf9160 SoC becomes supported by the driver.
nrfx helps dealing with differences with interface to the NVMC
in secure and non-secure execution modes.
This patch adds NRFX_NVMC Kconfig entry for enabling nrfx_nvmc and
select it along with nordic flash driver.
Disabled UICR operation on nRF9160 for non-secure build
as UICR is not available in this mode.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Add driver support for Atmel SAM0 device ID, which is 16-bytes long.
The device ID can simply be read from memory at a known location, but
the location is only described in the data sheet, not in ASF.
For SAMD2x it's 0x0080A00C, 0x0080A040, 0x0080A044 & 0x0080A048.
For SAMD5x it's 0x008061FC, 0x00806010, 0x00806014 & 0x00806018.
This adds a new property to the device tree to define the device ID
registers for this SoC family.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Added option to have LFCLK synthesized from HFCLK. It is not low
power but ensures constant relation between HFCLK and LFCLK and
might be useful in certain scenarios (e.g. testing).
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add driver and device tree binding for the Low Power Inter-Integrated
Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Use the RV32M1 SoC intmux driver initialization priority set by
Kconfig. Change the default to match the default value of 40 used
before.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
I does make sense to use index only after we make sure it is valid,
issue is found in harness tests.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
In stereo case the pdm stream continuosly alternates 1-bit from
the left channel with 1-bit from the right channel. In this case
we need first to demultiplex channels bits on byte basis.
Then the Open_PDM_Filter library has to be called twice, one for
each channel.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Add support for pulsing the hardware reset pin of the FXOS8700 high
during initialization.
According to the datasheet, this is required for the I2C/SPI bus
auto-detection logic to work properly if the VDD/VDDIO power
sequencing order cannot be guaranteed.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
gpio_intel_apl_read() should set *value to 1, not 2, when the
GPIO input is a logical high.
Fixes: #15499
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
For STM32L47x/48x series devices, register ASCR should be configured to
connect analog switch of gpio lines to the ADC.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Allows to enable initial RTS/CTS hardware flow control
in the dts.
Co-authored-by: Benoit Leforestier <benoit.leforestier@gmail.com>
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Reformat L4 pinmux to be consistent with other pinmux files,
and for a better reading.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Fixed using chipselect with seperate chipselect GPIOs and how they were
referenced from/in DeviceTree.
Also configure the device during initialization so it's ready to go
after init.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Adjusted the MCP2515 driver to switch from KConfig SPI configuration to
DTS based configuration.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
The MCP2515 is a CAN controller that can be connected via SPI to an
host MCU. This driver adds support for the MCP2515 as a new driver in
the CAN subsystem.
As it is a SPI peripheral it uses a thread for its interrupt
handling and the received message filtering is done inside this
interrupt thread, as the MCP2515 filter capabilities are not sufficient
for the Zephyr CAN interface.
The driver was validated with an external CAN logger and the adjusted
CAN sample application.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
The following fix:
commit c8b17ec403
Author: Tobias Aschenbrenner <tobias.aschenbrenner@blik.io>
Date: Tue Dec 18 14:16:00 2018 +0100
fix: kw41z: Use correct mapping for dBm
Was using SYS_LOG_INFO and should be using LOG_INFO.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Enable the clock for GPIO ports on the RV32M1 SoC before attempting to
access the port controller registers.
Fixes: #15339
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
According to documentation Compare event will not be triggered
if CC=0 and CLEAR task is set. Added handling of that situation.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
