The receive flag extraction used a compound shift assignment,
writing the right-shifted value back into the volatile MU status
register as a side effect. Use a plain shift into the local.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
uart_stm32_async_rx_disable() forced RXNE on and left the ERROR
interrupt enabled, causing per-byte/per-overrun ISR load on continuous
RX streams.
Keep async and interrupt-driven RX ownership separate: async disables
RXNE on enable and, on disable, only tears down async state and
disables ERROR. RXNE remains off; callers that switch back to
interrupt-driven RX must re-enable it via uart_irq_rx_enable().
This avoids ISR flooding for async users and matches API ownership.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
This adds support for the ARM Corstone System Architecture Specification
Ma2 (ARM CRSAS-MA2) Watchdog Timers.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Co-authored-by: Wojciech Sipak <wsipak@antmicro.com>
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
nPM10 devices' GPIO pins multiplex a lot of different functions. To avoid
application-side misconfiguration, an internal arbitration function was
added.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Add a display driver for the LeveTop LT7680. This was tested with the
sample `zephyr/samples/subsys/display/lvgl`.
While this display should theoretically support all 4 orientations, I only
managed to get it working with 0 and 180 degrees, so the driver only
supports these for now.
Signed-off-by: Thomas Fischer <thomas.fischer@jumo.net>
Co-authored-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Add a test to only process the TC and TCR interrupts if they are
enabled for the corresponding peripheral (indicated by the TCIE bit in
the CR1 register). This prevents processing twice transfer complete
sequence in case the I2C interrupt is shard between 2 I2C buses.
Update sample counter only when a sample is effectively transferred
when DMA is not used.
This change prevents de-synchronization issues for example when the I2C
bus interrupt is shared when another I2C bus and interrupt can be
triggered while there are no samples no transfer. Note that the change
in TC/TCR interrupt status is synced with the change made in the non-RTIO
driver by commit ffbc63efcb ("drivers: i2c: stm32: fix issue with shared
interrupts") that fixed issue #109993.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix an issue seen on STM32C0xx/G0xx/L0xx/U0xx where controller fails
the receive data due to DMA being armed after I2C transfer have started.
Arm DMA and enable the transfer interrupts before generating the
(repeated) START condition. The STM32 I2C controller can buffer only
two received bytes (RXDR plus the shift register) before it stretches
the clock. If the START were issued first, the controller could start
clocking bytes in while the DMA setup (dma_config()/dma_start()) is
still ongoing; on slow parts RXDR would never get drained and the
transfer would stall. Issuing START last guarantees that DMA is ready
to service the very first byte.
Assisted-by: Claude Opus 4.8
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Enable CONFIG_I2C_STM32_V2_DMA by default if at least a compatible
and enabled I2C device node defines 'dmas' DT properties.
Remove the EXPERIMENTAL state of I2C_STM32_V2_DMA config symbol since the
feature is now mature enough to be used.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Allow using DMA only in one direction and don't use DMA on read
messages when destination buffer is not aligned on cache line size
to prevent cache invalidation affects nearby data.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Do not enforce use of DMA in STM32 I2C non-RTIO driver when
CONFIG_I2C_STM32_V2_DMA is enabled. Instead, rely on the devicetree
device node providing or not a DMA configuration.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Convert cached flash addresses to non-cached flash addresses in Realtek
Bee DMA driver. Without this conversion, DMA may access an invalid flash
mapping and read back 0xdeadbeef.
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add UART asynchronous driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Asynchronous TX/RX transfers
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Use same window settings for both MIPI and DVP mode, helping reducing
the code size of the driver as well.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
In preparation for making DVP frmrate handling common with the existing
MIPI one, rename the structure ov5640_mipi_frmrate_config into
ov5640_frmrate_config as well as associated tables.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Avoid setting the output format as part of init_common_dvp since
this is set via the ov5640_set_fmt function as well.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
HFLIP/VFLIP settings are already done as part of the common init
sequence so avoid changing them specifically in the dvp part as
this is also accessible via dedicated controls.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Perform the sensor ID register check first before doing anything
else after the reset of the sensor.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Use BIT64() for the chain length limit, compare pointers against
NULL and drop a store already covered by the memset().
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Read avail->idx from shared memory once, replace the modulo with a
mask since queue sizes are powers of two, and make the helper void
as it cannot fail.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Carve the free descriptor stack storage out of the virtqueue
allocation instead of relying on a second, hidden k_malloc() in
k_stack_alloc_init(), whose return value was not checked.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
With K_FOREVER and no free descriptors, virtq_add_buffer_chain()
slept in k_stack_pop() while holding the queue spinlock. Pop
descriptors before taking the lock, rolling the chain back on
failure, so the lock only guards the available ring update. The
free descriptor count is now updated under the lock so it stays
coherent on SMP, and finite timeouts actually wait as documented
instead of failing immediately.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
virtq_add_buffer_chain() with bufs_size == 0 would write
recv_cbs[0xffff] out of bounds and publish a bogus descriptor index
to the device. Return -EINVAL instead.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Little-endian converted values were used as array indexes and
descriptor fields were stored without conversion, which is broken on
big-endian targets. Index with CPU-order values and convert the
addr/len/flags/next fields when writing the descriptor table. No
functional change on little-endian targets.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
format_map[] is keyed by the Type A (6800) bus-width constants
(MIPI_DBI_MODE_6800_BUS_{8,9,16}_BIT = 0x5/0x4/0x3), but
mcux_dcnano_lcdif_dbi_get_format() compared each entry's key
against `bus_type - MIPI_DBI_MODE_6800_BUS_16_BIT`. That subtraction
correctly normalizes the Type B (8080) values 0x6/0x7/0x8 down to
0x3/0x4/0x5, but it also shifts the Type A values 0x3/0x4/0x5 down
to 0x0/0x1/0x2 which do not exist in the map. As a result every
6800 mode returned -EINVAL from configure(), even though the switch
above accepts the same three modes and selects
kLCDIF_DbiTypeA_FixedE, and mipi-dbi-device.yaml lists all three
as valid mipi-mode values.
Only normalize the Type B values before the lookup so both bus
types resolve correctly. The 8080 path is byte-for-byte identical
to what it does today.
Fixes#114739
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Add a disk_access driver for virtio,blk devices.
It supports negotiated block size and scatter-gather requests.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Currently, it is possible to link a IEEE802.15.4 build with
stale blobs. Add blobs verify directive to enforce blobs version
check while building.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
The esp_ieee802154_energy_detect_done() runs from the radio ISR.
Defer the energy_scan_done callback to a workqueue so it is invoked
from thread context instead of ISR context.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Use the active channel's configuration when converting raw sensor data
to frequency and capacitance.
The conversion helpers were using cfg->ch_cfg->fin_sel and
cfg->ch_cfg->inductance, which always reference channel 0. This gives
incorrect results for multi-channel configurations where channels use
different fin_sel or inductance values.
Index ch_cfg with the selected channel so each conversion uses the
correct per-channel configuration.
Signed-off-by: Sundareswar Palanichamy <sundareswarp@gmail.com>
lis2dh_fetch_xyz did not return -ENODATA when LIS2DH_STATUS_DRDY_MASK
was clear. Because the successful read returned 0, the data-ready check
was masked and old data was silently reported as fresh.
Signed-off-by: Markus Grafen <markus.grafen@medicassist.de>
When CONFIG_SYSTEM_TIMER_LPM_COMPANION_COUNTER is used to keep time across
a low-power state, sys_clock_idle_exit() reconstructs the elapsed time
and announces it to the kernel. Two intermediate values were computed
in 32 bits, which overflows once a single low-power sleep exceeds 2^32
core cycles (~134 s at 32 MHz):
- dcycles (the unannounced cycle delta) was uint32_t. Truncation
makes the announced tick count far too small, so k_sleep() never
completes and the MCU appears to never wake from STOP.
- announced_cycles += dticks * CYC_PER_TICK evaluated the product in
32 bits before adding to the 64-bit accumulator. Truncation under-counts
announced_cycles by a multiple of 2^32, so each subsequent sleep's
dcycles is too large and kernel time runs progressively fast.
Widen dcycles to 64 bits and cast the multiply to cycle_t so both
operations are performed in 64 bits. Only affects builds with a 64-bit
cycle counter (CONFIG_CORTEX_M_SYSTICK_64BIT_CYCLE_COUNTER) using the
counter companion; verified on STM32L151 (32 MHz core, LSE RTC companion)
with 5- and 9-minute STOP intervals.
Signed-off-by: Markus Grafen <markus.grafen@medicassist.de>
Assisted-by: Claude:claude-opus-4.8
STM32 I2C bus recovery bitbangs the scl-gpios/sda-gpios pins
through the GPIO API, but I2C_STM32_BUS_RECOVERY never pulled in
GPIO. The build relied on the ST board defconfig to enable
CONFIG_GPIO; since commit 90b9c954f0 ("boards: st: *: don't
enable CONFIG_GPIO by default") the drivers.i2c.build.bus_recovery
build on nucleo_f411re fails to link with undefined references to
the GPIO ports named by the I2C node (those properties were added
to ST boards by commit 56e96eef9b).
A select GPIO is not possible here: the symbol lives inside the
if I2C block and selecting GPIO from there creates a recursive
Kconfig dependency. Use depends on GPIO instead - all recovery
code in the driver is already guarded by
CONFIG_I2C_STM32_BUS_RECOVERY, so the feature simply stays off
without GPIO - and enable CONFIG_GPIO explicitly in the
bus_recovery test scenario so it keeps building the recovery path.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The HD44780 driver is a purely GPIO-driven LCD controller: the
register-select-gpios, enable-gpios and data-bus-gpios properties
are required by the binding and driven through the GPIO API, but
AUXDISPLAY_HD44780 never pulled in GPIO. The build relied on the ST
board defconfig to enable CONFIG_GPIO; since commit 90b9c954f0
("boards: st: *: don't enable CONFIG_GPIO by default") the
nucleo_f746zg auxdisplay sample build fails to link with undefined
references to the GPIO port devices. Select GPIO unconditionally
since the driver cannot function without it.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The generic cellular modem driver embeds gpio_dt_spec entries for
the power, reset, wake, ring, dtr and status pins and drives them
through the GPIO API, but MODEM_CELLULAR never pulled in GPIO. The
build relied on the ST board defconfig to enable CONFIG_GPIO; since
commit 90b9c954f0 ("boards: st: *: don't enable CONFIG_GPIO by
default") the b_u585i_iot02a cellular_modem sample build fails to
link with an undefined reference to the GPIO port referenced by the
modem's mdm-power-gpios. Select GPIO unconditionally: the specs
span six properties across all vendor compatibles, and physical
modems need at least a power or reset pin (the BG9x binding marks
mdm-power-gpios as required), so a per-property conditional select
is not worth the complexity here.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The NT35510 driver drives its optional reset-gpios and bl-gpios
pins through the GPIO API, but its Kconfig never pulled in GPIO.
The build relied on the ST board defconfig to enable CONFIG_GPIO;
since commit 90b9c954f0 ("boards: st: *: don't enable CONFIG_GPIO
by default") the stm32h747i_disco build with the
st_b_lcd40_dsi1_mb1166_a09 shield fails to link with an undefined
reference to the GPIO port device referenced by the display node.
Select GPIO when any enabled node has one of these properties,
following the same pattern as the otm8009a and stm32_ltdc drivers.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The OTM8009A driver drives its optional reset-gpios and bl-gpios
pins through the GPIO API, but its Kconfig never pulled in GPIO.
The stm32h747i_disco build relied on the ST board defconfig to
enable CONFIG_GPIO; since commit 90b9c954f0 ("boards: st: *: don't
enable CONFIG_GPIO by default") linking fails with undefined
references to the GPIO port devices referenced by the display node.
Select GPIO when any enabled node has one of these properties,
following the pattern used by the stm32_ltdc and stm32_ospi
drivers, since both properties are optional in the binding.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The PWM DALI driver unconditionally uses the GPIO API for its
required rx-gpios pin, but DALI_PWM only selected PWM and COUNTER.
The sample built anyway because ST board defconfigs used to enable
CONFIG_GPIO; since commit 90b9c954f0 ("boards: st: *: don't enable
CONFIG_GPIO by default") the nucleo_f091rc build fails to link with
an undefined reference to the GPIOA device. Select GPIO so the
driver pulls in its own dependency.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
pwm_resume applies the pinctrl from devicetree, sets the gpio to the
idle value, respecting the nordic,inverted flag in the pinctrl nodes.
However, the IDLEOUT register is not set on socs which include this
register. The IDLEOUT register takes precedent over the GPIO setting,
it must thus be set to match the pin polarity, otherwise glitches
will be observed when PWM goes idle, see issue #114343.
This commit adds setting the channel idle state as part of pwm_resume.
An nrfy function is used since the nrfx_pwm driver sets this idle
states on nrfx_pwm_init, which is run before pinctrl is set, and thus
before the driver is able to get the nordic,inverted setting, since
it reads this by reading the pin out setting set by pinctrl.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Mark an IPI child enabled before unmasking its interrupt. Otherwise, a
pending interrupt can run the ISR while the child still appears disabled,
leaving its status uncleared and trapping the CPU in an interrupt storm.
Mask the interrupt before marking the child disabled so the ISR cannot skip
a channel while its interrupt is still unmasked.
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Add typed wrappers for XENMEM_increase_reservation and
XENMEM_decrease_reservation using the existing Xen memory-op helper
style. Both operations use struct xen_memory_reservation, so share the
reservation setup with the existing populate-physmap wrapper.
These calls are useful for Zephyr when it runs as a Xen hardware/control
domain, not as ordinary Zephyr heap management. The Xen support already
exposes domain creation, maximum-memory, memory-mapping, grant-table,
and event-channel control APIs. A Zephyr control-domain service or
validation app needs the reservation operations to exercise the same
guest memory lifecycle: ask Xen to adjust a domain reservation, receive
any extent bases returned by Xen, and later return guest frames to Xen
when the domain is torn down or resized.
Keep this as a typed Xen wrapper instead of adding a Zephyr memory
subsystem driver. A real balloon or memory-hotplug driver would need a
policy for which frames can be removed, coordination with Zephyr's
allocator, and ownership of runtime memory pressure. This patch only
exposes the stable Xen ABI primitive needed by that future policy and by
control-domain test code.
Signed-off-by: Vladyslav Goncharuk <vladyslav_goncharuk@epam.com>
