GPIO isolation during sleep leaves all pins floating, for power saving.
In some configurations the UART peripheral will remain ON during sleep
and can be affected by signal shifts in the pins. Use the pad hold
function to leave signals recessive and avoid spurious UART events
which can dirty the FIFO and leave pending interrupts which can
stall the system.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Attach the hardware capture of received PTP frames to the packet
and request a transmit timestamp when the network stack asks for
one, so PTP can measure the time frames crossed the wire.
The receive capture is latched from the last descriptor before it
is returned to the DMA, and the transmit capture is read back from
the first descriptor once the DMA releases it.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Expose the IEEE 1588 clock provided by the Ethernet MAC as a PTP
clock device, so applications can read, set, offset and rate
adjust it through the PTP clock API.
The reference frequency is queried from the clock control driver
instead of being assumed, and only PTP frames are timestamped.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add SoC and devicetree support for the R-Car Gen4 R8A779G0 A76.
Co-authored-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Fix the integer-to-pointer cast warning by casting through uintptr_t
when converting clk->rate to clock_control_subsys_rate_t on 64-bit
environmet.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Switch the Cadence SPI driver to use the DEVICE_MMIO API instead
of directly accessing the physical base address from the devicetree.
This is required to support platforms with an active MMU (such as the
Cortex-A9 on Zynq 7000), where accessing unmapped physical addresses
causes MMU translation faults.
Closes#113693
Signed-off-by: Simon Maurer <mail@maurer.systems>
The ACI_HAL_STACK_RESET command is replaced by ACI_RESET command.
Update comment.
Added endianness management for 32 bits options parameter.
Remove misaligning.
Signed-off-by: Eric Mechin <eric.mechin@st.com>
Don't allow enabling the STM32 pinctrl driver if no GPIO port is enabled
as this would cause a build error in the GPIOport manager module.
If no GPIO port is enabled, the pinctrl driver is useless anyways.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
It is relatively common (at least for nRF93M1, Telit LE910) that channel
configuration commands such as `ATE0` that are normally sent during the
`init` script are not actually carried over to the DLCI channels opened
with CMUX.
Enable vendor implementations to provide a script that should be run
after a DLCI channel is opened to re-apply these configurations.
Note that this script is NOT automatically run for user DLCI channels,
as the `modem_cellular` is not responsible for opening these pipes.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add board overlays and platform_allow / filter entries so the measure_freq
and check_freq samples and the clock_monitor_api test run on the
FREQME-capable frdm_mcxa153, frdm_mcxa156, frdm_mcxa266, frdm_mcxa344,
frdm_mcxa366, frdm_mcxa577, frdm_mcxn236, mcx_n5xx_evk (MCXN547),
mcx_n9xx_evk (MCXN947), frdm_mcxl255 and mimxrt700_evk (MIMXRT798S) boards.
The nxp,freqme driver does not enable the clocks it measures, so on MCXN -
where the FRO_12M / FRO_HF distribution to the Frequency Measure mux is
gated until clock_control_on() - the samples and test enable the measured
source clocks at startup. The clocks are declared independently of the
monitor in a "clock-monitor-required-clocks" (samples) /
"test-required-clocks" (test) node, added with new bindings, that the
application turns on before configuring; boards whose sources are always
running omit the node.
Extend the clock_monitor_api test with a set_source case that switches the
reference and target between declared sources and re-measures to confirm
the switch took effect, driven by per-instance "switch-reference" /
"switch-target" / "switch-target-expected-hz" properties added to the
test-clock-monitor fixture binding and to the FREQME board overlays.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Enable clock_control_get_rate and clock_control_on for FRO_HF,
FRO_HF_DIV, FRO_12M, CPU/AHB and external clock rates.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a clock_monitor back-end for the NXP FREQME (Frequency Measurement)
peripheral, wrapping the MCUX lpc_freqme HAL. It supports MEASURE
(one-shot) and WINDOW (continuous MIN/MAX threshold) modes, queries the
reference rate from clock_control, and enables the peripheral gate through
clock_control. It does not enable the reference or target source clocks -
the application must ensure they are running before configure()/start();
the driver only routes and measures them.
Reference and target clocks are selected from devicetree-declared source
lists ("reference-sources" / "target-sources"); each source pairs an
INPUTMUX route with a frequency provider (a "clocks" phandle or a fixed
"clock-frequency"). clock_monitor_set_source() switches the reference and
the target between the declared sources at runtime and drops the device
back to unconfigured state, so the next configure() re-derives REF_SCALE
and the WINDOW thresholds. Reference sources must resolve a frequency;
target sources may omit one, since the target rate is measured, not
predicted.
This includes the devicetree binding, the INPUTMUX connection-cookie header
with per-family cookies (MCXA, MCXC, MCXN, MCXL, MCXW and RT700) plus the
NXP_FREQME_SOURCE_UNCHANGED sentinel, and the syscon clock identifiers used
to query the FRO / CPU-AHB / external clock rates and to gate FREQME.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Receive interrupts can arrive before the ENET_QOS DMA has completed the
regular and context descriptor writebacks used for PTP RX timestamps.
Add a short bounded wait for the context descriptor ownership handoff
and timestamp status bits before extracting the timestamp.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
Use xen_sched_yield() in the Xen HVC UART driver instead of calling the
low-level scheduler hypercall entry point directly.
This keeps the driver on the public Xen scheduler helper API while
preserving the existing behavior. The driver still yields the current
VCPU when the TX ring is full so the console backend can consume data.
Signed-off-by: Vladyslav Goncharuk <vladyslav_goncharuk@epam.com>
Assisted-by: Codex:gpt-5 cpp-code-map
Add typed helpers for Xen scheduler operations used by Zephyr guests and
management code:
- yield; block; poll; shutdown; remote shutdown; shutdown code; pin
override.
The raw hypercall entry point remains available for low-level code, but
normal Zephyr callers should not need to depend on the
architecture-specific hypercall header or build Xen ABI request
structures by hand. Keep these operations under <zephyr/xen/sched.h>,
matching the existing Xen wrapper style.
Signed-off-by: Vladyslav Goncharuk <vladyslav_goncharuk@epam.com>
Assisted-by: Codex:gpt-5 cpp-code-map
DRIVER_FEATURES is a write-only register per the virtio specification
(4.2.2.2), but virtio_mmio_write_driver_feature_bit() did a
read-modify-write on it. Reads return 0, so every call only ever wrote
the single current mask bit and erased all feature bits previously
written to the same 32-bit word -- e.g. a device driver negotiating a
feature bit in word 1 (bits 33..63) silently dropped VIRTIO_F_VERSION_1
set during transport init.
Accumulate the feature bits in a per-device shadow and write complete
words instead. This also drops the sys_cpu_to_le32() applied to the
mask, which was wrong because virtio_mmio_write32() already performs
the conversion (a no-op on little-endian hosts, corruption on
big-endian ones).
Fixes#115150
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
virtio_mmio_reset() passes VIRTIO_MMIO_STATUS to
virtio_mmio_read_status_bit(), but that macro is the register offset
(0x70 = 112), not a bit number. The loop condition therefore evaluates
read32(STATUS) & BIT(112), which is always 0, so the driver never
actually waits for the device to complete the reset (and BIT(112) is
shift-count-overflow UB on 32-bit platforms).
Poll the status register value instead, as required by the virtio
specification (4.2.2: after writing 0 to Status, the driver must wait
until it reads back 0).
Fixes#115149
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
The patch ad42613252 added GPIO_DISCONNECTED support
for gpio_mcux_port_configure, but port_get_direction was not updated
accordingly.
port_get_direction() only checks PDDR to determine pin direction,
so a disconnected pin (PDDR cleared) is incorrectly reported as an
input. This causes the gpio_get_direction.test_disconnect test to
fail on boards using the PORT-based gpio_mcux driver.
Check PORT PCR and PDDR state to identify disconnected pins and
exclude them from direction results, so they are reported as
neither input nor output per the Zephyr GPIO API contract.
Fixes: #114432
Assisted-by: Claude:opus-4.6
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
The weekday field was masked with 0x08, which zeroes every valid
1-to-7 value, so the day of week was never stored and always read
back as -1. Use the 3-bit mask 0x07 for both the pack and unpack
sides.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
(~SPEED_Msk | ~SDAHOLD_Msk) is all-ones for disjoint fields, so
reconfiguration never cleared the old SPEED/SDAHOLD bits. Use
~(SPEED_Msk | SDAHOLD_Msk).
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Extended sleep interval is the period during which STA will stop all
types of TX/RX. Through this command user can configure the quiet period.
Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
Add ext1-pwren-gpios binding to nxp,wifi.yaml for M.2 module VPCIe_3V3
power control. On imx91 (AArch64), GPC is not available so read
WL_WAKE_HOST GPIO directly via wakeup_gpios DT property instead.
Use CONFIG_PM_MCUX_GPC to guard fsl_gpc.h include, which is more
precise than excluding by SoC series.
Signed-off-by: Li Long <li.long@nxp.com>
The counter-backed RTC wrapper is the only RTC driver that depends on
another device: it fetches and calls its parent counter device during
init, so it must initialize after the counter. It previously reused the
shared RTC_INIT_PRIORITY symbol, whose default is not guaranteed to
order the wrapper after the backing counter, so each board and test had
to override CONFIG_RTC_INIT_PRIORITY to build reliably.
Introduce a wrapper-scoped RTC_COUNTER_INIT_PRIORITY (default 70) used
only by rtc_counter. The shared RTC_INIT_PRIORITY default is left
unchanged for all other RTC drivers, and consumers of the wrapper no
longer need per-board init-priority overrides. Correct ordering is
verified at runtime by the device_is_ready() check on the backing
counter during init.
Signed-off-by: Harini T <harini.t@amd.com>
This reverts commit 713cdff118.
Build error:
ERROR: /soc/mmc@ee140000 <rcar_mmc_init> is initialized before its
dependency /regulator_1p8v <regulator_fixed_init>
ERROR: ... /regulator_3p3v <regulator_fixed_init>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This reverts commit f9bed91088.
build error:
Build failure - error: static assertion failed: "cpu0 clock-frequency
does not match HSE * mul"
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
set the default of SDHC_INIT_PRIORITY to
KERNEL_INIT_PRIORITY_DEVICE, just like at the other
driver priorities.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit adds a new DT control `hsi-prediv` for `wch,ch32v20x_30x`
devices and compile-time checks to ensure the clock configuration is valid.
This allows control of the internal clock divisor to be able to reach the
full 144MHz when using the internal clock source (`HSI`).
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
Writes/erases use the indirect interface and don't update the D-cache, so
memory-mapped reads returned stale data once the cache was enabled.
Invalidate the affected range on write/erase completion.
Assisted-by: GPT-5.3-Codex
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add HL78XX_MODEM_INFO_FW_VERSION to the public modem API and
return the modem firmware version through get_modem_info().
Also introduce a configurable desired firmware version option
for firmware validation and diagnostics.
Signed-off-by: Zafer SEN <zafersn93@gmail.com>
Replace the generic initialization-failure handling path with a
rule-based recovery framework for HL78xx modem chat scripts.
The new recovery mechanism captures script failure context,
including the failed script, command index, request, and result,
and uses this information to select a targeted recovery action.
Successful recovery is tracked and verified before the failure
state is fully cleared.
Key changes include:
- Introduce a dedicated RECOVERY state
- Capture and preserve script failure context
- Add configurable recovery rules and recovery actions
- Track recovery attempts and enforce retry limits
- Add helpers for clearing and confirming recovery state
- Recover corrupted KBNDCFG band configuration automatically
- Recover post-restart KSUP configuration timeouts
- Extend modem chat APIs to expose the active script and command
- Remove the legacy diagnostic-script recovery path
- Simplify restart fallback handling and recovery lifecycle
- Remove the obsolete script failure counter
This improves modem robustness by enabling targeted recovery of
known script failures while avoiding unnecessary modem resets
and full reinitialization sequences.
Signed-off-by: Zafer SEN <zafersn93@gmail.com>
Rename the PMC configuration script state leave handler to
better match the associated state and follow existing handler
naming conventions.
This is a non-functional change that improves code clarity and
consistency within the HL78xx state machine implementation.
Signed-off-by: Zafer SEN <zafersn93@gmail.com>
The buffer size validation compared buffer_size (bytes) against
num_channels (sample count), allowing undersized buffers to pass.
The byte count was then stored in results_length and used as a
uint16_t slot count in the sample-reading worker, causing
out-of-bounds 16-bit writes.
Fix by:
- Using the shared adc_sequence_validate_buffer() helper to validate
buffer_size against num_channels * sizeof(uint16_t), matching the
common approach introduced for the other ADC drivers
- Storing buffer_size / sizeof(uint16_t) in results_length
- Using post-decrement (length-- > 0) instead of pre-decrement
(--length > 0) to allow the correct number of writes
Assisted-by: Claude:opus-4.6
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Prevent infinite loops when hardware becomes unresponsive
by adding a timeout in TX context allocation.
Signals interface is down and returns -ETIMEDOUT on timeout.
Co-authored-by: Alessandro Nuzzi <alesnu96@gmail.com>
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
This adds support for ARM Corstone System Architecture Specification Ma2
(ARM CRSAS-MA2) System Counter and System Timer.
The HW consists of one 64-byt System Counter, and any number
of System Timers that have match registers to generate interrupts
based on the value of the System Counter.
The timers don't have any counter/timer of their own, meaning that
System Counter can't be started or stopped independently if there is an
enabled System Timer.
Add the crsas-ma2 timer to the test for counters.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Signed-off-by: Krystian Hebel <khebel@antmicro.com>
Some STM32 SAI nodes may expose a shared kernel clock for both sub-blocks,
while others may provide different kernel clocks for sub-block A and
sub-block B.
These changes allow the driver to handle SAI nodes with different kernel
clock layouts. Nodes with sai_ker_ck use a shared kernel clock for both
sub-blocks, while nodes with sai_a_ker_ck and sai_b_ker_ck use
separate kernel clocks for each sub-block.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Modified the Microchip XEC eSPI TAF V2 driver adding support for
MEC174x/5x/165x. We agree with code quality tool analysis the eSPI
TAF register structure is too larger and not maintainable. The driver
now uses Zephyr's system memory mapped register access routines.
quality check tools find the structure too large.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The do_ccc syscall verifier checked the outer payload and the
ccc/targets arrays but operated on the caller's live structure and
did not validate the per-target data buffers, unlike the i3c_transfer
verifier which snapshots its message array before use.
Make the two paths consistent: introduce copy_ccc_and_do(), which
snapshots the payload, allocates a kernel-side copy of the target
array via k_usermode_alloc_from_copy(), and validates each data
buffer with K_SYSCALL_MEMORY() before calling the implementation.
num_targets is capped at 31 as a sanity bound. The driver-written
num_xfer and err fields are copied back to the caller after the
transfer so results still propagate; data buffers are unaffected
as their pointers still reference user memory.
Signed-off-by: Ryan McClelland <rymcclel@gmail.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
rv8263c8_calibration_get() decodes the offset register with the
mode-to-step mapping reversed relative to rv8263c8_calibration_set()
and the application manual: it multiplies fast mode (MODE = 1) by
the 4340 ppb normal mode step and normal mode by the 4069 ppb fast
mode step, so every readback is scaled by the wrong step size.
The signed 7-bit decode is also broken. The register byte is read
into an int8_t, so the MODE bit acts as the sign during integer
promotion, and the branch for a set bit 6 ORs in bit 7 of an
already-positive value: a stored offset of -64 (0x40 with MODE = 0)
reads back as +192 steps. Mask the 7-bit offset field and use
sign_extend(), as rtc_rv8803 does for the same register layout.
With both fixes a set()/get() sequence returns the effective
programmed value at hardware resolution.
Built tests/drivers/build_all/rtc (i2c_devices.overlay) for
qemu_cortex_m3 with CONFIG_RTC_CALIBRATION=y. No hardware run;
register-level analysis against the RV-8263-C8 application manual.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
rv8263c8_calibration_set() masks the mode candidates with
GENMASK(7, 0), so bit 7 of a negative two's complement candidate
lands in the MODE bit of the offset register: every negative
calibration request silently switches the device into fast mode
even when normal mode was selected. Mask with the signed 7-bit
offset field (bits 6..0) instead so the MODE bit is controlled
only by the selected mode.
The function also accepts any int32_t request. Out-of-range values
now return -EINVAL per the rtc_set_calibration() API contract
instead of silently wrapping in the register field. In addition,
the fast mode candidate is only selected when it fits the 7-bit
field: fast mode has the smaller step, so near the range limits
its candidate can exceed the field even though the request itself
is representable in normal mode.
Values previously accepted beyond +/-64 offset steps now fail with
-EINVAL, which is a user-visible conformance fix.
Built tests/drivers/build_all/rtc (i2c_devices.overlay) for
qemu_cortex_m3 with CONFIG_RTC_CALIBRATION=y. No hardware run;
register-level analysis against the RV-8263-C8 application manual.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
CK48 is now moved to separate mode.
It is shared by RNG and USB peripherals. This avoids
collision and also allows checking in RNG driver.
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ ./scripts/check_quoted_includes.py -w drivers/usb/
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
A peer that negotiated ACFC could not talk to us at all. The HDLC
receiver rejected such a frame twice: STATE_HDLC_FRAME_ADDRESS
resynchronised on any first octet other than 0xff, and ppp_process_msg()
dropped whatever survived unless the frame started with 0xff 0x03.
RFC 1662 ch. 3.2 requires accepting both forms.
Let STATE_HDLC_FRAME_ADDRESS fall through into STATE_HDLC_FRAME_DATA for
any non-delimiter octet, which also gives an ACFC frame the 0x7d
unescaping it needs when the Protocol field starts with 0x00, and make
the header removal peek before pulling.
The FCS needs no adjustment: it is computed over the frame as
transmitted, so an ACFC frame simply has fewer octets covered. The
Address and Control fields must not be synthesized back in.
Frames damaged by line noise are no longer rejected on the Address octet
and are now caught by the FCS check alone, which is why
NET_PPP_VERIFY_FCS defaults to y.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Aleksandr Senin <al@meshium.net>
