C45 direct registers access is only supported by the LAN865x internal PHY,
not by the LAN867x external PHY, even though the MAC supports it. Restrict
C45 direct register access to the LAN865x internal PHY. The LAN867x
external PHY supports C45 registers only via indirect access through C22
registers.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Align the LAN865x driver module initialization priority with the default
priorities of MDIO and PHY drivers. The microchip_t1s PHY driver supports
both LAN865x internal PHY and LAN867x external PHY. It was observed that
the microchip_t1s driver initialization priority did not match the
priority sequence used by the GMAC driver when the evb-lan8670-rmii (an
external LAN8670 PHY) was connected to the SAME54 Curiosity Ultra
platform, leading to potential initialization order issues. This change
ensures the correct initialization sequence for reliable operation.
The initialization priorities of the microchip_t1s and mdio_lan865x
drivers are now set to the default values used in Zephyr. The LAN865x
driver init priority is updated to the most appropriate value so that the
microchip_t1s init priority aligns with all MAC drivers, maintaining the
correct initialization sequence.
Since the microchip_t1s driver can be used by many MAC drivers, keeping
the default priority provided by Zephyr is a good approach. Instead,
setting a specific priority for the eth_lan865x driver is more appropriate
to ensure proper initialization order.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Prevent disabling OTG HS and USBPHY clocks
during sleep on STM32U5 series
Disabling these clocks during sleep mode
was causing USB device initialization issues
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Prevent disabling OTG HS and USBPHY clocks
during sleep on STM32U5 series
Disabling these clocks during sleep mode
was causing USB device initialization issues
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
The dmic_mcux driver required a mapping of paired dmics to
specify the same pdm number, and would arbitrarily assign the left
channel of the pair to even dmic channel number and the right
to an odd dmic channel number.
Change this so that the pdm number in the mapping is
used as the dmic channel number, and paired dmics are checked to
specify consecutive pdm numbers (instead of the
same pdm number).
This allows users to control explicitly which dmic
channel to use and whether that dmic channel is left or right,
without this arbitrary indirect mapping. This is important
in case they want a dmic that is wired to be right channel
to be assigned to dmic channel 0, which is the only channel
that supports hwvad.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Enable driver to consume RTK data-correction messages published
in order to enhance GNSS Navigation results.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
So this API can be used to send frames with a different encoding than
UBX. This enables UBX drivers to send RTCM3 correction frames using UBX
API, without having to switch over modem pipes.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
LUT sizes directly reflects the global data when enabled in dts
(even if no or few pins are really consumed). Also the PINCM
numbering across the series (g, l and c) is within 255, so fix
to use uint8_t to save the global space.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
All the HAL API/wrapper depends on PINCM indexing, which cannot
be derived from neither pin number nor the address offset.
With current approach, update the LUT table of possible PINCM's
for L series with GPIO A, B and C banks.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
although udiv is represented in clock tree of L series, this is
not really present or controllable from SYSCTL registers. Enable
udiv only if present in dts.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Differential mode support consists of:
- If differential mode is supported by the underlying hardware AND at
least one differential channel is enabled in the devicetree for this
ADC instance, then perform a differential mode calibration in addition
to the usual single ended calibration during initialisation.
- Set channels to the appropriate differential or single ended mode
during channel setup.
Currently the N6 series is not supported even though the underlying
hardware supports differential mode, due to complications in the
calibration procedure.
Signed-off-by: Matt Rodgers <mrodgers@witekio.com>
Co-authored-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
TI MSPM0 timer module has capture block used to capture timings of input
signal. Add a support for TI MSPM0 PWM capture.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Configure the initial pin state of the SPIM peripheral to SLEEP, not
DEFAULT. This fixes the pins being configured in DEFAULT until the first
time the interface is used if `zephyr,pm-device-runtime-auto` is
enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
A kernel panic was observed on a platform when k_sem_give() was called
in npcx_kbd_ksi_isr(). From the panic information, it appears that
the semaphore was used before it was initialized. This commit prevents
the potential issue by enabling the interrupt only after
the input_kbd_matrix_common_init() function is called
(where the semaphore is initialized).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Configure the initial pin state of the UARTE peripheral to SLEEP, not
left uninitialised. This fixes the pin configuration not being set until
the interface is used if `zephyr,pm-device-runtime-auto` is enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
RP2350 provides a function to get OTP-backed chip ID. Prefer using this
on supported platforms for these reasons:
- a secure internal identifier, same as read by picotool
- works on flashless boards
- does not conflict with code running in XIP mode (e.g. when the other
core tries to access device ID)
- when used with USB HWID serial number will match one BootROM has
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Co-authored-by: Alexander Wachter <alexander@wachter.cloud>
Previously, the CMSDK APB dual timer driver hardcoded the counter
clock frequency to 24 MHz, which limits reuse across SoCs and
boards with different timer clock sources.
This patch replaces the hardcoded frequency with a value derived
from the device tree's `clocks` phandle, using the
`clock-frequency` property of the referenced clock controller node.
If the property is missing, it falls back to a default 24 MHz.
Signed-off-by: Lidor T <lidor@exibit-iot.com>
Allow for users to define the sampling period via the sampleper
register on a per instance basis through device-tree properties.
The previous value was hard coded. The same value is now the default
value.
Signed-off-by: Mark Geiger <MarkGeiger@posteo.de>
In lis2dux12_freq_to_odr_val, the loop through the array of possible ODR
frequencies can break sooner than expected if power-mode is
set to High Performance mode and the requested ODR is less than or
equal to 25Hz.
Moreover, move the "odr |= 0x10" statement used for HP mode in the
chip_api set_odr_raw() API, so that we enter the HP mode even when the
ODR is set from DT only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This change introduces GPIO_RX_PORT_IRQ_DECL() and GPIO_RX_PORT_IRQ_ELEM()
macros to conditionally generate GPIO port IRQ declarations and elements
only when the 'port_irq_names' property exists in the device tree node.
This improves code clarity and avoids generating unused code for ports
that do not have IRQ support for Renesas RX
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This driver supports multi-color LEDs built with several monochromatic
LEDs. ->set_color is the only LED driver API method implemented.
Instead of calling led_set_brightness() for each monochromatic LED,
led_set_color() can be called on the leds-group-multicolor device to
set all colors at once.
See the leds-group-multicolor DT binding for details.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
For all LED drivers, the underlying subsystem is automatically selected
in Kconfig if their compatible node is found in DT.
The only exception is the PWM LED driver which depends on PWM instead
of selecting it. The PWM Kconfig option must be explicitely selected in
order to have LED_PWM enabled.
This patch updates the Kconfig of the PWM LED driver to have the same
behavior as other LED drivers: PWM is now automatically selected if a
"pwm-leds" compatible node is found in DT.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add support to generate the random MAC if 'zephyr,random-mac-address'
is set,uses 'local-mac-address' from DT if available, or falls back
to a default Xilinx OUI-based MAC with zeroed bytes
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
Automatically hide the nRF7x interface from the connection manager if
the TX path is disabled (scan only mode). This prevents function calls
like `conn_mgr_all_if_up(true)` from bringing up the interface which
can never result in a connection.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Restructured counter and timer.
CTimer/Timer is now parent to pwm and counter.
Created PWM driver and tied to pwm and pwm-led
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
This moves the couple functions that are and will be all over
the various clock operations for all platforms.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Handle `SENSOR_CHAN_ALL` case of the sample_fetch callback of the
lis2dw12 driver. Without this, `sensor_sample_fetch()` does not work
correctly for this device, e.g. rendering the rtio and the sensor shell
unusable.
Signed-off-by: Ruben Völl <ruben.voell@sevenlab.de>
Rpu recovey debug stats are stored in hal_dev_ctx which is not
persistent in case of interface is brought down/up. Need to add
in nrf_wifi_ctx_zep and update before interface goes down.
Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
The MAX17055 peripheral allows measuring the current
value (which corresponds to the instantaneous value). Respond to
the `SENSOR_CHAN_CURRENT` command, and retrieve the data
from the `0x0a` device register.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
