Handle GAMC register with device memory-mapped input/output management.
As the MMIO is used, remove the MMU configurations for GMAC accordingly.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add a driver for the WIZnet W6300 stand-alone Ethernet controller
with SPI interface. The driver operates in MACRAW mode using Socket 0
to send and receive raw Ethernet frames via Zephyr's Ethernet L2 layer.
PHY link state is monitored via the W6300 interrupt pin combined with
a periodic polling thread. The SPI protocol uses a 4-byte command
frame (instruction + address high + address low + dummy) for both
read and write operations, as required by the W6300 hardware.
Signed-off-by: Manjae Cho <manjae.cho@samsung.com>
Fix the race between restoring interrupt enable register (ier)
states and runtime interrupt enabling that caused ec watchdog
timeouts on Google Ciri platform during stress testing. The
issue occurs if the adc interrupt enable bit is set right
before restoration, overwriting it with the outdated disabled
status and stucking adc thread.
To address this, this commit synchronizes `ier_setting[]` with
runtime enable/disable operations so
`ite_intc_restore_interrupts()` uses the latest ier state.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Wi-Fi on PSRAM-enabled builds was failing because the shared multi
heap overlapped relocated .ext_ram.data noinit content. Anchor the
heap on the linker-reserved window, size esp32c5 and esp32s3 ext
segments to the cache window and bump the Wi-Fi SPIRAM heap floor.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add ESP32_WIFI_TASK_STACK_SIZE to control the stack size used by the
Wi-Fi tasks spawned through the blobs. The adapter applies the
value as a floor: when the Wi-Fi library passes a larger stack,
at runtime, the larger value wins, so a higher Kconfig only
raises the minimum and never shrinks the request.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
dma_init() performs a soft-reset to put the DMA into a known state, but
this reset is not repeated on subsequent stop/start cycles. If the DMA
stopped with error bits set, the next configure picks up the dirty state.
Add a needs_dma_soft_reset flag that is set by dma_stop() and checked at
the top of dma_configure(). When set, dma_configure() issues a soft-reset
via the RX channel DMACR (which resets both TX and RX), polls until the
reset bit clears, then continues with normal configuration.
Fixes DMA re-use after network interface down/up cycles.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
adds a #if defined(CONFIG_CPU_CORTEX_M7) compilation gate for the
set_up_plls() function. This eliminates compiler errors on dual core
STM32H7 SoCs where the secondary core (Cortex-M4) enables pll since
according to the Zephyr docs, the clock configuration is only accessible
to the M7 core.
For example on the stm32h755xx soc the secondary Cortex-M4 core may choose
to enable the spi3 peripheral and have its kernel clock use pll2. Without
this fix, an implicit declaration of function errors related to the
following functions: get_vco_input_range and get_vco_output_range.
Signed-off-by: Jay Pacamarra <jay.pacamarra@sanctuary.ai>
Add basic `LOG_INF` messages notifying users of the updated charging
state when callbacks to users are run notifying them of the changes.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Relax the voltage clamping applied when configuring the maximum charge
voltage from software. Instead of treating the devicetree value as the
top limit, allow the full IC charge range to be selected.
Signed-off-by: Jordan Yates <jordan@embeint.com>
KSO16 and KSO17 may be used as GPIO function,
so the property can't be claimed "required: true".
Also, add the condition, if kso16/kso17 is used as kbs function,
then switch pin function to output temporarily before pin control
to kbs mode.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Some architectures require aligned accesses so the recv_cbs address must be
aligned. With this fix, Virtio will work on riscv32_virtual platform.
Signed-off-by: Jérémy Lefaure <jlefaure@antmicro.com>
On 32 bits platforms, the 32 bits shift leads to undefined behavior. This
fix makes the driver build without warning on 32 bits platforms.
Signed-off-by: Jérémy Lefaure <jlefaure@antmicro.com>
Some reset reason masks are now guarded by symbols.
Include them in WDT reset reason definition.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
The number of "fake" registers was too low for the
register numbers effectively written, causing invalid
memory access.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Add SPI driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Master and Slave operation modes
- Polling, Interrupt, and DMA transfer modes
- Transmit (TX) and Receive (RX) functionality
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
The cache driver API requires cache_data_flush_all(),
cache_data_invd_all() and cache_data_flush_and_invd_all() to be
defined whenever CONFIG_DCACHE is selected. Without these symbols,
any image that pulls in the generic cache API fails to link on
ESP32 SoCs with the cache driver enabled, for example:
tests/kernel/cache on esp32s2_devkitc
tests/kernel/cache on esp32s3_devkitc/procpu
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The GPIO_DDR register uses 1 for output mode and 0 for input mode.
The previous implementation incorrectly swapped these values, causing
gpio_pin_is_input() and gpio_pin_is_output() to return wrong results.
Also mask out unconnected pins using connect_pin to ensure
disconnected GPIOs are not reported as either input or output.
Fixes gpio_get_direction test failures on RTL87x2G and RTL8752H series.
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
When network is temporary lost, we might receive
PPP_DEAD event just before parsing "+CEREG: ..."
Therefore immediately redialing might lead to out-of-sync
states.
Delay the redial script by the PERIODIC_SCRIPT_TIMEOUT
as any other script failures do.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
In tcpci_tcpm_transmit_data() the gate that decides whether the packet
is a non-SOP* transmission (Hard Reset, Cable Reset, BIST) was checking
msg->header.message_type, the 5-bit PD header message type ID. That
field overlaps the SOP* range: any standard SOP message whose header
message_type is >= NUM_SOP_STAR_TYPES (e.g. PS_RDY = 6, PR_Swap = 10,
DR_Swap = 11, ...) was misclassified as non-SOP* and written to the
TRANSMIT register without retries, undermining PD negotiation
reliability against CC-line noise.
The TRANSMIT register's type field is enum pd_packet_type, which is
carried in msg->type. Use msg->type for both the gate and the
TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY() argument, matching the retry
path further down the function which already uses msg->type.
Signed-off-by: Way Young <wayyoung@gmail.com>
Replace the fixed 1-second transfer timeout with a value derived from
the actual number of SCL cycles required for the transfer, plus a
configurable margin (I3C_CADENCE_TRANSFER_TIMEOUT_MARGIN_US, default
10000 us).
Three helpers cover each transfer type:
- cdns_i3c_calc_timeout_i3c: SDR (broadcast header + 9 bits/byte) and
HDR-DDR (ENTHDR0 preamble + DDR word count at 8 SCL cycles/word,
including command header and CRC words)
- cdns_i3c_calc_timeout_i2c: 7-bit (9 bits) or 10-bit (18 bits)
address frame + 9 bits per data byte, using the I2C SCL frequency
- cdns_i3c_calc_timeout_ccc: broadcast addr + CCC command byte +
optional broadcast data + per-target address and data
Signed-off-by: Ryan McClelland <rymcclel@gmail.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The battery alias is verified to be a sensor device before use.
Also the commit fixes incorrect use of `argv[1]` instead of `dev->name`.
Signed-off-by: Maksim Salau <maksim.salau@gmail.com>
Ready registers are defined for the nrf54h series but not necesssary for
other soc families.
Limit the Ready register check only to this family of socs.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
Remove the 'andestech,qspi-nor-xip' compatible string and unify both
flash_andes_qspi.c and flash_andes_qspi_xip.c flash drivers use
'andestech,qspi-nor' compatible string.
The driver selection is now handled via Kconfig logic.
CONFIG_FLASH_ANDES_QSPI_XIP is strickly depends on XIP is enabled and
the 'zephyr,flash' chosen node is compatible with 'andestech,qspi-nor'.
Since these two driver variants cannot coexist, the application is
responsible for enabling the appropriate driver Kconfig.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add the pwm-buzzer compatible and the corresponding driver in
drivers/buzzer/buzzer_pwm.c. The PWM channel period sets the audio
frequency and the duty cycle sets the perceived volume (50% is
loudest for piezos; the driver maps the linear 0..100% volume
percentage to a triangular 0..50% duty curve so 100% volume gives
maximum loudness).
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add the gpio-buzzer compatible and the corresponding driver in
drivers/buzzer/buzzer_gpio.c. Active buzzers contain their own
oscillator and produce a fixed tone whenever they are powered.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Introduce a consumer-facing buzzer API for boards that have a buzzer
wired through a PWM channel or a single GPIO. Apps drive buzzers via
buzzer_tone(), buzzer_beep() (plays the device's natural frequency
encoded in DT), buzzer_set_volume(), and buzzer_stop().
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
add spinlock for thread safety in socket operations. I noticed that
the native_sim would otherwise crash
under high network load.
Signed-off-by: Fin Maaß <info@finmaass.de>
Validate the SPI bus frequency supplied via spi_config before it is
used to compute the baud-rate clock divider to prevent the following
faults:
- A zero frequency causes an integer division-by-zero when computing
the clock divider, resulting in a hardware fault or an undefined
value being written to the SPI_BAUDR register.
- A frequency exceeding half of the input core clock produces a
divider value less than the minimum of 2 required by the
DesignWare SSI databook (section 6.2.2), overclocking the
peripheral and causing undefined bus behaviour.
Return -EINVAL for a zero frequency and -EINVAL for a frequency
greater than clk_hz / 2, surfacing the error to the caller rather
than silently misconfiguring the hardware.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
When configuring the nRF SPIM, the frequency needs to be limited by
the max frequency of the SPIM, which is specified in the devicetree.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
These functions are from phy_oa_tc14_plca.c, which
is only a helper for phys to implement the set_plca_cfg,
get_plca_cfg and get_plca_sts functions of the ethernet_phy
api, therefore they should be internal.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Fix SPI clock frequency being modified during DMA transfers.
Fix regression in DMA configuration structure update.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Fix incorrect behavior for non-8-bit SPI word sizes.
Fix the handling when both TX and RX buffers are NULL.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Enable IOCON clocks from the devicetree clocks property during
pinctrl initialization.
Keep the existing LPC path intact and only use the clock control
flow when a clock is described in devicetree.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx IOCON clock IDs to the MCUX SYSCON clock bindings and
handle them in the shared clock control driver.
This provides the common gate support needed for RT7xx IOCON
instances to be managed through the clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Use the optional clocks property to request the GPIO port clock
during driver initialization.
This lets RT7xx GPIO instances rely on the common clock control
path instead of board-specific clock enabling.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx GPIO clock IDs to the MCUX SYSCON clock bindings and
handle them in the shared clock control driver.
This provides the common GPIO gate support needed for RT7xx
GPIO instances to be managed through the clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
