The "st,stm32-usbphyc" compatible was used for three different hardware
programming models, which goes against the Devicetree Specification.
This was masked though special checks in CMake which is hacky at best.
Split the compatible in three compatibles (2 new + 1 reused):
- "st,stm32-usbphyc" where the PHY clock frequency is configured
through USBPHYC registers in the RCC MMIO interface (STM32H7R/S)
- "st,stm32f7-usbphyc" where the PHY clock frequency is configured
through a distinct MMIO interface with five options available:
12, 12.5, 16, 24 and 25 MHz
- "st,stm32n6-usbphyc" where the PHY clock frequency is configured
through a distinct MMIO interface with three options available:
19.2, 20 and 24 MHz
Update SoC DTSI and drivers (Kconfig, CMakeLists and source) to work
with the new organization brought by these bindings.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The month register counts 1-12 but the driver stored tm_mon (0-11)
raw and read it back unchanged, corrupting the chip's own calendar
rollover. Apply the one-month offset in both directions, as the
pcf85063a and pcf8523 drivers do.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a disk driver that exposes any device implementing the memc
read/write API as a block device. This enables using external
memory as storage for FAT filesystems or general block I/O without
requiring memory-mapped access.
The driver uses the zephyr,memc-ram-disk compatible and reads the
backing memc device phandle, disk name, and sector configuration
from devicetree. Read and write operations are translated directly
to memc_read() and memc_write() calls.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Add ADC driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- 12-bit resolution
- Divide mode and Bypass mode
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Support Zephyr RTOS on Cortex A720 for R-Car X5H.
For more information and documentation, please visit the product page:
https://www.renesas.com/secure/gen5-r-car-x5h
Signed-off-by: Nam Nguyen <nam.nguyen.xn@renesas.com>
The property was both `boolean` and `required: true` so it was always
present on nodes with the compatible (i.e., STM32WL5 "SUBGHZSPI" node).
The SPI driver serialized this property into field `use_subghzspi_nss`,
but it really acted as `is_subghzspi` instead... which does not require
a specific property: the SUBGHZSPI node can be identified by its special
compatible `st,stm32-spi-subghz` alone!
Drop the `use-subghz-nss` property from the binding since it is useless,
and update the STM32WL SoC DTSI accordingly. In the STM32 SPI driver,
rename the `use_subghzspi_nss` field to `is_subghzspi` and initialize it
to true iff an SPI node has the special compatible. While at it, inline
function spi_stm32_is_subghzspi() into its only caller and add a comment
explaining why the check is needed to slightly simplify the driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The individual bands within a GNSS constellation do not count as a new
system. This commit was overloading the meaning of `gnss_system`, as
demonstrated by:
* The NMEA handling has no way to result in these new defines
* The new defines have no meaning in several in-tree contexts (e.g
in `struct gnss_satellite`)
* The commit changed the meaning of `GNSS_SYSTEM_GPS` for example to
mean the whole GPS constellation in some contexts, and the L1 band of
the GPS constellation in others.
The real problem is the limitation of the `set_enabled_systems` API,
which is insufficiently flexible to communicate individual bands within
a GNSS system.
The correct solution is to add a new `gnss_signals` define, implement
a new `set/get_enabled_signals` API and deprecate
`set/get_enabled_systems`.
This reverts commit f8800c8ab3.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Create a new quectel,21-g.yaml device tree binding and modify the
current EG25-G modem cellular code to also support EG21-G, removing
specific references to EG25-G from the implementation and
making sure the proper definitions exist for both EG21 and EG25.
Also make mdm-reset-gpios optional for EG25-G.
Signed-off-by: Guilherme Costa <guilhermecosta@stratioautomotive.com>
The driver wrote tm_mon (0-11) and tm_wday (0-6) directly into the
DS1307 month and day registers, which count 1-12 and 1-7, so the
chip's own calendar logic ran with the wrong month and the stored
values were out of the documented range. Convert by one in both
directions, as the ds1302 driver does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The minute and hour don't-care branches both wrote RTC_ALARM_SEC,
clobbering the seconds alarm programmed just before and leaving stale
minute/hour match values active. Target the minute and hour alarm
registers.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The AD4170 driver already supports the "-4" members of this Sigma-Delta
ADC family (AD4170-4, AD4190-4, AD4195-4) from a single shared driver,
differentiated by compatible string and PRODUCT_ID.
Add support for the "-8" variants. Per their datasheets, the AD4195-8
and AD4190-8 both report PRODUCT_ID 0x49 and expose analog inputs
AIN8..AIN15 in addition to AIN0..AIN7; the register map, 24-bit
resolution, 16 channels, 8 setups and filters are identical to the rest
of the family.
Wire up two new compatibles (adi,ad4195-8-adc, adi,ad4190-8-adc),
extend the ad4170_input enum and the dt-bindings header with the extra
analog inputs, and add the parts to the build_all coverage.
Signed-off-by: Robert Budai <robert.budai@analog.com>
- Set burst_len to 1 when zero, since CSZ=0 (zero bytes per trigger)
causes WRE/RDE interrupt errors
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
- Allow zero-length messages for i2c scan support
- Fix MB interrupt handling for read NACK detection
- Fix read-to-RESTART bus state handling
- Fall back to interrupt mode for single-byte reads when DMA enabled
- Use LISTIFY for interrupt configuration to support all interrupt lines
- Refactor variable names and cleanup
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
The core code of the eeprom target library is a simple implementation of
byte oriented read and write against a memory range. The same protocol
is used by a lot of devices that use it to address a set of register and
is useful for other target drivers as well.
Refactor it out to a library so it can be reused, structs, code, api
implementation, dt binding and helpers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Replace the driver specific I2C_DW_RW_TIMEOUT_MS with the generic macro
that allows override via Kconfig and dt properties.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Replace various depends on I2C_DW with a single if I2C_DW, this stops
options under here from being exposed in Kconfig for unrelated platforms
and cleans up the config a bit.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The driver stored the devicetree register address in cfg->base and used
it as a virtual address without ever mapping it. That only works where
the boot page tables already cover the peripheral. On the ZynqMP and
Versal NET APUs they do not, so the SPI_CONF write at the top of
spi_cdns_init() faults.
Convert to the DEVICE_MMIO helpers, which map the region in init() and
drop the assumption that the virtual address equals the physical one.
Also fixes a truncation: base was uint32_t, while DT_INST_REG_ADDR() is
pointer-width.
No functional change on non-MMU targets, where DEVICE_MMIO_IS_IN_RAM is
unset: building drivers.spi.build.spi_cdns for qemu_cortex_m3 before and
after gives byte-for-byte identical disassembly.
Signed-off-by: Iustin Stolniceanu <stolniceanuiustin@gmail.com>
The flow control configuration and associated delay (`AT+IFC`) only need
to be sent if the configuration is not already correct. Since the
setting is saved in flash, the vast majority of boots can be made 100 ms
faster by querying the current setting and skipping the configuration
if it already matches.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Use %zu instead of %d in LOG_DBG for size_t arguments (fill_len,
offset) to fix -Wformat build warnings.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Not all i.MX RT11xx SoCs implement a WDOG4 instance; on those parts
the SRC_SRSR register has no WDOG4_RST_B_M7 flag and the driver fails
to build. Take the flag into account only when the SoC header
defines it.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The pue_mux register layout check indexed the pinmux array with the
raw pin number, while all other accesses use the gap-compensated
cfg_idx. On a port with gpio-reserved-ranges and a compacted pinmux
map this reads the wrong entry, or past the end of the array.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
With PULLEN set, the PORT_OUT bit selects the pull direction. The
pull-down path never cleared a previously set OUT bit, so a requested
pull-down could configure a pull-up instead. Clear the latch in the
pull-down case, as the gpio_mchp_port_g1 driver does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
When CONFIG_SOC_SERIES_NRF71_TFM_RAM_CTRL_SERVICE is set, route
z_nrf_retained_mem_retention_apply() to the secure RAM-control service
(tfm_platform_ram_ctrl_retention_set) instead of nrfx_ram_ctrl; the secure
build keeps the direct nrfx path. Apply regions best-effort and return
-EIO if the secure service rejects one.
Signed-off-by: Erdem Simsek <erdem.simsek@nordicsemi.no>
- spi_context_lock: move the ISR assert from function entry to guard the
actual blocking call (inside !already_locked), so the legitimate
SPI_LOCK_ON fast path is not falsely caught.
- spi_context.h comment: clarify that calling from ISR is legal when the
lock is already held via SPI_LOCK_ON.
- spi.h: point to the RTIO submit path as the correct way to chain
asynchronous transactions, per @teburd and @npitre.
Suggested-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Tibor Kiss <kiss.tibor@gmail.com>
Added help text for the I3C_CONTROLLER and I3C_TARGET options. While these
are promptless, they are worth explaining and should show up in the Kconfig
reference doc page so that cross-references to them can be resolved.
Assisted-by: Claude:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The TX path was broken if we did not prefill the
TX queue with more than one block. This is because
the TX DMA was queueing a NULL block causing DMA
failures after transfer of the first block.
Added logic to wait for atleast 2 blocks before
starting a transmit.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The ppb conversion in rtc_sam0_get_calibration() multiplies the
FREQCORR correction value by 1000000000 in a 32-bit expression.
Any correction value of 3 or more overflows int32_t (3e9 >
INT32_MAX), so the reported calibration is garbage for most of
the register range (VALUE goes up to 127).
Do the multiplication in 64 bits, matching the equivalent
conversion in the Microchip G1 RTC driver. The result fits
comfortably in int32_t: with the smallest in-tree cal-constant
(983040), the maximum magnitude is 127 * 1e9 / 983040, about
129186 ppb.
Built tests/drivers/rtc/rtc_api for samc21n_xpro with
CONFIG_RTC_CALIBRATION=y.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Restore the previous interrupt state when DMM RX buffer preparation
fails. Returning with the IRQ lock held could leave interrupts disabled
after uart_rx_buf_rsp() reports the error.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Model DMAEND and FRAMETIMEOUT_DMAEND support as a devicetree
capability. Use DMAEND for finite asynchronous RX frame timeouts on
capable UARTE instances and retain STOPRX on unsupported hardware.
Disable TIMER-based byte counting when DMAEND is available. Preserve
buffer accounting when uart_rx_disable() races with an ENDRX rollover,
reject buffer responses during teardown, and restore the interrupt
state after DMM preparation failures.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
The default case of the angle_magnitude_axis switch programs
TMAG5273_ANGLE_EN_POS. This value sets bits outside the ANGLE_EN
field and overlaps with the adjacent range configuration bits in
SENSOR_CONFIG_2.
Use TMAG5273_ANGLE_EN_NONE instead to be corrrectly configured.
Signed-off-by: Stefan Prisacariu <stefan.prisacariu@prevas.dk>
The alarm getter open-coded find_lsb_set on the weekday bitmask
without the -1 index correction, returning the weekday off by one.
Use the rv8803_mask2weekday helper like get_time.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The Zephyr SD subsystem expects a 136-bit R2 response in
sdhc_command::response[4] with response[3] holding the most
significant 32 bits and response[0] holding the least significant
32 bits.
intel_emmc_host stored the 32-bit fragments in reverse order, so
resp3 (bits 127:96) was placed in response[0] and resp0 (bits 31:0)
in response[3]. Reverse the assignments.
sam_hsmci read the HSMCI_RSPR FIFO into response[3..0] in the order
the FIFO returns data, but that puts the most significant word in
response[0]. Read the FIFO into response[0..3] instead, matching the
Zephyr layout.
Fixes#112868
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Add support for selecting HSE/1024 as the STM32WB RF wakeup (low speed)
clock source, as an alternative to LSE, for boards without a 32.768 kHz
LSE crystal.
The source is selected through the existing clock-cell mechanism on the
ble_rf devicetree node (e.g. <&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(1024))
RFWKP_SEL(3)>), so no new devicetree property and no clock-control driver
change are needed. The ipm_stm32wb driver reads the configured source from
that clock cell and, for HSE/1024, sets the HSE/1024 SHCI low speed clock
bit on top of the CFG_BLE_LS_SOURCE value from app_conf.h. The Cube
app_conf.h is not modified, so no companion hal_stm32 change is required.
Note: switching the RF wakeup clock source is a CPU2 clock change and
requires a power-on reset to take effect.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Port haptics API changes to the CS40L26/27 driver, notably
*_calibrate(), *_monitor_get(), *_monitor_set(),
*_select_source(), and *_set_level(). Removes CS40L5x-specific
API functions from the public header that have been replaced
by the haptics API.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
The dual-edge minimum interval check was immediately overridden by
an unconditional check requiring twice the step width, which only
applies to single-edge stepping, so valid dual-edge intervals were
rejected. Restrict the stricter check to single-edge mode.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Update the driver of SCLK (Slow Clock Controller) for compatible with
more MPUs such as sam9x and sama5d2 series.
Signed-off-by: Tony Han <tony.han@microchip.com>
A dedicated config item for SCKC is added so that the drivers for PMC
and SCKC can be built seperately.
Signed-off-by: Tony Han <tony.han@microchip.com>
