drivers: spi: silabs: eusart: Asynchronous support
Add support for asynchronous transfer in silabs eusart spi driver. Signed-off-by: Francois Laplante <frlaplan@silabs.com>
This commit is contained in:
Francois Laplante
Carles Cufí
parent
52ceb6ab86
commit
8dad73bf47
3 changed files with 482 additions and 68 deletions
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@ -11,6 +11,7 @@ supported:
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- bluetooth
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- gpio
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- uart
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- spi
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- dma
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- watchdog
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- comparator
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@ -1,6 +1,7 @@
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# Silabs EUSART SPI configuration option
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# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
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# Copyright (c) 2025 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SPI_SILABS_EUSART
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@ -12,3 +13,16 @@ config SPI_SILABS_EUSART
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select PINCTRL if SOC_FAMILY_SILABS_S2
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help
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Enable the EUSART SPI driver
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config SPI_SILABS_EUSART_DMA
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bool "Silabs EUSART SPI controller driver DMA enabled transfer"
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depends on SPI_SILABS_EUSART
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select DMA
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default y if SPI_ASYNC
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config SPI_SILABS_EUSART_DMA_MAX_BLOCKS
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int "Silabs EUSART SPI controller driver maximum DMA transfer block per channel for a transaction."
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depends on SPI_SILABS_EUSART_DMA
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default 8
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help
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One block is needed for every chunk found in the SPI transaction and every 2048 bytes
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,28 +8,48 @@
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#define DT_DRV_COMPAT silabs_eusart_spi
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#include <stdbool.h>
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#include <stddef.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/device.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/clock_control_silabs.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/dma/dma_silabs_ldma.h>
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#include <zephyr/drivers/dma.h>
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#include <em_cmu.h>
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#include <em_eusart.h>
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LOG_MODULE_REGISTER(spi_silabs_eusart, CONFIG_SPI_LOG_LEVEL);
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/* Required by spi_context.h */
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#include "spi_context.h"
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#define SPI_WORD_SIZE 8
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#if defined(CONFIG_SPI_ASYNC) && !defined(CONFIG_SPI_SILABS_EUSART_DMA)
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#warning "Silabs eusart SPI driver ASYNC without DMA is not supported"
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#endif
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/* Structure Declarations */
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#define SPI_WORD_SIZE 8
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#ifdef CONFIG_SPI_SILABS_EUSART_DMA
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#define SPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE (0x800U)
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struct dma_channel {
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const struct device *dma_dev;
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uint8_t dma_slot;
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int chan_nb;
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struct dma_block_config dma_descriptors[CONFIG_SPI_SILABS_EUSART_DMA_MAX_BLOCKS];
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};
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#endif
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struct spi_silabs_eusart_data {
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struct spi_context ctx;
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#ifdef CONFIG_SPI_SILABS_EUSART_DMA
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struct dma_channel dma_chan_rx;
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struct dma_channel dma_chan_tx;
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#endif
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};
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struct spi_silabs_eusart_config {
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@ -37,14 +58,30 @@ struct spi_silabs_eusart_config {
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const struct silabs_clock_control_cmu_config clock_cfg;
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uint32_t clock_frequency;
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const struct pinctrl_dev_config *pcfg;
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uint8_t mosi_overrun;
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};
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/* Helper Functions */
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static int spi_silabs_eusart_configure(const struct device *dev, const struct spi_config *config,
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uint16_t *control)
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#ifdef CONFIG_SPI_SILABS_EUSART_DMA
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static volatile uint8_t empty_buffer;
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#endif
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static bool spi_silabs_eusart_is_dma_enabled_instance(const struct device *dev)
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{
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#ifdef CONFIG_SPI_SILABS_EUSART_DMA
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struct spi_silabs_eusart_data *data = dev->data;
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__ASSERT_NO_MSG(!!data->dma_chan_tx.dma_dev == !!data->dma_chan_rx.dma_dev);
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return data->dma_chan_rx.dma_dev != NULL;
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#else
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return false;
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#endif
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}
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static int spi_silabs_eusart_configure(const struct device *dev, const struct spi_config *config)
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{
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struct spi_silabs_eusart_data *data = dev->data;
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const struct spi_silabs_eusart_config *eusart_config = dev->config;
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const struct spi_silabs_eusart_config *eusart_cfg = dev->config;
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uint32_t spi_frequency;
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EUSART_SpiAdvancedInit_TypeDef eusartAdvancedSpiInit = EUSART_SPI_ADVANCED_INIT_DEFAULT;
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@ -52,8 +89,8 @@ static int spi_silabs_eusart_configure(const struct device *dev, const struct sp
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int err;
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err = clock_control_get_rate(eusart_config->clock_dev,
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(clock_control_subsys_t)&eusart_config->clock_cfg,
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err = clock_control_get_rate(eusart_cfg->clock_dev,
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(clock_control_subsys_t)&eusart_cfg->clock_cfg,
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&spi_frequency);
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if (err) {
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return err;
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@ -65,7 +102,7 @@ static int spi_silabs_eusart_configure(const struct device *dev, const struct sp
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/* Already configured. No need to do it again, but must re-enable in case
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* TXEN/RXEN were cleared due to deep sleep.
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*/
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EUSART_Enable(eusart_config->base, eusartEnable);
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EUSART_Enable(eusart_cfg->base, eusartEnable);
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return 0;
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}
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@ -95,11 +132,11 @@ static int spi_silabs_eusart_configure(const struct device *dev, const struct sp
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* user has configured the controller to, and the max frequency for the
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* transaction.
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*/
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if (eusart_config->clock_frequency > spi_frequency) {
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if (eusart_cfg->clock_frequency > spi_frequency) {
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LOG_ERR("SPI clock-frequency too high");
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return -EINVAL;
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}
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spi_frequency = MIN(eusart_config->clock_frequency, spi_frequency);
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spi_frequency = MIN(eusart_cfg->clock_frequency, spi_frequency);
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if (config->frequency) {
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spi_frequency = MIN(config->frequency, spi_frequency);
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}
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@ -137,21 +174,275 @@ static int spi_silabs_eusart_configure(const struct device *dev, const struct sp
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eusartInit.databits = eusartDataBits8;
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eusartInit.advancedSettings = &eusartAdvancedSpiInit;
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#ifdef CONFIG_SPI_SILABS_EUSART_DMA
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if (spi_silabs_eusart_is_dma_enabled_instance(dev)) {
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if (!device_is_ready(data->dma_chan_tx.dma_dev)) {
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return -ENODEV;
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}
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eusartAdvancedSpiInit.TxFifoWatermark = eusartTxFiFoWatermark1Frame;
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eusartAdvancedSpiInit.RxFifoWatermark = eusartRxFiFoWatermark1Frame;
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if (data->dma_chan_rx.chan_nb < 0) {
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data->dma_chan_rx.chan_nb =
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dma_request_channel(data->dma_chan_rx.dma_dev, NULL);
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}
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if (data->dma_chan_rx.chan_nb < 0) {
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LOG_ERR("DMA channel request failed");
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return -EAGAIN;
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}
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if (data->dma_chan_tx.chan_nb < 0) {
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data->dma_chan_tx.chan_nb =
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dma_request_channel(data->dma_chan_tx.dma_dev, NULL);
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}
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if (data->dma_chan_tx.chan_nb < 0) {
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dma_release_channel(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
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data->dma_chan_rx.chan_nb = -1;
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LOG_ERR("DMA channel request failed");
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return -EAGAIN;
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}
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}
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#endif
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/* Enable EUSART clock */
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err = clock_control_on(eusart_config->clock_dev,
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(clock_control_subsys_t)&eusart_config->clock_cfg);
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if (err < 0) {
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return err;
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err = clock_control_on(eusart_cfg->clock_dev,
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(clock_control_subsys_t)&eusart_cfg->clock_cfg);
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if (err < 0 && err != -EALREADY) {
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goto exit;
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}
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/* Initialize the EUSART */
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EUSART_SpiInit(eusart_config->base, &eusartInit);
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EUSART_SpiInit(eusart_cfg->base, &eusartInit);
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data->ctx.config = config;
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return 0;
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exit:
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#ifdef CONFIG_SPI_SILABS_EUSART_DMA
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if (spi_silabs_eusart_is_dma_enabled_instance(dev)) {
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dma_release_channel(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
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dma_release_channel(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
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data->dma_chan_rx.chan_nb = -1;
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data->dma_chan_tx.chan_nb = -1;
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}
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#endif
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return err;
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}
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#ifdef CONFIG_SPI_SILABS_EUSART_DMA
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static void spi_silabs_dma_rx_callback(const struct device *dev, void *user_data, uint32_t channel,
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int status)
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{
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const struct device *spi_dev = (const struct device *)user_data;
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struct spi_silabs_eusart_data *data = spi_dev->data;
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struct spi_context *instance_ctx = &data->ctx;
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ARG_UNUSED(dev);
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if (status >= 0 && status != DMA_STATUS_COMPLETE) {
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return;
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}
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if (status < 0) {
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dma_stop(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
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dma_stop(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
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}
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spi_context_cs_control(instance_ctx, false);
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spi_context_complete(instance_ctx, spi_dev, status);
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}
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static void spi_silabs_eusart_clear_txrx_fifos(EUSART_TypeDef *eusart)
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{
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sys_write32(EUSART_CMD_CLEARTX, (mem_addr_t)&eusart->CMD_SET);
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while (sys_read32((mem_addr_t)&eusart->STATUS) & EUSART_STATUS_RXFL) {
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(void)sys_read32((mem_addr_t)&eusart->RXDATA);
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}
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while (sys_read32((mem_addr_t)&eusart->STATUS) & EUSART_STATUS_CLEARTXBUSY) {
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}
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}
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static size_t spi_silabs_longest_transfer_size(struct spi_context *instance_ctx)
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{
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uint32_t tx_transfer_size = spi_context_total_tx_len(instance_ctx);
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uint32_t rx_transfer_size = spi_context_total_rx_len(instance_ctx);
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return MAX(tx_transfer_size, rx_transfer_size);
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}
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static int spi_silabs_dma_config(const struct device *dev,
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struct dma_channel *channel,
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uint32_t block_count, bool is_tx)
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{
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struct dma_config cfg = {
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.channel_direction = is_tx ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY,
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.complete_callback_en = 0,
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.source_data_size = 1,
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.dest_data_size = 1,
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.source_burst_length = 1,
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.dest_burst_length = 1,
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.block_count = block_count,
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.head_block = channel->dma_descriptors,
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.dma_slot = channel->dma_slot,
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.dma_callback = !is_tx ? &spi_silabs_dma_rx_callback : NULL,
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.user_data = (void *)dev,
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};
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return dma_config(channel->dma_dev, channel->chan_nb, &cfg);
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}
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static uint32_t spi_eusart_fill_desc(const struct spi_silabs_eusart_config *cfg,
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struct dma_block_config *new_blk_cfg, uint8_t *buffer,
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size_t requested_transaction_size, bool is_tx)
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{
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/* Set-up source and destination address with increment behavior */
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if (is_tx) {
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new_blk_cfg->dest_address = (uint32_t)&cfg->base->TXDATA;
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new_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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if (buffer) {
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new_blk_cfg->source_address = (uint32_t)buffer;
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new_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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/* Null buffer pointer means sending dummy byte */
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new_blk_cfg->source_address = (uint32_t)&(cfg->mosi_overrun);
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new_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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} else {
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new_blk_cfg->source_address = (uint32_t)&cfg->base->RXDATA;
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new_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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if (buffer) {
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new_blk_cfg->dest_address = (uint32_t)buffer;
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new_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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/* Null buffer pointer means rx to null byte */
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new_blk_cfg->dest_address = (uint32_t)&empty_buffer;
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new_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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}
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/* Setup max transfer according to requested transaction size.
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* Will top if bigger than the maximum transfer size.
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*/
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new_blk_cfg->block_size = MIN(requested_transaction_size,
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SPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE);
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return new_blk_cfg->block_size;
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}
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struct dma_block_config *spi_eusart_fill_data_desc(const struct spi_silabs_eusart_config *cfg,
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struct dma_block_config *desc,
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const struct spi_buf buffers[],
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int buffer_count,
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size_t transaction_len,
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bool is_tx)
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{
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__ASSERT(transaction_len > 0, "Not supported");
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size_t offset = 0;
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int i = 0;
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uint8_t *buffer = NULL;
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while (i != buffer_count) {
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if (!buffers[i].len) {
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i++;
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continue;
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}
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if (!desc) {
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return NULL;
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}
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buffer = buffers[i].buf ? (uint8_t *)buffers[i].buf + offset : NULL;
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offset += spi_eusart_fill_desc(cfg, desc,
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buffer,
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buffers[i].len - offset,
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is_tx);
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if (offset == buffers[i].len) {
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transaction_len -= offset;
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offset = 0;
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i++;
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}
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if (transaction_len) {
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desc = desc->next_block;
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}
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}
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while (transaction_len) {
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if (!desc) {
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return NULL;
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}
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transaction_len -= spi_eusart_fill_desc(cfg, desc, NULL, transaction_len, is_tx);
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if (transaction_len) {
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desc = desc->next_block;
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}
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}
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desc->next_block = NULL;
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return desc;
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}
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static void spi_eusart_reset_desc(struct dma_channel *channel)
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{
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int i;
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memset(channel->dma_descriptors, 0, sizeof(channel->dma_descriptors));
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for (i = 0; i < ARRAY_SIZE(channel->dma_descriptors) - 1; i++) {
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channel->dma_descriptors[i].next_block = &channel->dma_descriptors[i + 1];
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}
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}
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static int spi_eusart_prepare_dma_channel(const struct device *spi_dev,
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const struct spi_buf *buffer,
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size_t buffer_count,
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struct dma_channel *channel,
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size_t padded_transaction_size,
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bool is_tx)
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{
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const struct spi_silabs_eusart_config *cfg = spi_dev->config;
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struct dma_block_config *desc;
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int ret = 0;
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spi_eusart_reset_desc(channel);
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desc = spi_eusart_fill_data_desc(cfg, channel->dma_descriptors,
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buffer, buffer_count, padded_transaction_size, is_tx);
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if (!desc) {
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return -ENOMEM;
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}
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ret = spi_silabs_dma_config(spi_dev, channel,
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ARRAY_INDEX(channel->dma_descriptors, desc),
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is_tx);
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return ret;
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}
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static int spi_eusart_prepare_dma_transaction(const struct device *dev,
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size_t padded_transaction_size)
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{
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int ret;
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struct spi_silabs_eusart_data *data = dev->data;
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if (padded_transaction_size == 0) {
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/* Nothing to do */
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return 0;
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}
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ret = spi_eusart_prepare_dma_channel(dev, data->ctx.current_tx, data->ctx.tx_count,
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&data->dma_chan_tx, padded_transaction_size,
|
||||
true);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_eusart_prepare_dma_channel(dev, data->ctx.current_rx, data->ctx.rx_count,
|
||||
&data->dma_chan_rx, padded_transaction_size, false);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void spi_silabs_eusart_send(EUSART_TypeDef *eusart, uint8_t frame)
|
||||
{
|
||||
/* Write frame to register */
|
||||
|
|
@ -199,25 +490,122 @@ static int spi_silabs_eusart_shift_frames(EUSART_TypeDef *eusart,
|
|||
if (spi_context_rx_buf_on(&data->ctx)) {
|
||||
UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
|
||||
}
|
||||
|
||||
spi_context_update_rx(&data->ctx, 1, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spi_silabs_eusart_xfer(const struct device *dev, const struct spi_config *config)
|
||||
static int spi_silabs_eusart_xfer_dma(const struct device *dev, const struct spi_config *config)
|
||||
{
|
||||
int ret;
|
||||
#ifdef CONFIG_SPI_SILABS_EUSART_DMA
|
||||
const struct spi_silabs_eusart_config *eusart_config = dev->config;
|
||||
struct spi_silabs_eusart_data *data = dev->data;
|
||||
struct spi_context *ctx = &data->ctx;
|
||||
const struct spi_silabs_eusart_config *eusart_config = dev->config;
|
||||
int ret = 0;
|
||||
|
||||
size_t padded_transaction_size = spi_silabs_longest_transfer_size(ctx);
|
||||
|
||||
if (padded_transaction_size == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spi_silabs_eusart_clear_txrx_fifos(eusart_config->base);
|
||||
|
||||
ret = spi_eusart_prepare_dma_transaction(dev, padded_transaction_size);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
spi_context_cs_control(ctx, true);
|
||||
|
||||
do {
|
||||
/* RX channel needs to be ready before TX channel actually starts */
|
||||
ret = dma_start(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
|
||||
if (ret) {
|
||||
goto force_transaction_close;
|
||||
}
|
||||
|
||||
ret = dma_start(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
|
||||
if (ret) {
|
||||
|
||||
goto force_transaction_close;
|
||||
}
|
||||
|
||||
ret = spi_context_wait_for_completion(&data->ctx);
|
||||
if (ret < 0) {
|
||||
goto force_transaction_close;
|
||||
}
|
||||
|
||||
/* Successful transaction. DMA transfer done interrupt ended the transaction. */
|
||||
return 0;
|
||||
force_transaction_close:
|
||||
dma_stop(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
|
||||
dma_stop(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
|
||||
spi_context_cs_control(ctx, false);
|
||||
return ret;
|
||||
#else
|
||||
return -ENOTSUP;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int spi_silabs_eusart_xfer_polling(const struct device *dev, const struct spi_config *config)
|
||||
{
|
||||
const struct spi_silabs_eusart_config *eusart_config = dev->config;
|
||||
struct spi_silabs_eusart_data *data = dev->data;
|
||||
struct spi_context *ctx = &data->ctx;
|
||||
int ret;
|
||||
|
||||
spi_context_cs_control(ctx, true);
|
||||
|
||||
ret = 0;
|
||||
while (!ret && spi_silabs_eusart_transfer_ongoing(data)) {
|
||||
ret = spi_silabs_eusart_shift_frames(eusart_config->base, data);
|
||||
} while (!ret && spi_silabs_eusart_transfer_ongoing(data));
|
||||
}
|
||||
|
||||
spi_context_cs_control(ctx, false);
|
||||
spi_context_complete(ctx, dev, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spi_silabs_eusart_transceive(const struct device *dev,
|
||||
const struct spi_config *config,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs,
|
||||
bool asynchronous,
|
||||
spi_callback_t cb,
|
||||
void *userdata)
|
||||
{
|
||||
struct spi_silabs_eusart_data *data = dev->data;
|
||||
struct spi_context *ctx = &data->ctx;
|
||||
int ret;
|
||||
|
||||
spi_context_lock(ctx, asynchronous, cb, userdata, config);
|
||||
|
||||
ret = spi_silabs_eusart_configure(dev, config);
|
||||
if (ret) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
|
||||
|
||||
if (spi_silabs_eusart_is_dma_enabled_instance(dev)) {
|
||||
/* DMA transfer handle a/synchronous transfers */
|
||||
ret = spi_silabs_eusart_xfer_dma(dev, config);
|
||||
} else if (!asynchronous) {
|
||||
ret = spi_silabs_eusart_xfer_polling(dev, config);
|
||||
} else {
|
||||
/* Asynchronous transfers without DMA is not implemented,
|
||||
* please configure the device tree
|
||||
* instance with the proper DMA configuration.
|
||||
*/
|
||||
ret = -ENOTSUP;
|
||||
}
|
||||
|
||||
out:
|
||||
spi_context_release(ctx, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* API Functions */
|
||||
|
|
@ -241,40 +629,31 @@ static int spi_silabs_eusart_init(const struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int spi_silabs_eusart_transceive(const struct device *dev, const struct spi_config *config,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs)
|
||||
static int spi_silabs_eusart_transceive_sync(const struct device *dev,
|
||||
const struct spi_config *config,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs)
|
||||
{
|
||||
struct spi_silabs_eusart_data *data = dev->data;
|
||||
uint16_t control = 0;
|
||||
int ret;
|
||||
|
||||
spi_context_lock(&data->ctx, false, NULL, NULL, config);
|
||||
|
||||
ret = spi_silabs_eusart_configure(dev, config, &control);
|
||||
if (ret < 0) {
|
||||
spi_context_release(&data->ctx, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
|
||||
spi_silabs_eusart_xfer(dev, config);
|
||||
|
||||
spi_context_release(&data->ctx, ret);
|
||||
|
||||
return 0;
|
||||
return spi_silabs_eusart_transceive(dev,
|
||||
config,
|
||||
tx_bufs,
|
||||
rx_bufs,
|
||||
false,
|
||||
NULL,
|
||||
NULL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
static int spi_silabs_eusart_transceive_async(const struct device *dev,
|
||||
const struct spi_config *config,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs,
|
||||
struct k_poll_signal *async)
|
||||
const struct spi_config *config,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs,
|
||||
spi_callback_t cb,
|
||||
void *userdata)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
return spi_silabs_eusart_transceive(dev, config, tx_bufs, rx_bufs, true, cb, userdata);
|
||||
}
|
||||
#endif /* CONFIG_SPI_ASYNC */
|
||||
#endif
|
||||
|
||||
static int spi_silabs_eusart_release(const struct device *dev, const struct spi_config *config)
|
||||
{
|
||||
|
|
@ -286,33 +665,53 @@ static int spi_silabs_eusart_release(const struct device *dev, const struct spi_
|
|||
if (!(eusart_config->base->STATUS & EUSART_STATUS_TXIDLE)) {
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Device Instantiation */
|
||||
static DEVICE_API(spi, spi_silabs_eusart_api) = {
|
||||
.transceive = spi_silabs_eusart_transceive,
|
||||
.transceive = spi_silabs_eusart_transceive_sync,
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
.transceive_async = spi_silabs_eusart_transceive_async,
|
||||
#endif /* CONFIG_SPI_ASYNC */
|
||||
#endif
|
||||
.release = spi_silabs_eusart_release,
|
||||
};
|
||||
|
||||
#define SPI_INIT(n) \
|
||||
PINCTRL_DT_INST_DEFINE(n); \
|
||||
static struct spi_silabs_eusart_data spi_silabs_eusart_data_##n = { \
|
||||
SPI_CONTEXT_INIT_LOCK(spi_silabs_eusart_data_##n, ctx), \
|
||||
SPI_CONTEXT_INIT_SYNC(spi_silabs_eusart_data_##n, ctx), \
|
||||
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)}; \
|
||||
static struct spi_silabs_eusart_config spi_silabs_eusart_cfg_##n = { \
|
||||
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
||||
.base = (EUSART_TypeDef *)DT_INST_REG_ADDR(n), \
|
||||
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
|
||||
.clock_cfg = SILABS_DT_INST_CLOCK_CFG(n), \
|
||||
.clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000) \
|
||||
}; \
|
||||
SPI_DEVICE_DT_INST_DEFINE(n, spi_silabs_eusart_init, NULL, &spi_silabs_eusart_data_##n, \
|
||||
&spi_silabs_eusart_cfg_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,\
|
||||
&spi_silabs_eusart_api);
|
||||
#ifdef CONFIG_SPI_SILABS_EUSART_DMA
|
||||
#define SPI_SILABS_EUSART_DMA_CHANNEL_INIT(index, dir) \
|
||||
.dma_chan_##dir = { \
|
||||
.chan_nb = -1, \
|
||||
.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)), \
|
||||
.dma_slot = \
|
||||
SILABS_LDMA_REQSEL_TO_SLOT(DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)),\
|
||||
},
|
||||
#define SPI_SILABS_EUSART_DMA_CHANNEL(index, dir) \
|
||||
COND_CODE_1(DT_INST_NODE_HAS_PROP(index, dmas), \
|
||||
(SPI_SILABS_EUSART_DMA_CHANNEL_INIT(index, dir)), ())
|
||||
#else
|
||||
#define SPI_SILABS_EUSART_DMA_CHANNEL(index, dir)
|
||||
#endif
|
||||
|
||||
#define SPI_INIT(n) \
|
||||
PINCTRL_DT_INST_DEFINE(n); \
|
||||
static struct spi_silabs_eusart_data spi_silabs_eusart_data_##n = { \
|
||||
SPI_CONTEXT_INIT_LOCK(spi_silabs_eusart_data_##n, ctx), \
|
||||
SPI_CONTEXT_INIT_SYNC(spi_silabs_eusart_data_##n, ctx), \
|
||||
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
|
||||
SPI_SILABS_EUSART_DMA_CHANNEL(n, rx) \
|
||||
SPI_SILABS_EUSART_DMA_CHANNEL(n, tx) \
|
||||
}; \
|
||||
static struct spi_silabs_eusart_config spi_silabs_eusart_cfg_##n = { \
|
||||
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
||||
.base = (EUSART_TypeDef *)DT_INST_REG_ADDR(n), \
|
||||
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
|
||||
.clock_cfg = SILABS_DT_INST_CLOCK_CFG(n), \
|
||||
.mosi_overrun = (uint8_t)SPI_MOSI_OVERRUN_DT(n), \
|
||||
.clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000), \
|
||||
}; \
|
||||
SPI_DEVICE_DT_INST_DEFINE(n, spi_silabs_eusart_init, NULL, \
|
||||
&spi_silabs_eusart_data_##n, &spi_silabs_eusart_cfg_##n, \
|
||||
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_silabs_eusart_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue