The arm_arch_timer driver only uses the architecture-level
IRQ_CONNECT/irq_enable abstractions, both of which dispatch through
arch_irq_*() and therefore work whether the underlying interrupt
controller is a GIC or a SoC-supplied custom controller. The latter
is selected via CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER, in which
case the arm64 arch layer maps the calls to the SoC-provided
z_soc_irq_* hooks.
The "depends on GIC" predates custom-intc support landing in arm64
and is artificially restrictive. Relax it so non-GIC arm64 SoCs can
reuse the canonical timer driver instead of cloning it.
The driver itself is unchanged.
Signed-off-by: Jonathan Elliot Peace <jep@alphabetiq.com>
Fixing some target misbehaviors I found while working with
a multi-target setup. Namely:
1. Potential missing event when swapping directions / repeated
starts
2. Make target more robust against controller timing between
ACK and sending first byte
3. Target defaulted to ACKing every address, now checks for match
4. Set pins back to default gpio when unregistering, and
reconfigure them for i2c when registering. This prevents an
unregistered I2C from breaking the bus by holding it low
5. Disabled NVIC when unregistering targets. Infineon has dedicated
interrupts for SCBs, so this is safe.
6. Preemptively arm wrie buffer to avoid a potential race condition
when target RX auto-ACK is enabled
Restructure the event handler since it was getting too large - split
out a target path
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
The implementation of the "system timer low-power companion interface"
when CONFIG_SYSTEM_TIMER_LPM_COMPANION_COUNTER is selected is generic,
but was done in the Cortex-M SysTick driver for historical reasons.
Move the implementation to a common source file included in the build
when CONFIG_SYSTEM_TIMER_LPM_COMPANION_COUNTER is selected. This cleans
up the Cortex-M SysTick driver and allows other system timer drivers to
benefit from the code.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The Digital Filter for Sigma Delta Modulators (DFSDM) is dedicated to
interface external Σ∆ modulators.
It features:
* Up to 8 multiplexed input digital serial channels:
– SPI or Manchester-coded 1 wire interface
– clock output for Σ∆ modulators
* Up to 8 internal digital parallel channels:
– up to 16 bit resolution
– internal sources: memory (CPU/DMA write) data streams
* Adjustable digital signal processing
* Up to 24-bit output data resolution
* Signed output data format
* Continuous or one-shot conversion
* “regular” or “injected” conversions
* Analog watchdog
* Short-circuit detector
* Min/Max extremes detector
* DMA read access
* Interrupts for end of conversion, overrun, analog watchdog,
short-circuit, channel clock absence
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
The LLI descriptor cache flush was unconditionally performed even
when a Cache Coherence Unit (CCU) is present. When CCU is enabled,
hardware guarantees a consistent data view between the DMA and
processor, making software cache maintenance redundant.
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
The max_channel is a compile time constant derived from device tree
and never modified at runtime.
Adding it to read only dev_cfg structure and using this variable from
dev_cfg structure
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
Abstract DT reset property check into a reset_supported macro,
update variable type to uint32_t, and remove channel < 0
check which is always false because of the uint32_t type
variable
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
The driver used a plain enum for channel state tracking which is
not safe on multi-core systems. A plain enum read-modify-write is
not guaranteed atomic on SMP a concurrent read on another core
could observe a torn or intermediate state value.
Replace ch_state with atomic_t and use atomic_set()/atomic_get()
for all channel state transitions. This ensures state visibility
across all cores without blocking, and preserves ISR callability
as required by the Zephyr DMA API
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
Previously, upstream left the AXI CTL fields at 0. Now adding the
AxCache and AxProt attributes macro and setting to the values
required for cache-coherent interconnect in Agilex5.
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
The driver currently checks for DT_INST_PROP_OR(n, ...). n is not
defined, it should be inst.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The stop_det handler resets dw->state to READY and clears
read_in_progress before calling the target's stop() callback.
The driver is already in READY stateand a concurrent interrupt
may observe an inconsistent view.
Invoke stop() first, then reset state. This matches the ordering of
most other Zephyr I2C target drivers and keeps the state transition
atomic with respect to the callback.
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
dw->read_in_progress is only cleared in the stop_det branch of the
target ISR and at target_register() time. If a master read is
aborted by NACK (tx_abrt) or by bus error (rx_under/rx_over/tx_over)
without a terminating STOP, the flag remains set. The next legitimate
master read then takes the else branch and invokes read_processed()
instead of read_requested(), so the target never sees a fresh
read transaction and returns stale data.
Clear read_in_progress in every error path that resets dw->state
to READY.
i2c_dw_slave_read_clear_intr_bits() previously re-read IC_INTR_STAT
locally, while i2c_dw_isr() had already cached the same register at
entry. Two independent reads of a hardware status register create a
race: bits can be asserted by hardware between the two reads, causing
the helper and the ISR to observe different views of the interrupt
state.
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
Assisted-by: Claude:claude-opus-4.7
The target ISR gates write_requested() on `dw->state != CMD_SEND` so
that back-to-back rx_full interrupts during a single write do not
re-enter the callback. However, dw->state is only transitioned back
to READY on stop_det. If the STOP interrupt is lost (glitch, bus
reset, another master drives STOP while we are servicing the ISR),
or if the master issues a repeated START with the same direction
(WRITE-Sr-WRITE, which is legal in I2C), the state stays CMD_SEND
forever and write_requested() is never called again for the rest of
the target's life.
i2c_dw_slave_read_clear_intr_bits() already handles start_det by
resetting state to READY, but START_DET is not in the enabled
interrupt mask in i2c_dw_slave_register(), so that path is dead code.
Unmask START_DET so the boundary of every new (re)START on the bus
is observed and state is correctly reset before the rx_full handler
decides whether to call write_requested().
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
Replace the driver-private spinlock with the unified timer lock API
introduced by commit 32b1399669 ("kernel/timeout: introduce
sys_clock_lock() and sys_clock_announce_locked()"), following the
pattern already applied to other SMP-capable timer drivers.
No in-tree board enables CONFIG_SMP on a Cortex-M, so the specific
two-CPU race that motivated that commit does not apply here. The
same two-lock window is still reachable in UP, though: a nested IRQ
handler that uses time facilities can fire between sys_clock_isr()'s
update of the hardware baseline (cycle_count, announced_cycles,
under the driver-private lock) and the sys_clock_announce() call
that advances curr_tick (under the kernel's timeout_lock), see the
two halves of "now" out of sync, and observe time going backwards
from one call to the next. Putting the hardware cycle baseline and
curr_tick under a single lock closes that window the same way it
does on SMP.
As a direct consequence, sys_clock_set_timeout() and
sys_clock_elapsed() no longer need to acquire anything -- the caller
already holds the kernel timeout lock across both the driver call
and the following sys_clock_announce(). The driver is now consistent
with the convention used by all the other timer drivers.
sys_clock_cycle_get_32() / sys_clock_cycle_get_64() /
sys_clock_idle_exit() / z_sys_clock_hw_cycles_per_sec_update() are
called from contexts that do not hold the kernel's timeout lock, so
they acquire it via sys_clock_lock() themselves.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Rework sys_clock_set_timeout() along the same lines as the RISC-V
machine timer (drivers/timer/riscv_machine_timer.c) and ARM generic
timer (drivers/timer/arm_arch_timer.c) drivers: compute the absolute
cycle target for the next fire and program SysTick for the delta to
it, rather than reconstructing a tick-aligned fire point on every
call through the old "-1, round up to tick boundary, subtract
unannounced" dance.
The core of the computation shrinks from:
delay = ticks * CYC_PER_TICK;
delay += unannounced;
delay = DIV_ROUND_UP(delay, CYC_PER_TICK) * CYC_PER_TICK;
delay -= unannounced;
delay = MAX(delay, MIN_DELAY);
if (delay > MAX_CYCLES) { last_load = MAX_CYCLES; }
else { last_load = delay; }
into:
int64_t want = ((uint64_t)last_elapsed + ticks) * CYC_PER_TICK;
int64_t delta = want - unannounced;
cycles = CLAMP(delta, MIN_DELAY, MAX_CYCLES);
SysTick->LOAD = cycles - 1;
No tick-boundary realignment and no DIV_ROUND_UP round-trip. The
64-bit intermediate absorbs arbitrarily large 'ticks' without
overflowing the 32-bit cycle product. The division-by-CYC_PER_TICK
that lived in the hot path is gone (divisions by non-constant
divisors are costly even on 32 bits, so avoiding them where we can
is worthwhile).
Concretely:
* Track last_elapsed -- the tick count most recently returned to the
kernel via sys_clock_elapsed() -- and use it as the "now" reference
when computing the deadline. sys_clock_isr() resets last_elapsed
to 0 on every announce.
* The pre-clamp on 'ticks' and the MAX_TICKS derivation are gone:
the clamp applies to the computed cycle count (the quantity the
hardware LOAD register actually constrains), and MAX_CYCLES is
the 24-bit COUNTER_MAX directly.
* Explicitly clear SCB->ICSR PENDSTCLR on every reprogram. Writing
SysTick->VAL = 0 clears CTRL.COUNTFLAG but leaves any pending
SysTick exception from the old schedule armed in ICSR. Without this
explicit clear, a wrap that fired between sys_clock_elapsed() and
the LOAD/VAL reset would still trigger the ISR once interrupts are
re-enabled, with the ISR then reading the new LOAD/VAL and
mis-accounting the elapsed time. Matches the pattern already used
in the LPM RESET_BY_LPM path.
The elapsed() helper, overflow_cyc bookkeeping, LPM companion paths,
runtime frequency update, 64-bit cycle counter variant, the val1/val2
drift-compensation dance around the LOAD/VAL write, and the
non-tickless fallback are untouched. The wire-level behaviour is
identical in the normal case; the only observable behaviour change
is the PENDSTCLR write, which closes a latent race that could delay
a stale ISR by one LOAD worth of cycles.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Added autonomous analog CTDAC for PSE84 device.
This implementation uses the autonomous controller (MFD)
that is shared with other autanalog drivers.
The CTDAC stands for Continuous Time DAC. It is a programmable DAC
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
The DAC output can either be software controlled or be driven
through the AC hardware by loading through an internal LUT memory.
AC MFD references the DAC configuration, and brings together all
other autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
This PR introduces the `sda-hold-time-ns` DeviceTree property for
DesignWare I2C controllers. The driver logic is updated to prioritize
this nanosecond configuration, calculating the necessary hardware clock
ticks at build time using the new `HOLD_TIME_TO_TICKS` macro. If the
property is not defined, it safely falls back to the legacy
`sda-hold-tx` tick configuration.
Fixes#83437
Signed-off-by: Akansh Sinha <akansh.sinha.dev@gmail.com>
Add support for configuring the minimum timer delay via the Devicetree
property 'zephyr,min-timeout-cycles'. This is particularly useful for
platforms using low-frequency clock sources (e.g., 32.768 kHz).
The driver's default MIN_DELAY is MAX(1024, CYC_PER_TICK / 16). On a
system with a 32.768 kHz clock and CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000,
CYC_PER_TICK is 32. This results in a MIN_DELAY of 1024 cycles, which
translates to a ~31 ms minimum timeout. This granularity is too
coarse for tickless operation and causes failures in tests that expect
sub-10ms precision.
This change allows boards to override this limit, enabling finer timing
resolution while maintaining the existing default for backward
compatibility.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Allow configuring the clock source for TI's dmtimer using syscon driver for
MMR writes. The new property "clksel" takes offset and value to select
the mux configuration.
This is required since there are no clock parent APIs in the clock
controller subsystem as of now.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
The i2c bus may be pulled low by unstable environment.
Check the status before I2C transfer and
skip transmission if the bus is not ready.
Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
- Switch binding to zephyr,cellular-modem-device.yaml
- Use MODEM_DT_INST_PPP_DEFINE to properly associate PPP with the modem
device and preserve runtime PM integration
Signed-off-by: Luca Impagliazzo <Luca.Impagliazzo@telit.com>
Add an event for broadcasting the current network status (Cell tower
info) to application users. There is no common 3GPP AT command that
provides this information, but vendor-specific commands appear to exist
for most modems. e.g. `AT%XMONITOR` for Nordic and `AT#RFSTS` for Telit.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Store the current registration access technology internally.
Switch cellular drivers to request the long form registration events to
extract this information. The `+CREG`, `+CGREG` and `+CEREG` commands
are 3GPP standards, but no effort has been made to check that each modem
supports the `2` mode beyond the nRF91 and Telit LE910C1 modems.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add the i2c_target_register and i2c_target_unregister callbacks
for the ESP32 I2C driver. The target path uses the SCL stretch
interrupt to feed one byte per controller clock, supports the
byte-by-byte and buffer-mode callbacks, and reports bus errors
through the optional error callback.
The same instance can act as controller between target
callbacks, since i2c_transfer temporarily switches it to
controller mode and restores the target configuration when the
transaction ends.
Target mode requires the SCL stretch-cause hardware feature and
is therefore enabled on ESP32-S2, S3, C3, C5, C6 and H2 only.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Having an interface library named "mbedTLS" and the real library named
"mbedtls" (as provided by the Mbed TLS module) is misleading.
This commit replaces:
- mbedTLS -> mbedtls_iface for the CMake library. "mbedTLS" is still
available as alias to "mbedtls_iface" for backward
compatibility, but this should be removed in the future.
- mbedTLS -> Mbed TLS in comments and documentation.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
The DM9051 IC automatically appends a 4-byte CRC to each frame
stored in internal SRAM. The original driver did not account for
this, causing potential buffer overflow for large frames.
Add ETH_DM9051_CRC_SIZE constant and increase TX/RX buffer sizes
accordingly. Use IN_RANGE macro for RX length validation and
sizeof(data->rx_buf) for length checks.
Fixes: buffer overflow when receiving frames close to MTU (1500 bytes)
Fixes: potential RX length check issues with hardcoded values
Fixes: missing minimum frame size validation
Suggested-by: jukkar
Signed-off-by: Ching Ping Sun <tom_sun@davicom.com.tw>
There is such situation where the PINCTRL is enabled but no pinctrl
state for i2c dw, we need to skip the pinctrl_apply_state() otherwise
the driver can't be initialized successfully.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Remap brightness values from the [0, 255] range to the
[0, LED_BRIGHTNESS_MAX] range before calling
led_set_brightness_dt().
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
The FLEXCAN_MbHandleIRQ function expects the last mailbox index as a
parameter, not the total number of mailboxes. Mailbox indices are
zero-based (0 to N-1), so passing the mailbox count directly causes
an off-by-one error that could lead to accessing an invalid mailbox
index during interrupt handling.
This fix changes the fourth parameter from `config->number_of_mb` to
`config->number_of_mb - 1U`, ensuring the correct last mailbox index
is passed to the IRQ handler.
The issue could manifest as incorrect interrupt handling or potential
memory access violations when processing CAN mailbox interrupts,
particularly when all available mailboxes are configured in classical
CAN.
Signed-off-by: William Tang <william.tang@nxp.com>
Drop scmi_system_protocol_message_attributes() checks and rely on
scmi_system_power_state_set() return value instead, since protocol
attributes do not guarantee support for specific power states.
This simplifies the logic and ensures consistent handling of reboot
requests. Also improve error logging by including the requested
power state.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
After GPIO-based I2C bus recovery, pinctrl_apply_state() restores
the SCL/SDA pin configuration, but the I2C peripheral registers
remain in a faulted state. This causes the bus to remain unusable
after recovery completes.
Call i2c_stm32_runtime_configure() after restoring pin state to
fully reinitialize the peripheral registers, leaving the bus in
a known-good working state.
Fixes#108956
Signed-off-by: Moksh Panicker <mokshpanicker.7@gmail.com>
Select the internal 4.096V reference during init. The REF_SEL register
defaults to external, causing 0V output when no external reference is
connected.
Signed-off-by: Radu Ciobanu <Radu-rares.Ciobanu@analog.com>
Replace the custom bee_keyscan_all_released_and_debounced function with
input_kbd_matrix_active.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add CPU PLL initialization, configuration, and clock gating for BL808.
The CPUPLL uses the same WAC PLL register layout as AUPLL, located at
CCI_BASE + 0x7D0 with CCI_CPUPLL_* field prefixes.
Config tables provide per-crystal analog parameters and SDMIN values
for the 480 MHz reference frequency. CPUPLL is the default root clock
source in bl808.dtsi at 320 MHz, with BCLK at 80 MHz. Boards can
override up to 480 MHz via DTS overlay.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add Audio PLL initialization, configuration, and clock gating to the
BL808 clock controller. The AUPLL uses the CCI register block at
offset 0x750 with the same WAC PLL layout as WIFIPLL.
Config tables provide per-crystal analog parameters and SDMIN values
targeting 442.368 MHz (48 kHz audio family). BFLB_MUL_CLK scales to
other frequencies such as 451.584 MHz for the 44.1 kHz family.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add support for the TI TMP451 remote and local temperature sensor.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Kurtis Dinelle <kurtisdinelle@gmail.com>
The pinmux controller for the aesc silicon platform is a simple
controller to mux differnt input outputs to one output option.
Since this is an internal controller, pull, drive strength and slew
rate are not implemented due missing IO pad features.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add pm_device_action callback to handle the display's power
management actions. The driver initializes via
pm_device_driver_init. First-time hardware setup lives in the
TURN_ON action so the framework runs it once the device's power
domain is on. On suspend the driver sends DISPOFF followed by
SLPIN. On resume it sends SLPOUT followed by DISPON, with delays
per datasheet.
Datasheet delays in suspend and resume branch on k_can_yield():
yield-safe contexts use k_msleep, otherwise k_busy_wait. This
keeps both runtime-PM (regular thread) and system-managed (idle
thread, IRQs locked) callers safe.
Register the driver with PM_DEVICE_DT_INST_DEFINE so the PM
framework or runtime PM can control the display power state.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Install default EEPROM read API delegate to avoid unitialized "out"
variable when no delegate is installed by the application/test suite.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Install default CAN API delegates to avoid unitialized "out" variables when
no delegate is installed by the application/test suite.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
