remove the use of phy_configure_link() in the ethernet drivers.
The user can now select the default speeds via DT prop, doing
another phy_configure_link() in the eth driver would overwrite
that.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
fixed link mode is a mode where we don't comunicate with the phy,
therefore we don't need it in other phys as the generic phy_mii one.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
1. Fixed the bug that DAC value was set incorrectly.
2. The MIMXRT700 does not have windowed mode and
'enableSample' controls, code added for compatibility
on this platform.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Don't automatically enable device runtime PM on the SPI port just
because `PM_DEVICE_RUNTIME` is enabled. Require the user to explicitly
call `pm_device_runtime_enable` on the port, or add
`zephyr,pm-device-runtime-auto` to the devicetree node.
Through the usage of `pm_device_driver_init`, the default clock control
and pinctrl handling can all be contained in `spi_stm32_pm_action`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This commit adds config_get support for native_tty. This is helpful as
some driver code (e.g. u_blox m8) will error out if they can't read the
current configuration.
Signed-off-by: Vytautas Virvičius <vytautas@virvicius.dev>
Also increase regulator init priority so that ethernet vdd is
turned before PHY initialization
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Re-use the workqueue instead of having dedicated thread for handling
interrupts. This reduces memory usage and complexity.
Furthermore adds an auto mode for 100BASE-T1 negotiation.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The modem modules cmux module is currently directly coupled to the
presence of specific modems, rather than being selected by drivers
for whatever hardware wants to request the default MTU of 127 bytes.
This commit the makes the device drivers (for now, modem_cellular)
select the symbol, thus decoupling the modem modules from the
presence of any specific device.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Use wrapper function for read operations to allow using the new HAL
function that handles ECC checks and erased page detection.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
To fix MAX32690 flash problems, I created a wrap version of
MXC_FLC_Write(...) function which disables ICC before calling write
function and enables ICC after this function.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Disable interrupts during flash operations to prevent unintended jumps.
Interrupts are now disabled before read, erase, and write operations to
avoid accidental jumps to other flash sections while working on a
specific section.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Avoid entering low-power state during I2C host transfers in PIO mode.
Entering a low-power state during an active PIO transfer may prevent
the peripheral from generating the clock signal correctly,
resulting in transmission errors.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Avoid entering low-power state during I2C host transfers in PIO mode.
Entering a low-power state during an active PIO transfer may prevent
the peripheral from generating the clock signal correctly,
resulting in transmission errors.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Avoid entering low-power state during I2C host transfers in PIO mode.
Entering a low-power state during an active PIO transfer may prevent
the peripheral from generating the clock signal correctly,
resulting in transmission errors.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Allows enabling the Clock Recovery System (CRS) for HSI48 to achieve
the expected accuracy for USB transfers. Uses USB SOF packet by default.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
The Intel i226 Ethernet Controller is a PCIe Gen 2 one-lane modular
endpoint device that integrates a GbE Media Access Control (MAC) and
Physical Layer (PHY) port. This driver provides support for MAC and
DMA-specific initialization and runtime TX/RX operations.
Key features:
- MSI-X interrupts for TX/RX DMA channels.
- Multiple TX/RX DMA channel support with exclusive bottom-half.
- Implements a circular descriptor ring architechture with
producer-consumer semantics for high performance pkt processing.
- Full duplex support for 10/100/1000 Mbps.
- Half duplex support for 10/100 Mbps.
- Auto-negotiation for 10/100/1000 Mbps.
- MTU customization for flexible packet sizes.
- MAC address filtering based on:
- Random MAC generation.
- Local-mac-address mentioned in device tree.
- EEPROM pre-programmed mac address.
- Setting mac address via net shell.
- Support for multiple Ethernet interface instances.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
Intel i226 MAC supports MDIO C22 and MDIO C45. Standard PHY registers
are accessible through MDIO C22, whereas PMAPMD and PCS are accssible
through MDIO C45.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
The Ethernet device model consists of multiple subsystem components, such
as MDIO, PHY, MAC and PTP_CLOCK. These components are mapped into a single
PCIe BAR location with same base address.
This platform driver retrieves the MMIO mapping details and provides a
framework to share it with all the child subsystem components. This
approach avoid the duplicate remapping, ensures efficient re-use of
MMIO mappings across related devices.
Example device tree structure for first ethernet instance:
parent0: parent0 {
compatible = "intel,eth-plat";
interrupt-parent = <&intc>;
vendor-id = <0x8086>;
device-id = <0xXXXX>;
igc0: igc0 {
compatible = "intel,igc-mac";
/*
* MAC specific properties.
*/
status = "okay";
};
mdio0: mdio0 {
compatible = "intel,igc-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy";
/*
* PHY specific properties.
*/
reg = <0x0>;
};
};
};
This framework is modular and re-usable for other PCIe based Ethernet
devices. It can also be extended to support additional platform specific
information shared across child nodes.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
This reverts commit fd88386a9f, it breaks
uart support on ITE platforms when PM is enabled but PM_RUNTIME is not,
possibly others as well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move handling of write-to-clear status and stop detect to the
beginning of the ISR for PIO mode to reduce unnecessary clock
stretching and improve responsiveness during transfers.
This patch also separates status clearing for shared FIFO mode,
ensuring it is done at the appropriate point after data handling
completes, maintaining correct transfer behavior.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
When dual-flash mode is enabled, any erase operation is executed on both
flash memories in parallel. This means from the flash driver's point of
view, the size of a given sector/block is twice the size of a
sector/block on a single flash memory.
For example, assuming 4-KiB sectors for each flash memory, if the flash
driver is asked to erase at address 0x0000, the erase size must be a
multiple of 8 KiB since each sector erase operation will cause a 4-KiB
sector to erased in each flash memory.
Before this commit, the doubled erase size was only considered in
'setup_pages_layout'. Now, the actual sizes of the erase operations are
properly set in the flash driver's data and are used everywhere in the
driver.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
When dual-flash mode is enabled, even bytes are written to the first
flash memory and odd bytes to the second flash memory. This means, from
the flash driver's point of view, the size of a flash page is twice the
size of a single flash memory's page.
So if each flash memory has 256-byte pages, 512 bytes should be used as
page size by the flash driver. Using 256 bytes was working fine but is
suboptimal.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
When dual-flash mode is enabled, two identical flash memories are
connected to the QUADSPI peripheral, each having its own set of
registers. This means that when reading or writing a flash register,
this has to be made for both flash memories.
For example, when reading a status register (1 byte), the QUADSPI
peripheral must be configured to read two bytes of data, which
correspond respectively to the value of the register in the first and
second flash memory. Same thing when writing.
Before this commit, when dual-flash mode was enabled, only the register
of the first flash memory was considered, which means the second flash
memory could be incorrectly configured and that any write/erase
operation could be considered as completed too early, if the operation
takes more time to complete for the second flash memory.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
The 'qspi_read_status_register' routine implements the reading of a
flash memory's status register. This routine is used anytime reading a
status register is needed, except in 'qspi_wait_until_ready'. This
commit moves the read routine to be able to use it in
'qspi_wait_until_ready'. The 'qspi_write_status_register' is also moved
to keep it close to the read routine.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
In multiple places, "#if DT_PROP(DT_NODELABEL(quadspi), dual_flash) &&
defined(QUADSPI_CR_DFM)" was used to guard sections specific to
the dual-flash feature. This is quite long and "#ifdef
STM32_QSPI_DOUBLE_FLASH" is now used instead.
Note the presence of QUADSPI_CR_DFM is no more checked. This is not
considered as an issue since when QUADSPI_CR_DFM is not available, the
QSPI hardware doesn't support dual-flash mode so this mode must not be
enabled in the devicetree. With that change, enabling dual-flash mode
when not available causes a compile-time error.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
Add support for disabling autonegotiation to the cfg_link callback, as
with the phy_mii driver.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The driver previously could enter an infinite loop if the PHY software
reset failed to complete, which could happen due to hardware reset
issues or MDIO bus problems. Add a timeout of 1000 iterations so we
report an error in this scenario rather than causing a lockup.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
For GPIOs driving active-low signals, such as the VSC8541's reset pin,
they are supposed to be declared as active low in the device tree, and
set to 1 to assert and 0 to clear. Change the driver as such so that it
does not leave the PHY stuck in reset when so configured.
Also changed all in-tree board DTS files for this PHY to properly
declare the reset GPIO as active low.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The internal register read/write functions used uint32_t for the values
even though the registers are only 16 bits wide, resulting in a bunch of
casting. Change the internal functions to use uint16_t and wrap them for
the external read/write API which uses uint32_t.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The driver was not enabling the MDIO bus before trying to access
registers. Added enabling and disabling the bus around PHY register
accesses.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Fixed some build warnings in the driver from previous changes by
removing an unused variable and hooking up the cfg_link function. Also
removes some implicit boolean conversions.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
use mutex to protect page register
phy_mc_vsc8541_get_link got removed from
phy_mc_vsc8541_link_cb_set so, that
phy_mc_vsc8541_link_monitor (own thread)
is the only one to change data->state
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
- implement configure link
- support half duplex
- use defines from mii.h
- fix check ret vals
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a flash driver that is used to perform flash operations on a flash
chip that is connected to an Andes QSPI controller and is used for XIP
mode.
The driver is as small as possible, because necessary code has to be
placed in RAM. It is not possible to fetch code from flash while
performing erase/write operations.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
This commit adds a new driver for the MaxBotix MB7040 ultrasonic
rangefinder. The driver uses I2C communication to read range data
from the sensor and exposes it via the Zephyr sensor API.
Tested on an esp32-s3 board using I2C bus. Verified readings at multiple
distances to confirm accuracy.
Signed-off-by: Sabrina Simkhovich <sabrinasimkhovich@gmail.com>
Monitor mode doesn't require station mode. Disabling station mode
require necessary changes to work monitor mode.
Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
Previously, the clock_frequency property defined in the Device Tree was
not applied to the I2C controller, causing the controller to ignore the
specified bitrate configuration if no other config for speed. When using
default hardware settings, the lack of an explicit timing or frequency
config may result in the controller ignoring bitrate settings. This change
ensures that the clock_frequency value from DTS is now correctly mapped
and set during controller initialization, allowing the bitrate to take
effect as intended. This improves hardware configurability and ensures
the I2C bus operates at the desired speed specified in the Device Tree.
Signed-off-by: Xiaolu Sun <xiaolu.sun@intel.com>
when CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC set to 960M
and CONFIG_SYS_CLOCK_TICKS_PER_SEC set to 100
the MAX_TICKS will be zero or even negative value, which is not
expected.
so need add a protection here downgrading the accuracy to
its as high as possible
also add build message to show that tickless has no effect
fixes: #36766
there used to be a workaround, not a fix,
either change the CONFIG_SYS_CLOCK_TICKS_PER_SEC=200
or
CONFIG_PM to set the CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
to 32678
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
paj7620 log module was being registered twice ; use LOG_MODULE_DECLARE
instead in paj7620_trigger.c
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Previously, phy_monitor_work_handler() would return early without
rescheduling the delayed work if the callback (cb) was not set,
causing the periodic monitoring to stop. This change ensures that
k_work_reschedule() is always called, even when cb is NULL, so
monitoring of the PHY state continues.
This prevents the monitor from being inadvertently stopped and
ensures consistent behavior regardless of callback registration.
This issue was observed during testing with the evb-lan8670-rmii
(an external LAN8670 PHY) connected to the SAME54 Curiosity Ultra
platform.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Call mdio_bus_enable() and mdio_bus_disable() during clause 22 register
read/write operations. Previously, these APIs were not invoked, which
could lead to improper MDIO bus handling.
This issue was observed during testing with the evb-lan8670-rmii
(an external LAN8670 PHY) connected to the SAME54 Curiosity Ultra
platform.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
