z_timer_idle_enter is declared only when CONFIG_TICKLESS_IDLE is
selected. This function is not implemented anywhere, but the only
driver including this header is not TICKLESS_CAPABLE. So, no undefined
reference will happen.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Use TX FIFO level interrupt if available in hardware. It matches the
Zephyr UART API and avoids "bootstrapping" which is needed when using
the TX edge interrupt ("TI"). TX FIFO has room for up to 32 characters
and will typically reduce the number of interrupts.
Details:
APBUART can be synthesized with or without support for TX/RX FIFO.
Edge interrupts which fire when TX holding register changes and RX data
available are always available, independent of the FIFO configuration.
If FIFO is made available at synthesis time, two additional interrupts
become available: TX FIFO half-empty and RX FIFO half-full. These
are level interrupts.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit aligns the GRLIB APBUART driver with the Zephyr UART API
and fixes an issue where TX interrupt could previously be lost. It
was typically seen during interactive operation in the Zephyr shell.
There is an expectation in the Zephyr UART API that TX ready (i.e. TX
buffer space available) interrupt is a level interrupt, i.e. always
active while there's TX buffer space available. In particular, there's
an expectation that after uart_irq_tx_enable(), the TX interrupt will
immediately fire (assuming free TX buffer space is available).
The APBUART "Transmitter interrupt (CTRL_TI)" does not directly fulfill
this expectation because it is edge triggered and fires when the TX
holding register moves from being non-empty to empty. The solution
is to "bootstrap" interrupt processing by calling user-defined ISR
in irq_tx_enable().
This fix is similar to commit 49bb163756 ("drivers: serial:
uart_cmsdk_apb: Fix interrupt-driven operation").
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The driver allocated packet from the TX pool on its RX path. Fix this
by using a correct allocator function.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
ESP chip send number of available RX data using
+IPD=<sock>,<avail_bytes> command. This exact number (truncated to MRU)
was used to read data with AT+CIPRECVDATA=<sock>,<num_of_bytes>.
Use always MRU when sending AT+CIPRECVDATA=<sock>,<mru> request. When
there are less bytes available, then +CIPRECVDATA will just return less
bytes, which is fine for the driver.
There are two advantages to this new behavior:
* there is no need to follow how many bytes were notified by +IPD
message, thus reducing implementation size,
* when data is constantly received by ESP chip, then the last number of
bytes notified by +IPD is no longer up-to-date when sending a
AT+CIPRECVDATA; always requesting MRU number of bytes allows to
always receive maximum currently available number of bytes buffered
by ESP chip.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Dump of communication between ESP chip and Zephyr shows that
+IPD:<sock>,<bytes_avail> is always received after +CIPRECVDATA. This
means that we don't need to update sock->bytes_avail in esp_workq
thread. Additionally there is no need to schedule next AT+CIPRECVDATA
request, as that will be done by +IPD handler anyway.
Relying on +IPD to be received after each +CIPRECVDATA (as long as there
is some more data to be received) allows to simplify operations on
sock->bytes_avail. From now on only esp_rx thread will update its value
and schedule AT+CIPRECVDATA in esp_workq thread. Then in
sock->bytes_avail will be treated as "readonly" in esp_workq
thread. This allows to prevent race condition when both esp_rx and
esp_workq threads could potentially update value of sock->bytes_avail
value at the same time.
<sock>,CLOSED message is received always after retrieving all data from
ESP chip (using AT+CIPRECVDATA), so there is no need to check whether
there are more bytes to be received before marking socket as closed in
Zephyr driver.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Add extra error data information to callback parameter. Add tests for
testing the data provided.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Split setting EDAC IBECC ctrl to setting error_type and
error_trigger to make it easier for other platforms.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Replace addr with param1 and addr_mask with param2 for get / set types
of functions. Those names are more general and allow to implement
error injections for other platforms.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add an emulation controller which routes eSPI traffic to attached
emulators depending on the selected chip(mostly host).
This allows drivers for eSPI peripherals to be tested on systems
that don't have that peripheral attached, with the emulator handling
the eSPI traffic.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
The default configuration is made to be "master" at
"standard speed". This makes it possible to use the
driver without having to configure it.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Enable slave support for I2C device instances. Slave mode is
interrupt based, wheras master mode is still based on polling.
Remove ENI bit in master configuration since it is not needed for
master mode.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Initial driver and sample application of
TDK Invensense ICM42605 6-axis motion sensor.
This driver provide DTS for nRF52 DK board DTS setting.
Providing features are below.
Sensor data streaming - Accel, gyro
Tap, Double tap triggering.
Set/Get FSR, ODR by set attr API
Support multi instance feature.
Signed-off-by: JuHyun Kim <jkim@invensense.com>
Move i2s_cavs_irq_connect_##n up so its available later when used. This
fixes compile issues with the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit verifies if the mac configuration is done correctly
during liteeth setup, and prompts a warning when not.
Signed-off-by: Pawel Sagan <psagan@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This commit eliminates an inifite waiting for the TX ready flag
in the eth liteeth driver, exiting with error after a defined
number of attempts.
Signed-off-by: Pawel Sagan <psagan@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This patch adds support for Microchip's KSZ8794 DSA device, which for
switch and PHY control uses SPI communication.
This driver also provides support for handling tail tagging added and
decoded in the KSZ8794 device as well as modifying entries in the
static MAC address table.
It is also possible to use GPIO pin to reset KSZ8794 switch.
When the "reset-gpios" property is not defined, software based reset
is performed instead.
The KSZ8794 can now be used on boards which have SPI CS only available
as GPIO pin.
Signed-off-by: Stefan Bigler <stefan.bigler@securiton.ch>
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch modifies Bluetooth HCI RPMsg drivers and samples to use
RPMsg Service instead of configuring OpenAMP directly in the driver
or the sample.
Co-authored-by: Piotr Szkotak <piotr.szkotak@nordicsemi.no>
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
Introduce a Kconfig variable that the SoC can set to indicate the
number of instances in Device Tree. This also fixes the accuracy of
the Elkhart Lake instance count where the code was previously assuming
up to 12 instances even though DT lists 15 nodes.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Move all PCIe-based DT nodes under a PCIe bus and take advantage of
the DT_ANY_INST_ON_BUS_STATUS_OKAY() and DT_INST_ON_BUS() macros.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Remove DW and PCA9685 PWM controller drivers as they are unmaintained
and broken.
Both drivers lack support for the pwm_get_cycles_per_sec_t API function
which was introduced in commit 56e0b53c6e
in 2016.
Fixes#18607, #18608
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit add support for i2c on imx6sx.
I2C support is based on imx7d and requires NXP HAL.
The Device Tree binding is also changed to better reflect that i2c
driver support both imx6sx and imx7d.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Refactor slightly so we can read SFDP tables with this driver. Note
that the SFDP read command requires long frame mode transfers as data
exceeds 8 bytes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
QSPI doesn't have a different length expectation than normal SPI, so
introducing a new name for an existing name is unnecessary. Also
replace the constant with the actual buffer size where appropriate, in
somebody changes the the buffer definition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Kconfig allowed selecting any bit in the status register as the QE
bit, and defaulted it to 6. Devices need not require a QE bit at all,
and where JESD216 defines QE bit location the only place in first SR
byte that it can be is bit 6. Further, the code unconditionally wrote
the value 0x40 without respecting configuration of other bits. Some
of those bits control write protection of block-protected areas and
should not be changed.
Remove the Kconfig, instead using the jedec,jesd216-controlled
devicetree property. Allow the driver to recognize whether or not
setting the bit is required, and when it is only use bit 6. Only
update if the setting does not match the configuration.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The interface used to send commands supports only a command followed
by 8 bytes of data transfer. Reject attempts to do more, as the
result will be a successful transfer of only the first 8 bytes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Not all special commands require that a write-enable be issued first.
Allow the caller to decide.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW16 provides information on mechanisms to enter and exit 4-Byte
address modes, returning the device to reset state, and how to
manipulate the values in the first status register.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW15 provides information on entry and exit from QSPI modes. In
particular, it specifies whether and how the status register must be
updated for this feature.
Add a JESD216 devicetree property for the Quad Enable Requirements
value.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Instead of having a hard-coded maximum instance count, introduce a
Kconfig variable for it. The inclusion of the per-instance header
files is solved by having them chain-include each other with a
pre-processor condition that checks if the current header file is the
last one or not.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The reg-shift support was quite broken in that the code only looked
for this property on instance 0. Now we support the property on any
node which might declare it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Take advantage of DT_INST_FOREACH_STATUS_OKAY() to look for DLF and
PCP properties on any matching nodes with "okay" status.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use a dependency block instead of specifying a UART_NS16550 dependency
for each individual opton. This doesn't save many lines right now, but
may do so once more options are added.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
