Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add initial implementation of the uart async api
for stm32 mcus. This uses the dma controller
in normal mode for reception. In addition, to detect
reception of bytes we enable the idle line detection
interrupt.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Signed-off-by: Jun Li <jun.r.li@intel.com>
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move iis2dlpc trigger pulse configurations from Kconfigs to Device Tree.
Moreover the dts properties have been renamed as 'tap', which sounds a
better name to immediately catch the feature behind it. Since tap
threshold cannot be zero, this value (which is the default in dts
binding) is used to enable/disable the device feature per each axis.
The event can be generated on INT1 only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Simplify the switch case on trigger types (SENSOR_TRIG_DRDY and
SENSOR_TRIG_TAP) inside iis2dlpc_enable_int().
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The IIS2DLPC drdy interrupt can be routed to either INT1 or
INT2 pin. Currently the selection is done by Kconfig configuration.
This commit is instead moving it into Device Tree as 'drdy-int'.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This patch replace CONFIG_GPIO_SIFIVE_N_PRIORITY into interrupt-cell
of device-tree to set IRQ priority.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch replace CONFIG_UART_SIFIVE_PORT_0_IRQ_PRIORITY into
interrupt-cell of device-tree to set IRQ priority.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
In #31192 stm32 uart driver uart_irq_rx/tx_ready functions were
modified to take into account status of irq.
While it seems wlecome for TX (based on uart client's implementation),
this is not correct for RX.
Revert change in uart_stm32_irq_rx_ready function.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Replace marco function, defined(), with IS_ENABLED() in host sub-devices
driver implementation. In this PR, we won't replace the macros which
cause -Wimplicit-function-declaration warning if related configuration
is not enabled or its type is not boolean..
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for DMA based STM32 QSPI NOR flash controller.
Driver configures both NOR flash and also QSPI hardware block.
Reuses existing jesd216 library.
QSPI hardware block handling is done through the use of Cube HAL API.
This requires the use of HAL interface also for DMA besides zephyr
DMA driver.
Zephyr DMA driver is used only for IRQ routing while HAL driver
handles the IP block. To achieve this it is required to:
-Configure both Cube and Zephyr drivers at init.
-Inform Zephyr driver that current channel handling will be done
by another instance and only a limited configuration should be done.
For this last part, a unused parameter is overridden in order to
transmit the information.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
In preparation for QSPI DMA mode:
-Add a possibility to override driver by the HAL DMA. In that case
stream is set as busy and no configuration nor treatment is done.
In case of interrupt, flags clearing is let to HAL.
-Treat Half Transfer interrupt prior to Transfer Complete for the
cases were both IRQ are both raised at the time IRQ handler is called
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
AHB3 bus support is added for compatible series.
Additionaly, fix condition for AHB2 support and fix
formatting
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
According to AT commands manual, no wait after prompt '@'
is required if using AT+USOST commmand (aka. sendto,
only used with UDP).
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
core-macros.h includes other files not part of the xtensa HAL, make this
esp32 specific
Fixes#31301
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF.
This WDT timer ensures correct hand-over and startup sequence from
bootloader to application.
Enabling bootloader caused system clock initialization to fail
when clock rate is greater then 80MHz. This also fixes
esp32 clock source code.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
-The STM32F410RB has no AHB2 bus so LL_AHB2_GRP1_EnableClock() and
LL_AHB2_GRP1_DisableClock() should not be called for this soc.
-The interrupt table had to be changed because of no OTG_FS_WKUP_IRQn
(no USB OTG at all).
Signed-off-by: Hans Unzner <hansunzner@gmail.com>
Convert the driver so that it creates its instance basing on DT.
Remove no longer needed Kconfig option CRYPTO_NRF_ECB_NAME.
Also update accordingly the crypto sample.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Since the PU power rail of i2c bus might be gone at the initial state
after ec powered up, we might have no chance to get STOP condition. This
is because no i2c transactions occurred before its power rail is
restored. But it's crucial to reset the whole i2c module after i2c bus
is back to the idle state.
The original test suite for i2c recovery mechanism didn't consider this
case that initial i2c bus is low before ec powered on. Hence, this CL
fixed this symptom by:
1. Force i2c modules must proceed 'reset' step no matter we received
STOP condition or not.
2. Use Boolean for condition check to prevent misusage and meet MISRA.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Extend the PWM API with optional API functions for capturing PWM pulse
width and period cycles.
Fixes#26026.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3
is used as a clock source by certain peripherals, e.g. LTDC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Provide a utility function to compute PLL VCO input range so that it
can be re-used for other PLLs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
When flash is Dualbank and flash size is lower than 512K,
then there is a discontinuity between bank1 and bank2.
Also take into account bank swap capability.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When setting baudrate register, baudrate value is computed according
to the oversampling given value, which is default boot time
value (16).
In case oversampling value has been changed by bootloader (as in case
of TFM bootloader), a desynchronsation happens between OVR and BRR
values and the ouptut baudarate is incorrect.
For oversampling register before setting the baudrate to avoid this
situation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When calling irq_rx_ready or irq_tx_ready API, return the logical AND
between the irq status and the enable of that irq.
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2 versions of DMA hardware blocks could be found across stm32 series.
In order to simplify the handling of matching Kconfig symbols,
make this visible in dts files by creating "st,stm32-dma-v1" and
"st,stm32-dma-v2" and set them accordingly in dtsi files.
Duplicate and update related bindings to reflect that new state.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
1. don't use "inline" in .c, let the compiler decide
2. remove superfluous parentheses
3. simplify a function by directly returning the result of a boolean
operation
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Some interrupts can be enabled by the ROM, e.g. the timer interrupt.
When then in Zephyr the interrupt controller is enabled, before
individual interrupts are configured, interrupts can arrive and lead
to the spurious interrupt handler being invoked. Fix thid by
disabling all child interrupts when configuring cAVS interrupt
controllers.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Line break on #error directive is confusing github and ending up
breaking syntax highligthing in github UI which makes me nervous
during review.
Convert error message to a one liner.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Due to clock discrepancy, busy waiting for 15us was not covering for
half tick in certain cases. Busy wait runs from HF clock source.
Increased to 19us to cover it. Anyway, this case is hit very rarely,
only when there was aborted, not-cancelled compare value that was
about to expire. Because of that, increase shall not impact the
performance.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
For historical reasons, the maximum speed of the Atmel SAM USB
controller is done by comparing the maximum-speed property string from
the DT using strncmp at runtime.
Now that the DT_ENUM_IDX macro exists, we can use it to get the
maximum-speed property at build time and without string comparison.
Unsupported speed can also be reported at build time.
Note that the default speed in case the optional maximum-speed property
isn't present in the DT is changed from full-speed to high-speed to
match the property description. This is a no-op in practice as this
properties is defined at the soc level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
CAN_MCP2515_MAX_FILTER is not needed anymore and was probably just a
misunderstanding. Aligned it with the other CAN drivers.
This also was the last difference in the mcp2515 specific config for the
can sample, so that can be deleted as well.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
