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drivers: ethernet: mdio: stm32: move stmmaceth clock to parent

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move stmmaceth clock to parent, so it can also be
used by mdio and rename it to ``stm-eth``.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit is contained in:
Fin Maaß 2025-03-26 11:24:38 +01:00 • committed by Benjamin Cabé
commit 0f636ec2fa
13 changed files with 101 additions and 49 deletions
Download patch file Download diff file Expand all files Collapse all files

6
drivers/ethernet/eth_dwmac_stm32h7x.c
View file

@ -33,8 +33,8 @@ static const struct pinctrl_dev_config *eth0_pcfg =
PINCTRL_DT_INST_DEV_CONFIG_GET(0);
static const struct stm32_pclken pclken = {
.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits),
.bus = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bus),
.enr = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bits),
};
static const struct stm32_pclken pclken_tx = {
.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
@ -81,7 +81,7 @@ int dwmac_bus_init(struct dwmac_priv *p)
reg_val = sys_read32(reg_addr);
sys_write32(reg_val | 0x03800000, reg_addr);
p->base_addr = DT_INST_REG_ADDR(0);
p->base_addr = DT_REG_ADDR(DT_INST_PARENT(0));
return 0;
}

4
drivers/ethernet/eth_stm32_hal.c
View file

@ -1566,8 +1566,8 @@ PINCTRL_DT_INST_DEFINE(0);
static const struct eth_stm32_hal_dev_cfg eth0_config = {
.config_func = eth0_irq_config,
.pclken = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits)},
.pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bus),
.enr = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bits)},
.pclken_tx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits)},
.pclken_rx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bus),

38
drivers/mdio/mdio_stm32_hal.c
View file

@ -9,6 +9,8 @@
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/net/ethernet.h>
@ -28,6 +30,7 @@ struct mdio_stm32_data {
struct mdio_stm32_config {
const struct pinctrl_dev_config *pincfg;
struct stm32_pclken pclken;
};
static int mdio_stm32_read(const struct device *dev, uint8_t prtad,
@ -91,6 +94,14 @@ static int mdio_stm32_init(const struct device *dev)
const struct mdio_stm32_config *const config = dev->config;
int ret;
/* enable clock */
ret = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t)&config->pclken);
if (ret < 0) {
LOG_ERR("Failed to enable ethernet clock needed for MDIO (%d)", ret);
return ret;
}
ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
@ -106,18 +117,19 @@ static DEVICE_API(mdio, mdio_stm32_api) = {
.write = mdio_stm32_write,
};
#define MDIO_STM32_HAL_DEVICE(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static struct mdio_stm32_data mdio_stm32_data_##inst = { \
.heth = {.Instance = (ETH_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(inst))}, \
}; \
static struct mdio_stm32_config mdio_stm32_config_##inst = { \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, &mdio_stm32_init, NULL, \
&mdio_stm32_data_##inst, &mdio_stm32_config_##inst, \
POST_KERNEL, CONFIG_ETH_INIT_PRIORITY, \
&mdio_stm32_api);
#define MDIO_STM32_HAL_DEVICE(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static struct mdio_stm32_data mdio_stm32_data_##inst = { \
.heth = {.Instance = (ETH_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(inst))}, \
}; \
static struct mdio_stm32_config mdio_stm32_config_##inst = { \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(inst), stm_eth, bus), \
.enr = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(inst), stm_eth, bits)}, \
}; \
DEVICE_DT_INST_DEFINE(inst, &mdio_stm32_init, NULL, &mdio_stm32_data_##inst, \
&mdio_stm32_config_##inst, POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
&mdio_stm32_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_STM32_HAL_DEVICE)

9
dts/arm/st/f1/stm32f107.dtsi
View file

@ -21,13 +21,14 @@
ethernet@40028000 {
reg = <0x40028000 0x2000>;
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 14)>;
mac: ethernet {
compatible = "st,stm32-ethernet";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB1, 14)>,
<&rcc STM32_CLOCK(AHB1, 15)>,
clock-names = "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB1, 15)>,
<&rcc STM32_CLOCK(AHB1, 16)>;
status = "disabled";
};

11
dts/arm/st/f2/stm32f207.dtsi
View file

@ -12,13 +12,16 @@
ethernet@40028000 {
reg = <0x40028000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
mac: ethernet {
compatible = "st,stm32-ethernet";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx", "mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>,
<&rcc STM32_CLOCK(AHB1, 26)>,
clock-names = "mac-clk-tx", "mac-clk-rx",
"mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
<&rcc STM32_CLOCK(AHB1, 27)>,
<&rcc STM32_CLOCK(AHB1, 28)>;
status = "disabled";

11
dts/arm/st/f4/stm32f407.dtsi
View file

@ -12,13 +12,16 @@
ethernet@40028000 {
reg = <0x40028000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
mac: ethernet {
compatible = "st,stm32-ethernet";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx", "mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>,
<&rcc STM32_CLOCK(AHB1, 26)>,
clock-names = "mac-clk-tx", "mac-clk-rx",
"mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
<&rcc STM32_CLOCK(AHB1, 27)>,
<&rcc STM32_CLOCK(AHB1, 28)>;
status = "disabled";

11
dts/arm/st/f7/stm32f745.dtsi
View file

@ -77,13 +77,16 @@
ethernet@40028000 {
reg = <0x40028000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
mac: ethernet {
compatible = "st,stm32-ethernet";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx", "mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>,
<&rcc STM32_CLOCK(AHB1, 26)>,
clock-names = "mac-clk-tx", "mac-clk-rx",
"mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
<&rcc STM32_CLOCK(AHB1, 27)>,
<&rcc STM32_CLOCK(AHB1, 28)>;
status = "disabled";

11
dts/arm/st/f7/stm32f765.dtsi
View file

@ -70,13 +70,16 @@
ethernet@40028000 {
reg = <0x40028000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
mac: ethernet {
compatible = "st,stm32-ethernet";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx", "mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 25)>,
<&rcc STM32_CLOCK(AHB1, 26)>,
clock-names = "mac-clk-tx", "mac-clk-rx",
"mac-clk-ptp";
clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
<&rcc STM32_CLOCK(AHB1, 27)>,
<&rcc STM32_CLOCK(AHB1, 28)>;
status = "disabled";

9
dts/arm/st/h5/stm32h5.dtsi
View file

@ -540,12 +540,15 @@
ethernet@40028000 {
reg = <0x40028000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 19)>;
mac: ethernet {
compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
interrupts = <106 0>;
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB1, 19)>,
<&rcc STM32_CLOCK(AHB1, 20)>,
clock-names = "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB1, 20)>,
<&rcc STM32_CLOCK(AHB1, 21)>;
status = "disabled";
};

9
dts/arm/st/h7/stm32h7.dtsi
View file

@ -1027,12 +1027,15 @@
ethernet@40028000 {
reg = <0x40028000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 15)>;
mac: ethernet {
compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB1, 15)>,
<&rcc STM32_CLOCK(AHB1, 16)>,
clock-names = "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB1, 16)>,
<&rcc STM32_CLOCK(AHB1, 17)>;
status = "disabled";
};

10
dts/arm/st/n6/stm32n6.dtsi
View file

@ -645,14 +645,16 @@
ethernet@58036000 {
reg = <0x58036000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB5, 22)>;
mac: ethernet {
compatible = "st,stm32n6-ethernet", "st,stm32h7-ethernet",
"st,stm32-ethernet";
interrupts = <179 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB5, 22)>,
<&rcc STM32_CLOCK(AHB5, 23)>,
clock-names = "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB5, 23)>,
<&rcc STM32_CLOCK(AHB5, 24)>;
status = "disabled";
};

18
dts/bindings/ethernet/st,stm32-ethernet-controller.yaml Normal file
View file

@ -0,0 +1,18 @@
# Copyright The Zephyr Project Contributors
# SPDX-License-Identifier: Apache-2.0
description: |
ST STM32 Ethernet controller, contains the Ethernet MAC
and the MDIO as a child nodes.
compatible: "st,stm32-ethernet-controller"
include: base.yaml
properties:
reg:
required: true
clocks:
required: true
clock-names:
required: true

3
dts/bindings/ethernet/st,stm32-ethernet.yaml
View file

@ -2,7 +2,8 @@
# Copyright (c) 2024, STMicroelectronics
# SPDX-License-Identifier: Apache-2.0
description: ST STM32 Ethernet
description: |
ST STM32 Ethernet MAC, a child node of the Ethernet controller.
compatible: "st,stm32-ethernet"