drivers: clock: Add stm32mp13 clock
Add STM32MP13 clock driver. Supported clocks are HSE, HSI, PLL1 and peripheral clock. Signed-off-by: Julien Racki <julien.racki@st.com> Co-authored-by: Arif Balik <arifbalik@outlook.com>
This commit is contained in:
Julien Racki
Benjamin Cabé
parent
d508ec42e2
commit
c888760663
4 changed files with 204 additions and 1 deletions
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@ -56,6 +56,8 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MCO clock_stm32_mco.c)
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if(CONFIG_SOC_SERIES_STM32MP1X)
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zephyr_library_sources(clock_stm32_ll_mp1.c)
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elseif(CONFIG_SOC_SERIES_STM32MP13X)
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zephyr_library_sources(clock_stm32_ll_mp13.c)
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elseif(CONFIG_SOC_SERIES_STM32H7X)
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zephyr_library_sources(clock_stm32_ll_h7.c)
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elseif(CONFIG_SOC_SERIES_STM32H7RSX)
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@ -9,7 +9,7 @@ menuconfig CLOCK_CONTROL_STM32_CUBE
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depends on SOC_FAMILY_STM32
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default y
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select USE_STM32_LL_UTILS
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select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32H7X || \
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select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32MP13X || SOC_SERIES_STM32H7X || \
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SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || \
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SOC_SERIES_STM32N6X)
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select RUNTIME_NMI if ($(dt_nodelabel_enabled,clk_hse) && \
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199
drivers/clock_control/clock_stm32_ll_mp13.c
Normal file
199
drivers/clock_control/clock_stm32_ll_mp13.c
Normal file
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@ -0,0 +1,199 @@
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_system.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/sys/util.h>
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static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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volatile int temp;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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/* Ensure that the write operation is completed */
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temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
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UNUSED(temp);
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return 0;
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}
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static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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volatile int temp;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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/* Ensure that the write operation is completed */
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temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
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UNUSED(temp);
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system, uint32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_APB1:
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switch (pclken->enr) {
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case LL_APB1_GRP1_PERIPH_UART4:
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*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
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break;
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default:
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return -ENOTSUP;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static const struct clock_control_driver_api stm32_clock_control_api = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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};
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static void set_up_fixed_clock_sources(void)
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{
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if (IS_ENABLED(STM32_HSE_ENABLED)) {
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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/* Wait for HSE ready */
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}
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}
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if (IS_ENABLED(STM32_HSI_ENABLED)) {
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() != 1) {
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/* Enable HSI */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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}
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}
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}
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static int stm32_clock_control_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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set_up_fixed_clock_sources();
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#if STM32_SYSCLK_SRC_HSE
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE);
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while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_HSE) {
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}
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#elif STM32_SYSCLK_SRC_HSI
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSI);
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while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_HSI) {
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}
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#elif STM32_SYSCLK_SRC_PLL
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BUILD_ASSERT(IS_ENABLED(STM32_HSE_ENABLED),
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"STM32MP13 PLL requires HSE to be enabled!");
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/* The default system clock source is HSI, but the bootloader may have switched it. */
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/* Switch back to HSE for clock setup as PLL1 configuration must not be modified */
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/* while active.*/
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE);
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while ((READ_BIT(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) != RCC_MPCKSELR_MPUSRCRDY)) {
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}
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CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) {
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};
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CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) {
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};
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CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) {
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};
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uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n);
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uint32_t pll1_m = DT_PROP(DT_NODELABEL(pll1), div_m);
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uint32_t pll1_p = DT_PROP(DT_NODELABEL(pll1), div_p);
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uint32_t pll1_v = DT_PROP(DT_NODELABEL(pll1), frac_v);
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LL_RCC_PLL1_SetN(pll1_n);
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while (LL_RCC_PLL1_GetN() != pll1_n) {
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}
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LL_RCC_PLL1_SetM(pll1_m);
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while (LL_RCC_PLL1_GetM() != pll1_m) {
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}
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LL_RCC_PLL1_SetP(pll1_p);
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while (LL_RCC_PLL1_GetP() != pll1_p) {
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}
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LL_RCC_PLL1_SetFRACV(pll1_v);
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while (LL_RCC_PLL1_GetFRACV() != pll1_v) {
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}
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LL_RCC_PLL1_Enable();
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while (LL_RCC_PLL1_IsReady() != 1) {
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}
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SET_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
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while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) {
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};
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LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_PLL1);
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while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_PLL1) {
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}
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#endif
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return 0;
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}
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/**
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* @brief RCC device, note that priority is intentionally set to 1 so
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* that the device init runs just after SOC init
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*/
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DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
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stm32_clock_control_init,
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NULL,
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NULL, NULL,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&stm32_clock_control_api);
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@ -53,6 +53,8 @@
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#include <zephyr/dt-bindings/clock/stm32h7_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
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#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
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#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32N6X)
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#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
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#elif defined(CONFIG_SOC_SERIES_STM32U0X)
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