For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add optional user data argument to can_set_state_change_callback() to
comply with Zephyr API design guidelines.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Subghzspi instances cannot have any pinctrl configs,
they are blacklisted by the dts binding. This caused an
initialization failure of the spi_ll_stm32 driver for
subghzspi instance because no "default" pinctrl was found.
This commit solves the problem by skipping the pinctrl setup
for subghzpi devices. The use_subghzpi_nss property is used
to identify a subghzspi device, as this is a required boolean
property only available in the subghzspi binding this is a
perfect indicator for such instances.
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
This commit adds the API of get_config that will make test of
tests/drivers/i2c/i2c_api pass on it8xxx2_evb board.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.
Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
The gd32_exti_isr function may be unused if the GPIO driver is not
enabled but EXTI is (no IRQ will connect to it). This may be improved in
the future by requiring explicit enablement of the exti DT node.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adding these definitions help ease of porting POSIX applications.
They currently do nothing in the core network stack and will
return an error if used. However, they help port some POSIX
without changing these. In particular, this enables using the
Nim programming language's standard library with Zephyr.
- The values copy Linux amd64, similar to the other SO_OPTIONS
- Add SO_SNDBUF to fix simplelink wifi
- Use compat options in simplelink wifi
Signed-off-by: Jaremy J. Creechley <jaremy.creechley@panthalassa.com>
An additional devicetree poperty `single-wire` is added
to uart and usart bindings of stm32. The driver checks this value
during initialization and enables the single wire mode when set.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
Use pm_state_cpu_get_all to obtain CPU states instead of using extra ROM
duplicating existing information already holded by the PM subsystem.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The Event FIFO start address (EFSA) field within the Tx event FIFO
configuration register (TXEFC) occupies bit 15:2.
Change the CAN_MCAN_TXEFC_EFSA_POS definition to reflect this.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Rename a few CAN API functions for clarity and consistency with other
Zephyr RTOS APIs.
CAN_DEFINE_MSGQ() becomes CAN_MSGQ_DEFINE() to match K_MSGQ_DEFINE().
can_attach_isr() becomes can_add_rx_filter() since a filter callback
function is not an interrupt service routine (although it is called in
isr context). The word "attach" is replaced with "add" since filters are
added, not attached. This matches the terminology used is other Zephyr
APIs better.
can_detach() becomes can_remove_rx_filter() to pair with
can_add_rx_filter().
can_attach_msgq() becomes can_add_rx_filter_msgq() and documentation is
updated to mention its relationship with can_add_rx_filter().
can_register_state_change_isr() becomes can_set_state_change_callback()
since a state change callback function is not an interrupt service
routine (although it is called in isr context). The word "register" is
replaced with "set" since only one state change callback can be in
place.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This patch controls the SPI of the stm32H7 mcu when using
the DMA transfer. Starting and ending the transfer
are specific according to the RefMan.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
A generic function is used to give the register address to the DMA.
The SPI of the stm32H7 serie has two data registers for Tx and Rx
When the DMA is getting the address it differs between Rx and Tx.
As the stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_spi.h
has no such LL functions, the register address is get direclty.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The spi_stm32_complete() is checking spi flags which are valid when the
intance is still enable: disable afterwards. No more need to disable
the DMA transfer then
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Defines a function to control the spi busy state during DMA transfer.
After the DMA Tx, the spi might still have some data to Transmit.
The driver must wait for the SPI Tx before sending the next packet.
This is not required for the Rx part as the DMA Rx is already done.
Some mcus like stm32H7 have a TX complete bit, other must wait for the
TXE and BSY line.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Initial version of a PWM driver for GigaDevice GD32 SoCs. Only PWM
output is supported for now (no capture support).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Theoretically, source id check is not mandatory in the context we use
VT-D here (i.e. non VM one, just multi-vector MSI support)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Not sure this is requered as we do not mangle with domains, but let's
make sure this cache is clear.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A surprising issue: while sys_set_bit() on VTD_GCMD_REG work on
apollo_lake, it seems to create border effect on elkhart_lake: it may
reset some previous bit to 0.
So switching to full write of the register at once, which works for
both.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
VT-D will only be enabled if MSI multi-vector will also be requested,
on x86_64, for all boards BUT QEMU ones.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no point to enable VT-D if PCIE MSI multi-vector support is not
requested, as VT-D is uniquely being used to remap MSI multi-vector
based interrupts.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Those MMIO registers might be mapped in RAM and thus it's
really important to keep storage space for such mapping.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
QI operation are not supposed to last forever.
It's not an actual timeout based on clock, but a dummy counter instead.
That's because system clock might not have beed initialized yet, since
VT-D's init comes first (and that same init will use QI...)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Depending on a VT-D capability, it might be necessary to flush objects
from the cache.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Looks like it's mandatory to invalidate the Interrupt Entry Cache in
VT-D and the only way to do so is to enable Queued Interface.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
IR faults are non-recoverable, so it's good to know why. Thus let's
handle the fault event and print the fault.
Other faults are printed as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Looks like a source of fault if pieces of IRTE are written instead of
the whole 64 bits block it belongs to.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If VT-D's interrupt remapping is in place, all IOAPIC RTEs need to get
remapped as well (or then they will be simply blocked).
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adding a way to pre-install the irg/vector on an irte and a way to get
an irte based on irq/vector.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will not only be used by MSI remapping but by all relevant
interrupts.
Fix also IRTE settings:
- handle x2apic for destination id
- destination mode is always logical (as for IOAPIC)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
