Introducing the dma transfer (also through dmamux)
to transfer data to/from the NOR octo-flash
With a DMAMUX, the DMA channel is given by the DTS.
Note that STM32U5X does not support DMA here.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This supports three types GD32 FMC flash memory. GD32 FMC v1,
GD32 FMC v2 and GD32 FMC v3.
GD32 FMC v1 for small flash memory, flash size can be up to 512KB.
GD32 FMC v2 for large flash memory, flash size can be up to 3072KB.
GD32 FMC v3 not use page but sector as minimum block, flash size can
be up to 3072KB.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
According to i.MX RT1060 Reference Manual:
While the OR flag is set, no additional data is stored in the data
buffer even if sufficient room exists. To clear OR, write logic 1 to
the OR flag.
Clear OR (Overrun) flag whenever it is set, so that data continues to be
received after potential data overrun.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Add R-Car Gen3 PWM driver.
Clock diviser is automatically adjusted according to requested period
and duty-cycle in order to obtain as much accuracy as possible.
Indeed, in order to improve PWM accurancy, the PWM clock has to fit
the requested period. So use the given period_cycle to define if the
clock as to be adapted. In such case, increase/decrease the clock
diviser to adapt the period_cycle and be sure that it fits into the
10 bits counter of the PWM controller.
Tested on H3ULCB on pwm0 and pwm4.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
For some stm32 devices, the SDMMC clock selection is HSI 48MHz
by default (reset value). It must be enabled before acccessing
the peripheral.
The ErrorCode is reported when Init fails.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is the adaptation of the stm32 SPI driver with DMA
transfer for the stm32u5 soc.
Use the DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
also valid for the stm32U5 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit implements shell support for 1-Wire.
Commands for bus-reset, bit-, byte-, and block- communication,
as well as search and configuration are implemented.
- write_byte, and write_block perform a reset before,
in case the option "-r" is passed.
- using read_io_options() function to parse the reset option,
as this allows to easily add further options in the future.
- configuration type can be specified either as number or as name.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Introducing RaspberryPi Pico ADC driver.
This driver was created with reference to the adc_emul implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
MCO1 is also available on STM32F1 series (on top of STM32F4), allow
selection of MCO1 source with CLOCK_STM32_MCO1_SRC_* Kconfig parameters.
Available MCO1 sources are slightly different between STM32F4
(LSE, HSE, HSI, PLLCLK) and STM32F103 (HSE, HSI, PLLCLK/2, SYSCLK), and
STM32F105/F107 have a few more (EXT_HSE, PLL2CLK, PLLI2SCLK, PLLI2SCLK/2).
MCO1 on STM32F1 does not have a configurable divider (unlike STM32F4),
HAL call only configures source.
STM32F1 do not have MCO2.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
Use the clock control API to enable peripheral clocks. Note that both
GPIO and pinctrl drivers are updated at once since they share some IP
blocks.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use the clock control API to turn on ADC clocks. Note that clock
selection is not yet implemented, so we still rely on custom rcu
properties for that.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Ticker stop callback are executing in ULL_HIGH priority,
correct the value to 1U instead of 0U which is for LLL
execution context of the Bluetooth Controller.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Fix usage fault due to spurious ticker timeout expiry post
enqueuing of ticker stop operation.
Use ticker operation callback to handle completion of ticker
stop operation and then give the semaphore to thread to
notifying the completion of flash operation.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Due to Zephyr's WiFi updates, common private
enums used in `hal_espressif` are now being used.
This updates private internal values to meet hal_espressif
changes.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
ESP32 wifi connection uses Zephyr's net stack. Once WiFi connects
in station mode, is requires the application to handle DHCPv4
negotiation. This PR adds support to automatic negotiation by
handling the dhcpv4 calls in driver layer.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Moved all MBEDTLS dependencies from prj.conf
to Kconfig as WiFi depends on it.
Update esp32 wifi driver to enable `samples/net/wifi`
to work. Commands as such as `wifi connect` and `wifi scan` are now
available.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Remove the CAN_STM32FD_CLOCK_DIVISOR configuration option,
and add configuration via dts property clk-divider instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The configurable CAN clock divider CAN_STM32FD_CLOCK_DIVISOR
was not applied during initialization, because write protection
was not disabled.
While the clock divider was not applied, it was still used in clock rate
calculation, therefore resulting in incorrect bus speed setup.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use domain clocks if they are defined in dts.
Until now domain clock sources could be selected via kconfig.
STM32 platform now can configure domain clock sources via
clock control driver, therefore this commit makes use of it.
The configuration is shared between canfd instances, so a domain clock
has to be defined for only one instance. Otherwise, only the
configuration from the latest initialized instance will remain.
The dependency on clock source PCLK1 for CAN_STM32FD_CLOCK_DIVISOR
was removed, because the divider also divides other clocks.
Note that setting that divider does not work at all at the moment,
because the write protection is not disabled.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
* reduced cyclomatic complexity
* group validation by family to make the validation easier to understand
and extend
* change preprocessor markup where possible to allow for complete code
elimination when features (esp. IP) are disabled
* renamed net_context_get/set_ip_proto() to net_context_get_proto()
While the latter is formally part of the public API and might therefore
have to be deprecated rather than renamed, it is considered internal API
by the net developers, see
https://github.com/zephyrproject-rtos/zephyr/pull/48751#discussion_r942402612
Signed-off-by: Florian Grandel <jerico.dev@gmail.com>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In case SFDP table is provided via device tree, take care not reading
more than expected by the function caller as the result is written
in a structure which size is predefined by one specific byte in the
table, and could be smaller than the table size.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
soc.h has been removed for ARM64 SoC platforms and it is also needed by
ARM32, so remove it from related drivers.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
soc.h has been removed for ARM64 SoC platforms and it is also needed by
ARM32, so remove it from related drivers.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
soc.h has been removed for ARM64 SoC platforms and it is also needed by
ARM32, so remove it from related drivers.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.
Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
- "cavs_host_ipc" node labels to "adsp_ipc" labels.
- compatible "intel,cavs-host-ipc" renamed to
"intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
- "idc" node labels to "adsp_idc" labels.
- compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
so it is suitable for both CAVS and ACE SoC family.
Moved it from ipm bindings to ipc bindings where it belongs.
Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
status of the "adsp-ipc" and "adsp-ipc" node.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Convert the device to be Devicetree based. Adjusted tests and other
areas that were using old Kconfig properties.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
