drivers/interrupt_controller: Adding QI support in VT-D
Looks like it's mandatory to invalidate the Interrupt Entry Cache in VT-D and the only way to do so is to enable Queued Interface. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Anas Nashif
parent
97c299e0df
commit
2c904b379b
3 changed files with 174 additions and 1 deletions
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@ -26,6 +26,11 @@
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#include "intc_intel_vtd.h"
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static inline void vtd_pause_cpu(void)
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{
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__asm__ volatile("pause" ::: "memory");
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}
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static void vtd_write_reg32(const struct device *dev,
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uint16_t reg, uint32_t value)
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{
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@ -69,6 +74,94 @@ static void vtd_send_cmd(const struct device *dev,
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}
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}
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static void vtd_qi_init(const struct device *dev)
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{
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struct vtd_ictl_data *data = dev->data;
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uint64_t value;
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vtd_write_reg64(dev, VTD_IQT_REG, 0);
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data->qi_tail = 0;
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value = VTD_IQA_REG_GEN_CONTENT((uintptr_t)data->qi,
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VTD_IQA_WIDTH_128_BIT, QI_SIZE);
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vtd_write_reg64(dev, VTD_IQA_REG, value);
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vtd_send_cmd(dev, VTD_GCMD_QIE, VTD_GSTS_QIES);
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}
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static inline void vtd_qi_tail_inc(const struct device *dev)
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{
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struct vtd_ictl_data *data = dev->data;
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data->qi_tail += sizeof(struct qi_descriptor);
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data->qi_tail %= (QI_NUM * sizeof(struct qi_descriptor));
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}
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static int vtd_qi_send(const struct device *dev,
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struct qi_descriptor *descriptor)
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{
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struct vtd_ictl_data *data = dev->data;
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union qi_wait_descriptor wait_desc = { 0 };
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struct qi_descriptor *desc;
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uint32_t wait_status;
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desc = (struct qi_descriptor *)((uintptr_t)data->qi + data->qi_tail);
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desc->low = descriptor->low;
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desc->high = descriptor->high;
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vtd_qi_tail_inc(dev);
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desc++;
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wait_status = QI_WAIT_STATUS_INCOMPLETE;
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wait_desc.wait.type = QI_TYPE_WAIT;
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wait_desc.wait.status_write = 1;
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wait_desc.wait.status_data = QI_WAIT_STATUS_COMPLETE;
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wait_desc.wait.address = ((uintptr_t)&wait_status) >> 2;
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desc->low = wait_desc.desc.low;
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desc->high = wait_desc.desc.high;
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vtd_qi_tail_inc(dev);
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vtd_write_reg64(dev, VTD_IQT_REG, data->qi_tail);
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while (wait_status != QI_WAIT_STATUS_COMPLETE) {
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if (vtd_read_reg32(dev, VTD_FSTS_REG) & VTD_FSTS_IQE) {
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return -EIO;
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}
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vtd_pause_cpu();
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}
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return 0;
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}
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static int vtd_global_iec_invalidate(const struct device *dev)
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{
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union qi_iec_descriptor iec_desc = { 0 };
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iec_desc.iec.type = QI_TYPE_IEC;
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iec_desc.iec.granularity = 0; /* Global Invalidation requested */
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return vtd_qi_send(dev, &iec_desc.desc);
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}
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static int vtd_index_iec_invalidate(const struct device *dev, uint8_t irte_idx)
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{
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union qi_iec_descriptor iec_desc = { 0 };
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iec_desc.iec.type = QI_TYPE_IEC;
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iec_desc.iec.granularity = 1; /* Index based invalidation requested */
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iec_desc.iec.interrupt_index = irte_idx;
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iec_desc.iec.index_mask = 0;
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return vtd_qi_send(dev, &iec_desc.desc);
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}
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static void fault_status_description(uint32_t status)
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{
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if (status & VTD_FSTS_PFO) {
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@ -233,6 +326,8 @@ static int vtd_ictl_remap(const struct device *dev,
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data->irte[irte_idx].low = irte.low;
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data->irte[irte_idx].high = irte.high;
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vtd_index_iec_invalidate(dev, irte_idx);
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return 0;
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}
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@ -318,11 +413,14 @@ static int vtd_ictl_init(const struct device *dev)
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unsigned int key = irq_lock();
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uint64_t eime = 0;
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uint64_t value;
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int ret = 0;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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vtd_fault_event_init(dev);
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vtd_qi_init(dev);
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if (IS_ENABLED(CONFIG_X2APIC)) {
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eime = VTD_IRTA_EIME;
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}
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@ -332,6 +430,12 @@ static int vtd_ictl_init(const struct device *dev)
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vtd_write_reg64(dev, VTD_IRTA_REG, value);
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if (vtd_global_iec_invalidate(dev) != 0) {
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printk("Could not perform IEC invalidation\n");
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ret = -EIO;
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goto out;
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}
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if (!IS_ENABLED(CONFIG_X2APIC) &&
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IS_ENABLED(CONFIG_INTEL_VTD_ICTL_XAPIC_PASSTHROUGH)) {
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vtd_send_cmd(dev, VTD_GCMD_CFI, VTD_GSTS_CFIS);
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@ -343,9 +447,10 @@ static int vtd_ictl_init(const struct device *dev)
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printk("Intel VT-D up and running (status 0x%x)\n",
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vtd_read_reg32(dev, VTD_GSTS_REG));
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out:
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irq_unlock(key);
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return 0;
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return ret;
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}
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static const struct vtd_driver_api vtd_api = {
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@ -52,8 +52,59 @@ struct vtd_irte {
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#define IRTE_NUM 256
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#define IRTA_SIZE 7 /* size = 2^(X+1) where IRTA_SIZE is X 2^8 = 256 */
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#define QI_NUM 256 /* Which is the minimal number we can set for the queue */
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#define QI_SIZE 0 /* size = 2^(X+8) where QI_SIZE is X: 2^8 = 256 */
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#define QI_WIDTH 128
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struct qi_descriptor {
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uint64_t low;
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uint64_t high;
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};
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#define QI_TYPE_IEC 0x4UL
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union qi_iec_descriptor {
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struct qi_descriptor desc;
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struct iec_bits {
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uint64_t type : 4;
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uint64_t granularity : 1;
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uint64_t _reserved_0 : 4;
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uint64_t zero : 3;
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uint64_t _reserved_1 : 15;
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uint64_t index_mask : 5;
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uint64_t interrupt_index: 16;
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uint64_t _reserved_2 : 16;
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uint64_t reserved;
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} iec __packed;
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};
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#define QI_TYPE_WAIT 0x5UL
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union qi_wait_descriptor {
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struct qi_descriptor desc;
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struct wait_bits {
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uint64_t type : 4;
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uint64_t interrupt_flag : 1;
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uint64_t status_write : 1;
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uint64_t fence_flag : 1;
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uint64_t page_req_drain : 1;
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uint64_t _reserved_0 : 1;
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uint64_t zero : 3;
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uint64_t _reserved_1 : 20;
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uint64_t status_data : 32;
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uint64_t reserved : 2;
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uint64_t address : 62;
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} wait __packed;
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};
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#define QI_WAIT_STATUS_INCOMPLETE 0x0UL
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#define QI_WAIT_STATUS_COMPLETE 0x1UL
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struct vtd_ictl_data {
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struct vtd_irte irte[IRTE_NUM];
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struct qi_descriptor qi[QI_NUM] __aligned(0x1000);
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int irqs[IRTE_NUM];
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int vectors[IRTE_NUM];
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bool msi[IRTE_NUM];
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@ -61,6 +112,7 @@ struct vtd_ictl_data {
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unsigned int fault_irq;
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uintptr_t fault_record_reg;
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uint16_t fault_record_num;
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uint16_t qi_tail;
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uint8_t fault_vector;
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};
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@ -140,6 +140,7 @@
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#define VTD_FSTS_IQE BIT(4)
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#define VTD_FSTS_ICE BIT(5)
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#define VTD_FSTS_ITE BIT(6)
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#define VTD_FSTS_FRI_POS 8
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#define VTD_FSTS_FRI_MASK (0xF << VTD_FSTS_FRI_POS)
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#define VTD_FSTS_FRI(status) \
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@ -182,6 +183,21 @@
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#define VTD_FRCD_FI_IR(fault) \
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((fault & VTD_FRCD_FI_IR_MASK) >> VTD_FRCD_FI_IR_POS)
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/* Invalidation Queue Address register details */
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#define VTD_IQA_SIZE_MASK 0x7
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#define VTD_IQA_WIDTH_128_BIT 0
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#define VTD_IQA_WIDTH_256_BIT BIT(11)
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#define VTD_IQA_REG_GEN_CONTENT(addr, width, size) \
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((uint64_t)0 | (addr) | (width) | (size & VTD_IQA_SIZE_MASK))
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/* Invalidation Queue Head register details */
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#define VTD_IQH_QH_POS_128 4
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#define VTD_IQH_QH_MASK ((uint64_t)0xEF << VTD_IQH_QH_POS_128)
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/* Invalidation Queue Tail register details */
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#define VTD_IQT_QT_POS_128 4
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#define VTD_IQT_QT_MASK ((uint64_t)0xEF << VTD_IQT_QT_POS_128)
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H */
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