drivers/interrupt_controller: Add fault event support on Intel VT-D
IR faults are non-recoverable, so it's good to know why. Thus let's handle the fault event and print the fault. Other faults are printed as well. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Anas Nashif
parent
a8c8abd27e
commit
640e651cd8
4 changed files with 214 additions and 7 deletions
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@ -28,3 +28,7 @@ zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3 intc_esp32c3.c)
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zephyr_library_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c)
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zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
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zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.c)
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if(CONFIG_INTEL_VTD_ICTL)
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zephyr_library_include_directories(${ZEPHYR_BASE}/arch/x86/include)
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endif()
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@ -20,9 +20,27 @@
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#include <arch/x86/intel_vtd.h>
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#include <drivers/interrupt_controller/intel_vtd.h>
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#include <drivers/interrupt_controller/ioapic.h>
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#include <drivers/pcie/msi.h>
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#include <kernel_arch_func.h>
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#include "intc_intel_vtd.h"
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static void vtd_write_reg32(const struct device *dev,
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uint16_t reg, uint32_t value)
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{
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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sys_write32(value, (base_address + reg));
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}
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static uint32_t vtd_read_reg(const struct device *dev, uint16_t reg)
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{
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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return sys_read32(base_address + reg);
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}
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static void vtd_write_reg64(const struct device *dev,
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uint16_t reg, uint64_t value)
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{
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@ -31,11 +49,11 @@ static void vtd_write_reg64(const struct device *dev,
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sys_write64(value, (base_address + reg));
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}
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static uint32_t vtd_read_reg(const struct device *dev, uint16_t reg)
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static uint64_t vtd_read_reg64(const struct device *dev, uint16_t reg)
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{
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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return sys_read32(base_address + reg);
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return sys_read64(base_address + reg);
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}
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static void vtd_send_cmd(const struct device *dev,
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@ -51,6 +69,120 @@ static void vtd_send_cmd(const struct device *dev,
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}
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}
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static void fault_status_description(uint32_t status)
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{
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if (status & VTD_FSTS_PFO) {
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printk("Primary Fault Overflow (PFO)\n");
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}
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if (status & VTD_FSTS_AFO) {
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printk("Advanced Fault Overflow (AFO)\n");
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}
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if (status & VTD_FSTS_APF) {
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printk("Advanced Primary Fault (APF)\n");
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}
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if (status & VTD_FSTS_IQE) {
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printk("Invalidation Queue Error (IQE)\n");
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}
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if (status & VTD_FSTS_ICE) {
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printk("Invalidation Completion Error (ICE)\n");
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}
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if (status & VTD_FSTS_ITE) {
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printk("Invalidation Timeout Error\n");
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}
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if (status & VTD_FSTS_PPF) {
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printk("Primary Pending Fault (PPF) %u\n",
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VTD_FSTS_FRI(status));
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}
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}
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static void fault_record_description(uint64_t low, uint64_t high)
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{
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printk("Fault %s request: Reason 0x%x info 0x%llx src 0x%x\n",
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(high & VTD_FRCD_T) ? "Read/Atomic" : "Write/Page",
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VTD_FRCD_FR(high), VTD_FRCD_FI(low), VTD_FRCD_SID(high));
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}
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static void fault_event_isr(const void *arg)
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{
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const struct device *dev = arg;
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struct vtd_ictl_data *data = dev->data;
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uint32_t status;
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uint8_t f_idx;
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status = vtd_read_reg(dev, VTD_FSTS_REG);
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fault_status_description(status);
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if (!(status & VTD_FSTS_PPF)) {
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goto out;
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}
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f_idx = VTD_FSTS_FRI(status);
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while (f_idx < data->fault_record_num) {
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uint64_t fault_l, fault_h;
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/* Reading fault's 64 lowest bits */
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fault_l = vtd_read_reg64(dev, data->fault_record_reg +
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(VTD_FRCD_REG_SIZE * f_idx));
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/* Reading fault's 64 highest bits */
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fault_h = vtd_read_reg64(dev, data->fault_record_reg +
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(VTD_FRCD_REG_SIZE * f_idx) + 8);
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if (fault_h & VTD_FRCD_F) {
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fault_record_description(fault_l, fault_h);
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}
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/* Clearing the fault */
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vtd_write_reg64(dev, data->fault_record_reg +
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(VTD_FRCD_REG_SIZE * f_idx), fault_l);
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vtd_write_reg64(dev, data->fault_record_reg +
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(VTD_FRCD_REG_SIZE * f_idx) + 8, fault_h);
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f_idx++;
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}
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out:
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/* Clearing fault status */
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vtd_write_reg32(dev, VTD_FSTS_REG, VTD_FSTS_CLEAR(status));
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}
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static void vtd_fault_event_init(const struct device *dev)
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{
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struct vtd_ictl_data *data = dev->data;
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uint64_t value;
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uint32_t reg;
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value = vtd_read_reg64(dev, VTD_CAP_REG);
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data->fault_record_num = VTD_CAP_NFR(value) + 1;
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data->fault_record_reg = DEVICE_MMIO_GET(dev) +
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(uintptr_t)(16 * VTD_CAP_FRO(value));
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/* Allocating IRQ & vector and connecting the ISR handler,
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* by-passing remapping by using x86 functions directly.
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*/
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data->fault_irq = arch_irq_allocate();
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data->fault_vector = z_x86_allocate_vector(0, -1);
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vtd_write_reg32(dev, VTD_FEDATA_REG, data->fault_vector);
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vtd_write_reg32(dev, VTD_FEADDR_REG,
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pcie_msi_map(data->fault_irq, NULL, 0));
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vtd_write_reg32(dev, VTD_FEUADDR_REG, 0);
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z_x86_irq_connect_on_vector(data->fault_irq, data->fault_vector,
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fault_event_isr, dev);
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vtd_write_reg32(dev, VTD_FSTS_REG,
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VTD_FSTS_CLEAR(vtd_read_reg32(dev, VTD_FSTS_REG)));
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/* Unmasking interrupts */
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reg = vtd_read_reg32(dev, VTD_FECTL_REG);
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reg &= ~BIT(VTD_FECTL_REG_IM);
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vtd_write_reg32(dev, VTD_FECTL_REG, reg);
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}
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static int vtd_ictl_allocate_entries(const struct device *dev,
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uint8_t n_entries)
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{
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@ -185,18 +317,20 @@ static int vtd_ictl_init(const struct device *dev)
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struct vtd_ictl_data *data = dev->data;
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unsigned int key = irq_lock();
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uint64_t eime = 0;
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uint64_t irta;
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uint64_t value;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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vtd_fault_event_init(dev);
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if (IS_ENABLED(CONFIG_X2APIC)) {
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eime = VTD_IRTA_EIME;
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}
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irta = VTD_IRTA_REG_GEN_CONTENT((uintptr_t)data->irte,
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IRTA_SIZE, eime);
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value = VTD_IRTA_REG_GEN_CONTENT((uintptr_t)data->irte,
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IRTA_SIZE, eime);
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vtd_write_reg64(dev, VTD_IRTA_REG, irta);
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vtd_write_reg64(dev, VTD_IRTA_REG, value);
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if (!IS_ENABLED(CONFIG_X2APIC) &&
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IS_ENABLED(CONFIG_INTEL_VTD_ICTL_XAPIC_PASSTHROUGH)) {
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@ -58,6 +58,10 @@ struct vtd_ictl_data {
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int vectors[IRTE_NUM];
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bool msi[IRTE_NUM];
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int irte_num_used;
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unsigned int fault_irq;
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uintptr_t fault_record_reg;
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uint16_t fault_record_num;
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uint8_t fault_vector;
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};
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struct vtd_ictl_cfg {
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@ -20,7 +20,7 @@
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#define VTD_RTADDR_REG 0x020 /* Root Table Address */
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#define VTD_CCMD_REG 0x028 /* Context Command */
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#define VTD_FSTS_REG 0x034 /* Fault Status */
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#define VTD_FECTL_REG 0x038 /* Fault Event Control Register*/
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#define VTD_FECTL_REG 0x038 /* Fault Event Control */
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#define VTD_FEDATA_REG 0x03C /* Fault Event Data */
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#define VTD_FEADDR_REG 0x040 /* Fault Event Address */
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#define VTD_FEUADDR_REG 0x044 /* Fault Event Upper Address */
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@ -85,6 +85,17 @@
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#define VTD_VCMD 0xE10 /* Virtual Command */
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#define VTD_VCRSP 0xE20 /* Virtual Command Response */
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/* Capability Register details */
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#define VTD_CAP_NFR_POS 40
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#define VTD_CAP_NFR_MASK ((uint64_t)0xFFUL << VTD_CAP_NFR_POS)
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#define VTD_CAP_NFR(cap) \
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(((uint64_t)cap & VTD_CAP_NFR_MASK) >> VTD_CAP_NFR_POS)
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#define VTD_CAP_FRO_POS 24
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#define VTD_CAP_FRO_MASK ((uint64_t)0x3FFUL << VTD_CAP_FRO_POS)
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#define VTD_CAP_FRO(cap) \
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(((uint64_t)cap & VTD_CAP_FRO_MASK) >> VTD_CAP_FRO_POS)
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/* Global Command Register details */
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#define VTD_GCMD_CFI 23
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#define VTD_GCMD_SIRTP 24
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@ -117,6 +128,60 @@
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(addr << VTD_IRTA_ADDR_SHIFT) | \
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(mode) | (size & VTD_IRTA_SIZE_MASK))
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/* Fault event control register details */
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#define VTD_FECTL_REG_IP 30
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#define VTD_FECTL_REG_IM 31
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/* Fault event status register details */
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#define VTD_FSTS_PFO BIT(0)
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#define VTD_FSTS_PPF BIT(1)
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#define VTD_FSTS_AFO BIT(2)
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#define VTD_FSTS_APF BIT(3)
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#define VTD_FSTS_IQE BIT(4)
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#define VTD_FSTS_ICE BIT(5)
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#define VTD_FSTS_ITE BIT(6)
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#define VTD_FSTS_FRI_POS 8
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#define VTD_FSTS_FRI_MASK (0xF << VTD_FSTS_FRI_POS)
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#define VTD_FSTS_FRI(status) \
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((status & VTD_FSTS_FRI_MASK) >> VTD_FSTS_FRI_POS)
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#define VTD_FSTS_CLEAR_STATUS \
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(VTD_FSTS_PFO | VTD_FSTS_AFO | VTD_FSTS_APF | \
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VTD_FSTS_IQE | VTD_FSTS_ICE | VTD_FSTS_ITE)
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#define VTD_FSTS_CLEAR(status) \
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(status & VTD_FSTS_CLEAR_STATUS)
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/* Fault recording register(s) details
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* Note: parts of the register are split into highest and lowest 64bits
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* so bit positions are depending on it and are not based on 128bits reg.
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*/
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#define VTD_FRCD_REG_SIZE 16
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/* Highest 64bits info */
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#define VTD_FRCD_F BIT(63)
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#define VTD_FRCD_T BIT(62)
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#define VTD_FRCD_FR_POS 32
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#define VTD_FRCD_FR_MASK ((uint64_t)0xFF << VTD_FRCD_FR_POS)
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#define VTD_FRCD_FR(fault) \
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((uint8_t)((fault & VTD_FRCD_FR_MASK) >> VTD_FRCD_FR_POS))
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#define VTD_FRCD_SID_MASK 0xFFFF
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#define VTD_FRCD_SID(fault) \
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((uint16_t)(fault & VTD_FRCD_SID_MASK))
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/* Lowest 64bits info */
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#define VTD_FRCD_FI_POS 12
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#define VTD_FRCD_FI_MASK ((uint64_t)0xFFFFFFFFFFFFF << VTD_FRCD_FI_POS)
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#define VTD_FRCD_FI(fault) \
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((fault & VTD_FRCD_FI_MASK) >> VTD_FRCD_FI_POS)
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#define VTD_FRCD_FI_IR_POS 48
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#define VTD_FRCD_FI_IR_MASK ((uint64_t)0xFFFF << VTD_FRCD_FI_IR_POS)
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#define VTD_FRCD_FI_IR(fault) \
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((fault & VTD_FRCD_FI_IR_MASK) >> VTD_FRCD_FI_IR_POS)
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H */
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