IMR and ISR bits are same, but it stil better to differentiate them
properly. Also fixing naming where all ISR ends with an 'S'.
Change-Id: I2fc1e1d8d2743c3d98f5da40a5f4720a85c4f9a7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On ARC, the SPI IP block might be accessible only via user extended
auxiliary registers, which requires different instructions to read from
and write to.
Change-Id: I3aa5f223938a9aed7795de4aedc64bd529d62942
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Registers offsets are hopefully all the same, but size differs.
On x86, thus 32bits support, CTRL0 or DR for instance are 32 bits r/w.
And DFS on 32 bits support is placed differently as well.
Change-Id: I5115d5c3c9bba71ece4a6f4a1d3d2fdc203c8da1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Only 8 bit frames were supported. Added support for bigger data frames
which can go up to 32 bits (on 32bits version of the controller, 16 bits
otherwise). Store the frame size in bytes during configure, and use it
during pull/push to read/write correct frame size.
Change-Id: Iae8c55442e0a205403aa3febd1811b36aaf4c5b6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If SPI_INTEL is not requested, no need to instanciate specific value.
Change-Id: I5f41d919e258e420f2bd099db88ed2259f9cd27e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Introduced by commit 01d6f9f5ee0867f6ee8dc1506c2ebe62d9f296bb
Reported by Gustavo Lima Chaves
Change-Id: Ic29c33f4339c83a55ca45e93000cbc07b8dadbd2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Introduced by commit a6873a00d816daf303b0380dda91accd28df6497
Reordering the irq config function, and removing useless parameter.
Change-Id: I2d22cfe81153b104044d8672dd57115138437ed9
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The driver has to implement the logic in an interrupt based manner.
Applying the changes to the existing drivers.
Changing ADC's API and implementation as well to follow those changes.
Change-Id: Ie0c3e3e318f619ade6be935adb064a25446cc29c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rename class in pci_dev_info struct to allow to use C++ compilers.
Updated drivers to use new struct.
Change-Id: I17b94cb7bc094bccd615c8389a28589bfa90cab8
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Use a default priority to avoid Kconfig blocking when priority
is not set in SoC or Board.
Change-Id: I4edda47b955a7ee834f04dc40d0decbd8dee6305
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: I89090181acb5f48dd797e7773ab65c5f3d46c42a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.
Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Put initialization priorities as device driver Kconfig
parameter.
Initialization priority value for each platform is defined
in the platform Kconfig file.
Drivers and platform code use SYS_DEFINE_DEVICE to add
and initialization function.
Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
- Build the actual driver when relevant
- Provide the IOAPIC stub
- Provide the IRQ flags for IRQ_CONNECT_STATIC
- Set the default IRQ priorities
Change-Id: Iea20ef67c92cf7f48791fba5a8021448b7059950
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such controller is found on Quark SE Lakemont and ARC cores. This
driver currently supports the Lakemont core (x86).
Change-Id: Iefebd6ce9dbe81aa3902e7c2d801b07c027c548a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.
The change in API means that device drivers and sample
applications need to use the new API.
IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()
Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
- ROR interrupt needs to be acked by resetting the bit to 0
- Rx threshold seems buggy on that controller and setting it above 1
generates unreliable transmission as sometimes it does not trigger any
interrupt though the rx fifo is just full.
Change-Id: I4949c1fe7b42c70973efd4e0dafd14c6171f13f6
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
SPI port 1 needs the pinmuxer to be initialized first. Or then, all
modifications required from the CS GPIO logic won't apply.
Change-Id: Ibe4b2d4096065a9add23373075090d5e8a014650
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As for the SPI port 0, SPI port 1 needs a GPIO pin to emulate the CS.
Change-Id: I00911cd25c3fa0ae17a02ee6f43cbea7f4fbcca2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Obviously it's '&' and not '&&'.
Change-Id: I9bb9fee80a67697e8ea62bb001af1b72f5a356e6
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convering the intel_spi to use the updated device model
Change-Id: I016822aeecaf707ffa31b57b4e51e99262fce0e5
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Changes the default IRQ priority level from 0 to 2 for the following
kernel configuration options as priorities 0 and 1 are reserved for the
first 32 IDT entries.
SHARED_IRQ_0_PRI
SHARED_IRQ_1_PRI
I2C_DW_0_INT_PRIORITY
GPIO_DW_0_PRI
GPIO_DW_1_PRI
SPI_INTEL_PORT_0_PRI
SPI_INTEL_PORT_1_PRI
Change-Id: I0fc821c68156eb1e1fe776b2bd4ff5890bba40e8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Change-Id: I2276676142deea21cf8079449ce153f2fb887a8e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to have drivers that are usable cross architecture the
signature for IRQ_CONFIG needs to be the same to avoid #ifdef hell in
the driver code based on architecture.
Update the macro and it usage for existing drivers
Change-Id: I22e142b21d4e984add231d1dbd97020e4823985f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Gets rid of the trailing initialization level character from the
name of the device variable generated by the macro, since it serves
no useful purpose. (The linker scripts place the various initialization
sections in ascending order based on the name of the section, so there
is no need to embed the initialization level in the variable name itself.)
Change-Id: I56bb79a513b8f77fb1f3fbaccec14454c2520772
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
GPIO driver is initialized at pre-kernel-late level, if SPI does it too,
it will happen before GPIO (depends on the ordered list of
initialization). In order to ensure it gets GPIO initialized always
before SPI, let's set SPI to initalize at the next level: nano-early.
Change-Id: I6e34168c88fca0187a809bf5c7971492bd5acb5c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
It might be needed sometime to get some private data forwarded to the
callback, thus such user_data pointer is the easiest way to proceed.
Adding a macro to set the word size as well.
Change-Id: I68cbe2d480120253ccb13f13c656a38c27e21604
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If those are not set it means the controller has nothing to request
anymore from the driver.
Change-Id: Ie7e834e82b931e4b02ded3f9f619735b31b0a121
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Since the driver is the only one needing those, no need to expose them
anywhere.
Change-Id: Iac4eaa65a9dbdaa8e72c70ea0de35cd2b3d836d1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
At this points the slave is ready to deal with the master.
Change-Id: I815d3c577bd0b73100cbf585cc8ca78f180ec713
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This was failing, the documentationg provides numbers only telling at
one places these are hexadecimal values. So switching to hexadecimal.
Then DDS rate retrieving macro was bogus, so fixing it.
And adding debug output about the DDS rate and the clock ratio.
Change-Id: I9cc414796fbd7f7123f1f406c6bce7ffacf641e8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Providing the right settings through Galileo's Kconfig.
Change-Id: Ia5339eb90cb98d7dde3be0493bcfd9a6b6db60ed
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add Kconfig option to specify how interrupt is triggered for SPI.
Also enabling such support for Galileo platform.
Change-Id: Id3112d100089197940f826b827493174d0f22669
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is specific to Galileo board where its SPI port 0 needs to setup
the CS pin through a GPIO pin.
Change-Id: I9df6f7144a96bcd10f61fc7d057f89caa0e599d1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.
Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This macro is legacy from an early implementation of the init system
before the pure level was split into early and late phases remove it
now to avoid confusion going forward.
Change-Id: I6720874c840c9e14888fd6f411a8182e7420ca29
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
The code fragment to bind the instances of the SPI driveri is not
platform specific but is driver specific.
All the information required to bind a driver instance comes from
CONFIG_ variables. Having the binding code with the driver code
avoids duplicating the code fragments in each platform where the
driver may be used.
Change-Id: Iff40227e3e25d431ae870d585445971f35d934dd
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Or then the controller will spin around requesting to get its fifo
filled-in though it's unnecessary.
Change-Id: I81e7c483345236dee7691c3e780b1b06d6b2d0f8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Handle the new error callback type, a ROR interrupt is irrecoverable.
- Removing the fifo pre-fill: this should never be done that way. It's
up to the controller to request via an interrupt to get its fifo
filled-in. (TFS bit on SSSR register is the one requesting such
filling)
- Disabling the controller once completed (following transfer will
re-enable it)
- Removing useless debugging info
Change-Id: I466a8efb65a41f3315a6a36e10ea519d0c4b01e9
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without it, it won't go through a pci scan, and will just trust the
pre-set information for the bus/dev/function to enable the memory
mapped registers.
Change-Id: Ica9156be541619dce9684dd45f70e05b69782a7c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will make code that use it not too crowded with #ifdef #endif
Change-Id: Iec0fa662445b1cefdc7c64d9483e1ae483106a90
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such controllers are found in Quark's X1000 series, and thus are found
on Galileo boards v1 and v2.
Change-Id: Ib71486c9f27de1b6c48ce3cb3dd138d69833c2ea
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
