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drivers: Add 'U' to unsigned variable assignments

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Add 'U' to a value when assigning it to an unsigned variable.
MISRA-C rule 7.2

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
This commit is contained in:
Patrik Flykt 2018-11-29 11:12:22 -08:00 • committed by Anas Nashif
commit 8ff96b5a57
172 changed files with 693 additions and 693 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/adc/adc_context.h
View file

@ -185,7 +185,7 @@ static inline void adc_context_start_read(struct adc_context *ctx,
ctx->status = 0;
if (ctx->sequence->options) {
ctx->sampling_index = 0;
ctx->sampling_index = 0U;
if (ctx->sequence->options->interval_us != 0) {
atomic_set(&ctx->sampling_requested, 0);

4
drivers/adc/adc_dw.c
View file

@ -294,7 +294,7 @@ static int adc_dw_read_request(struct device *dev,
if (seq_tbl->options) {
info->seq_size = seq_tbl->options->extra_samplings + 1;
} else {
info->seq_size = 1;
info->seq_size = 1U;
}
info->state = ADC_STATE_SAMPLING;
@ -342,7 +342,7 @@ static void adc_dw_start_conversion(struct device *dev)
const struct adc_config *config = info->dev->config->config_info;
const struct adc_sequence *entry = info->ctx.sequence;
u32_t adc_base = config->reg_base;
u32_t ctrl, tmp_val, interval_us = 0;
u32_t ctrl, tmp_val, interval_us = 0U;
info->channel_id = find_lsb_set(info->channels) - 1;

10
drivers/adc/adc_intel_quark_d2000.c
View file

@ -267,7 +267,7 @@ static int adc_quark_d2000_read_request(struct device *dev,
if (seq_tbl->options) {
info->seq_size = seq_tbl->options->extra_samplings + 1;
} else {
info->seq_size = 1;
info->seq_size = 1U;
}
if (info->seq_size > ADC_FIFO_LEN) {
@ -276,7 +276,7 @@ static int adc_quark_d2000_read_request(struct device *dev,
/* check if buffer has enough size */
utmp = info->channels;
num_channels = 0;
num_channels = 0U;
while (utmp) {
if (utmp & BIT(0)) {
num_channels++;
@ -325,8 +325,8 @@ static void adc_quark_d2000_start_conversion(struct device *dev)
info->dev->config->config_info;
const struct adc_sequence *entry = info->ctx.sequence;
volatile adc_reg_t *adc_regs = config->reg_base;
u32_t i, val, interval_us = 0;
u32_t idx = 0, offset = 0;
u32_t i, val, interval_us = 0U;
u32_t idx = 0U, offset = 0U;
info->channel_id = find_lsb_set(info->channels) - 1;
@ -338,7 +338,7 @@ static void adc_quark_d2000_start_conversion(struct device *dev)
adc_regs->sample = ADC_FIFO_CLEAR;
/* setup the sequence table */
for (i = 0; i < info->seq_size; i++) {
for (i = 0U; i < info->seq_size; i++) {
idx = i / 4;
offset = (i % 4) * 8;

4
drivers/adc/adc_mcux_adc16.c
View file

@ -133,7 +133,7 @@ static void mcux_adc16_start_channel(struct device *dev)
struct mcux_adc16_data *data = dev->driver_data;
adc16_channel_config_t channel_config;
u32_t channel_group = 0;
u32_t channel_group = 0U;
data->channel_id = find_lsb_set(data->channels) - 1;
@ -174,7 +174,7 @@ static void mcux_adc16_isr(void *arg)
const struct mcux_adc16_config *config = dev->config->config_info;
struct mcux_adc16_data *data = dev->driver_data;
ADC_Type *base = config->base;
u32_t channel_group = 0;
u32_t channel_group = 0U;
u16_t result;
result = ADC16_GetChannelConversionValue(base, channel_group);

4
drivers/adc/adc_nrfx_adc.c
View file

@ -173,12 +173,12 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence)
return -EINVAL;
}
active_channels = 0;
active_channels = 0U;
nrfx_adc_all_channels_disable();
/* Enable the channels selected for the pointed sequence.
*/
channel_id = 0;
channel_id = 0U;
while (selected_channels) {
if (selected_channels & BIT(0)) {
/* The nrfx driver requires setting the resolution

4
drivers/adc/adc_nrfx_saadc.c
View file

@ -261,12 +261,12 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence)
return -EINVAL;
}
active_channels = 0;
active_channels = 0U;
/* Enable only the channels selected for the pointed sequence.
* Disable all the rest.
*/
channel_id = 0;
channel_id = 0U;
do {
if (selected_channels & BIT(channel_id)) {
/* Signal an error if a selected channel has not been

6
drivers/adc/adc_sam_afec.c
View file

@ -187,7 +187,7 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence)
int error = 0;
u32_t channels = sequence->channels;
data->channels = 0;
data->channels = 0U;
/* Signal an error if the channel selection is invalid (no channels or
* a non-existing one is selected).
@ -212,8 +212,8 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence)
return -EINVAL;
}
u8_t num_active_channels = 0;
u8_t channel = 0;
u8_t num_active_channels = 0U;
u8_t channel = 0U;
while (channels > 0) {
if (channels & 1) {

4
drivers/aio/aio_comparator_qmsi.c
View file

@ -142,7 +142,7 @@ static int aio_qmsi_cmp_init(struct device *dev)
config.cmp_en = QM_SCSS_CMP->cmp_en;
/* Clear callback pointers */
for (i = 0; i < dev_data->num_cmp; i++) {
for (i = 0U; i < dev_data->num_cmp; i++) {
dev_data->cb[i].cb = NULL;
dev_data->cb[i].param = NULL;
}
@ -161,7 +161,7 @@ static void aio_qmsi_cmp_isr(void *data)
u32_t int_status = QM_SCSS_CMP->cmp_stat_clr;
for (i = 0; i < dev_data->num_cmp; i++) {
for (i = 0U; i < dev_data->num_cmp; i++) {
if (int_status & (1 << i)) {
if (dev_data->cb[i].cb != NULL) {
dev_data->cb[i].cb(dev_data->cb[i].param);

12
drivers/audio/intel_dmic.c
View file

@ -652,14 +652,14 @@ static int source_ipm_helper(struct pdm_chan_cfg *config, u32_t *source_mask,
u8_t pdm_ix;
u8_t chan_ix;
enum pdm_lr lr;
u16_t pdm_lr_mask = 0;
u16_t pdm_lr_mask = 0U;
int ipm = 0;
/* clear outputs */
*source_mask = 0;
*stereo_mask = 0;
*swap_mask = 0;
*controller_mask = 0;
*source_mask = 0U;
*stereo_mask = 0U;
*swap_mask = 0U;
*controller_mask = 0U;
/* Loop number of PDM controllers in the configuration. If mic A
* or B is enabled then a pdm controller is marked as active. Also it
@ -668,7 +668,7 @@ static int source_ipm_helper(struct pdm_chan_cfg *config, u32_t *source_mask,
* swapped mono left. The function returns also in array source[] the
* indice of enabled pdm controllers to be used for IPM configuration.
*/
for (chan_ix = 0; chan_ix < config->req_num_chan; chan_ix++) {
for (chan_ix = 0U; chan_ix < config->req_num_chan; chan_ix++) {
dmic_parse_channel_map(config->req_chan_map_lo,
config->req_chan_map_hi,

4
drivers/bluetooth/hci/h4.c
View file

@ -155,9 +155,9 @@ static inline void copy_hdr(struct net_buf *buf)
static void reset_rx(void)
{
rx.type = H4_NONE;
rx.remaining = 0;
rx.remaining = 0U;
rx.have_hdr = false;
rx.hdr_len = 0;
rx.hdr_len = 0U;
rx.discardable = false;
}

2
drivers/bluetooth/hci/h5.c
View file

@ -711,7 +711,7 @@ static void h5_init(void)
h5.link_state = UNINIT;
h5.rx_state = START;
h5.tx_win = 4;
h5.tx_win = 4U;
/* TX thread */
k_fifo_init(&h5.tx_queue);

4
drivers/bluetooth/hci/spi.c
View file

@ -83,7 +83,7 @@ static inline void spi_dump_message(const u8_t *pre, u8_t *buf,
u8_t i, c;
printk("%s (%d): ", pre, size);
for (i = 0; i < size; i++) {
for (i = 0U; i < size; i++) {
c = buf[i];
printk("%x ", c);
if (c >= 31 && c <= 126) {
@ -283,7 +283,7 @@ static void bt_spi_rx_thread(void)
u8_t header_master[5] = { SPI_READ, 0x00, 0x00, 0x00, 0x00 };
u8_t header_slave[5];
struct bt_hci_acl_hdr acl_hdr;
u8_t size = 0;
u8_t size = 0U;
int ret;
(void)memset(&txmsg, 0xFF, SPI_MAX_MSG_LEN);

6
drivers/can/stm32_can.c
View file

@ -288,7 +288,7 @@ static int can_stm32_init(struct device *dev)
data->filter_usage = (1ULL << CAN_MAX_NUMBER_OF_FILTES) - 1ULL;
(void)memset(data->rx_response, 0,
sizeof(void *) * CONFIG_CAN_MAX_FILTER);
data->response_type = 0;
data->response_type = 0U;
clock = device_get_binding(STM32_CLOCK_CONTROL_NAME);
__ASSERT_NO_MSG(clock);
@ -595,8 +595,8 @@ static inline int can_stm32_set_filter(const struct can_filter *filter,
CAN_TypeDef *can,
int *filter_index)
{
u32_t mask = 0;
u32_t id = 0;
u32_t mask = 0U;
u32_t id = 0U;
int filter_nr = 0;
int filter_index_tmp = CAN_NO_FREE_FILTER;
int bank_nr;

8
drivers/clock_control/beetle_clock_control.c
View file

@ -84,7 +84,7 @@ static inline int beetle_clock_control_on(struct device *dev,
struct arm_clock_control_t *beetle_cc =
(struct arm_clock_control_t *)(sub_system);
u8_t bit = 0;
u8_t bit = 0U;
switch (beetle_cc->bus) {
case CMSDK_AHB:
@ -108,7 +108,7 @@ static inline int beetle_clock_control_off(struct device *dev,
struct arm_clock_control_t *beetle_cc =
(struct arm_clock_control_t *)(sub_system);
u8_t bit = 0;
u8_t bit = 0U;
switch (beetle_cc->bus) {
case CMSDK_AHB:
@ -154,7 +154,7 @@ static const struct clock_control_driver_api beetle_clock_control_api = {
#ifdef CONFIG_CLOCK_CONTROL_BEETLE_ENABLE_PLL
static u32_t beetle_round_freq(u32_t mainclk)
{
u32_t nc_mainclk = 0;
u32_t nc_mainclk = 0U;
/*
* Verify that the frequency is in the supported range otherwise
@ -175,7 +175,7 @@ static u32_t beetle_round_freq(u32_t mainclk)
static u32_t beetle_get_prescaler(u32_t mainclk)
{
u32_t pre_mainclk = 0;
u32_t pre_mainclk = 0U;
/*
* Verify that the frequency is in the supported range otherwise

12
drivers/clock_control/nrf5_power_clock.c
View file

@ -47,7 +47,7 @@ static int _m16src_start(struct device *dev, clock_control_subsys_t sub_system)
return -EAGAIN;
}
m16src_grd = 1;
m16src_grd = 1U;
irq_unlock(imask);
@ -87,7 +87,7 @@ static int _m16src_start(struct device *dev, clock_control_subsys_t sub_system)
}
/* release resource guard */
m16src_grd = 0;
m16src_grd = 0U;
hf_already_started:
/* rollover should not happen as start and stop shall be
@ -130,7 +130,7 @@ static int _m16src_stop(struct device *dev, clock_control_subsys_t sub_system)
return -EAGAIN;
}
m16src_grd = 1;
m16src_grd = 1U;
irq_unlock(imask);
@ -139,7 +139,7 @@ static int _m16src_stop(struct device *dev, clock_control_subsys_t sub_system)
nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
/* release resource guard */
m16src_grd = 0;
m16src_grd = 0U;
return 0;
}
@ -172,7 +172,7 @@ static int _k32src_start(struct device *dev, clock_control_subsys_t sub_system)
goto lf_already_started;
}
k32src_initialized = 1;
k32src_initialized = 1U;
irq_unlock(imask);
@ -348,7 +348,7 @@ static void _power_clock_isr(void *arg)
/* Start HF Clock if LF RC is used. */
if ((NRF_CLOCK->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk) ==
CLOCK_LFCLKSRCCOPY_SRC_RC) {
ctto = 1;
ctto = 1U;
}
}
}

4
drivers/console/ipm_console_receiver.c
View file

@ -30,7 +30,7 @@ static void ipm_console_thread(void *arg1, void *arg2, void *arg3)
driver_data = d->driver_data;
config_info = d->config->config_info;
ARG_UNUSED(arg2);
size32 = 0;
size32 = 0U;
pos = 0;
while (1) {
@ -42,7 +42,7 @@ static void ipm_console_thread(void *arg1, void *arg2, void *arg3)
if (ret) {
/* Shouldn't ever happen... */
printk("ipm console ring buffer error: %d\n", ret);
size32 = 0;
size32 = 0U;
continue;
}

16
drivers/console/telnet_console.c
View file

@ -100,11 +100,11 @@ static void telnet_rb_init(void)
{
int i;
telnet_rb.line_in = 0;
telnet_rb.line_out = 0;
telnet_rb.line_in = 0U;
telnet_rb.line_out = 0U;
for (i = 0; i < TELNET_LINES; i++) {
telnet_rb.l_bufs[i].len = 0;
telnet_rb.l_bufs[i].len = 0U;
}
}
@ -141,10 +141,10 @@ static void telnet_rb_switch(void)
telnet_rb.line_in++;
if (telnet_rb.line_in == TELNET_LINES) {
telnet_rb.line_in = 0;
telnet_rb.line_in = 0U;
}
telnet_rb.l_bufs[telnet_rb.line_in].len = 0;
telnet_rb.l_bufs[telnet_rb.line_in].len = 0U;
/* Unfortunately, we don't have enough line buffer,
* so we eat the next to be sent.
@ -152,7 +152,7 @@ static void telnet_rb_switch(void)
if (telnet_rb.line_in == telnet_rb.line_out) {
telnet_rb.line_out++;
if (telnet_rb.line_out == TELNET_LINES) {
telnet_rb.line_out = 0;
telnet_rb.line_out = 0U;
}
}
@ -166,7 +166,7 @@ static inline struct line_buf *telnet_rb_get_line_out(void)
telnet_rb.line_out++;
if (telnet_rb.line_out == TELNET_LINES) {
telnet_rb.line_out = 0;
telnet_rb.line_out = 0U;
}
if (!telnet_rb.l_bufs[out].len) {
@ -240,7 +240,7 @@ static inline bool telnet_send(void)
K_FOREVER);
/* We reinitialize the line buffer */
lb->len = 0;
lb->len = 0U;
if (net_context_send(out_pkt, telnet_sent_cb,
K_NO_WAIT, NULL, NULL) ||

18
drivers/console/uart_console.c
View file

@ -258,13 +258,13 @@ static void handle_ansi(u8_t byte, char *line)
{
if (atomic_test_and_clear_bit(&esc_state, ESC_ANSI_FIRST)) {
if (!isdigit(byte)) {
ansi_val = 1;
ansi_val = 1U;
goto ansi_cmd;
}
atomic_set_bit(&esc_state, ESC_ANSI_VAL);
ansi_val = byte - '0';
ansi_val_2 = 0;
ansi_val_2 = 0U;
return;
}
@ -317,7 +317,7 @@ ansi_cmd:
cursor_backward(cur);
end += cur;
cur = 0;
cur = 0U;
break;
case ANSI_END:
if (!end) {
@ -326,7 +326,7 @@ ansi_cmd:
cursor_forward(end);
cur += end;
end = 0;
end = 0U;
break;
case ANSI_DEL:
if (!end) {
@ -441,8 +441,8 @@ static bool handle_mcumgr(struct console_input *cmd, uint8_t byte)
clear_mcumgr();
cmd = NULL;
cur = 0;
end = 0;
cur = 0U;
end = 0U;
}
return true;
@ -529,8 +529,8 @@ void uart_console_isr(struct device *unused)
cmd->line[cur + end] = '\0';
uart_poll_out(uart_console_dev, '\r');
uart_poll_out(uart_console_dev, '\n');
cur = 0;
end = 0;
cur = 0U;
end = 0U;
k_fifo_put(lines_queue, cmd);
cmd = NULL;
break;
@ -617,7 +617,7 @@ static int uart_console_init(struct device *arg)
#if defined(CONFIG_USB_UART_CONSOLE) && defined(CONFIG_USB_UART_DTR_WAIT)
while (1) {
u32_t dtr = 0;
u32_t dtr = 0U;
uart_line_ctrl_get(uart_console_dev, LINE_CTRL_DTR, &dtr);
if (dtr) {

16
drivers/console/websocket_console.c
View file

@ -101,11 +101,11 @@ static void ws_rb_init(void)
{
int i;
ws_rb.line_in = 0;
ws_rb.line_out = 0;
ws_rb.line_in = 0U;
ws_rb.line_out = 0U;
for (i = 0; i < WS_CONSOLE_LINES; i++) {
ws_rb.l_bufs[i].len = 0;
ws_rb.l_bufs[i].len = 0U;
}
}
@ -127,10 +127,10 @@ static void ws_rb_switch(void)
ws_rb.line_in++;
if (ws_rb.line_in == WS_CONSOLE_LINES) {
ws_rb.line_in = 0;
ws_rb.line_in = 0U;
}
ws_rb.l_bufs[ws_rb.line_in].len = 0;
ws_rb.l_bufs[ws_rb.line_in].len = 0U;
/* Unfortunately, we don't have enough line buffer,
* so we eat the next to be sent.
@ -138,7 +138,7 @@ static void ws_rb_switch(void)
if (ws_rb.line_in == ws_rb.line_out) {
ws_rb.line_out++;
if (ws_rb.line_out == WS_CONSOLE_LINES) {
ws_rb.line_out = 0;
ws_rb.line_out = 0U;
}
}
@ -152,7 +152,7 @@ static inline struct line_buf *ws_rb_get_line_out(void)
ws_rb.line_out++;
if (ws_rb.line_out == WS_CONSOLE_LINES) {
ws_rb.line_out = 0;
ws_rb.line_out = 0U;
}
if (!ws_rb.l_bufs[out].len) {
@ -274,7 +274,7 @@ static bool ws_console_send(struct http_ctx *console)
NULL, NULL);
/* We reinitialize the line buffer */
lb->len = 0;
lb->len = 0U;
}
return true;

2
drivers/counter/counter_dtmr_cmsdk_apb.c
View file

@ -56,7 +56,7 @@ static u32_t counter_dtmr_cmsdk_apb_read(struct device *dev)
dev->config->config_info;
/* Return Counter Value */
u32_t value = 0;
u32_t value = 0U;
value = DUALTIMER_MAX_RELOAD - cfg->dtimer->timer1value;

2
drivers/counter/counter_tmr_cmsdk_apb.c
View file

@ -56,7 +56,7 @@ static u32_t counter_tmr_cmsdk_apb_read(struct device *dev)
dev->config->config_info;
/* Return Counter Value */
u32_t value = 0;
u32_t value = 0U;
value = TIMER_MAX_RELOAD - cfg->timer->value;

2
drivers/counter/timer_dtmr_cmsdk_apb.c
View file

@ -80,7 +80,7 @@ static u32_t timer_dtmr_cmsdk_apb_read(struct device *dev)
struct timer_dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Return Timer Value */
u32_t value = 0;
u32_t value = 0U;
value = data->load - cfg->dtimer->timer1value;

2
drivers/counter/timer_tmr_cmsdk_apb.c
View file

@ -80,7 +80,7 @@ static u32_t timer_tmr_cmsdk_apb_read(struct device *dev)
struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Return Counter Value */
u32_t value = 0;
u32_t value = 0U;
value = data->load - cfg->timer->value;

2
drivers/crypto/crypto_ataes132a_priv.h
View file

@ -119,7 +119,7 @@ void ataes132a_atmel_crc(u8_t *input, u8_t length,
u16_t double_carry;
u8_t higher_crc_bit;
for (i = 0, crc = 0; i < length; i++) {
for (i = 0, crc = 0U; i < length; i++) {
for (j = 7; j >= 0; j--) {
bit = !!(input[i] & BIT(j));
higher_crc_bit = crc >> 15;

6
drivers/display/display_ili9340.c
View file

@ -134,11 +134,11 @@ static int ili9340_write(const struct device *dev, const u16_t x,
ili9340_set_mem_area(data, x, y, desc->width, desc->height);
if (desc->pitch > desc->width) {
write_h = 1;
write_h = 1U;
nbr_of_writes = desc->height;
} else {
write_h = desc->height;
nbr_of_writes = 1;
nbr_of_writes = 1U;
}
ili9340_transmit(data, ILI9340_CMD_MEM_WRITE,
@ -148,7 +148,7 @@ static int ili9340_write(const struct device *dev, const u16_t x,
tx_bufs.count = 1;
write_data_start += (3 * desc->pitch);
for (write_cnt = 1; write_cnt < nbr_of_writes; ++write_cnt) {
for (write_cnt = 1U; write_cnt < nbr_of_writes; ++write_cnt) {
tx_buf.buf = (void *)write_data_start;
tx_buf.len = 3 * desc->width * write_h;
spi_write(data->spi_dev, &data->spi_config, &tx_bufs);

6
drivers/display/grove_lcd_rgb.c
View file

@ -252,9 +252,9 @@ int glcd_initialize(struct device *port)
LOG_DBG("initialize called");
dev->input_set = 0;
dev->display_switch = 0;
dev->function = 0;
dev->input_set = 0U;
dev->display_switch = 0U;
dev->function = 0U;
/*
* First set up the device driver...

32
drivers/display/mb_display.c
View file

@ -146,7 +146,7 @@ static void start_image(struct mb_display *disp, const struct mb_image *img)
int row, col;
for (row = 0; row < DISPLAY_ROWS; row++) {
disp->row[row] = 0;
disp->row[row] = 0U;
for (col = 0; col < DISPLAY_COLS; col++) {
if (GET_PIXEL(img, map[row][col].x, map[row][col].y)) {
@ -158,7 +158,7 @@ static void start_image(struct mb_display *disp, const struct mb_image *img)
disp->row[row] |= BIT(LED_ROW1_GPIO_PIN + row);
}
disp->cur = 0;
disp->cur = 0U;
if (disp->duration == K_FOREVER) {
disp->expiry = K_FOREVER;
@ -196,9 +196,9 @@ static void reset_display(struct mb_display *disp)
k_timer_stop(&disp->timer);
disp->str = NULL;
disp->cur_img = 0;
disp->cur_img = 0U;
disp->img = NULL;
disp->img_count = 0;
disp->img_count = 0U;
disp->scroll = SCROLL_OFF;
}
@ -269,7 +269,7 @@ static void update_scroll(struct mb_display *disp)
start_image(disp, &img);
} else {
if (disp->first) {
disp->first = 0;
disp->first = 0U;
} else {
disp->cur_img++;
}
@ -280,8 +280,8 @@ static void update_scroll(struct mb_display *disp)
return;
}
disp->cur_img = 0;
disp->first = 1;
disp->cur_img = 0U;
disp->first = 1U;
}
disp->scroll = SCROLL_START;
@ -299,7 +299,7 @@ static void update_image(struct mb_display *disp)
return;
}
disp->cur_img = 0;
disp->cur_img = 0U;
}
start_image(disp, current_img(disp));
@ -343,8 +343,8 @@ static void start_scroll(struct mb_display *disp, s32_t duration)
}
disp->scroll = SCROLL_START;
disp->first = 1;
disp->cur_img = 0;
disp->first = 1U;
disp->cur_img = 0U;
start_image(disp, get_font(' '));
}
@ -366,11 +366,11 @@ void mb_display_image(struct mb_display *disp, u32_t mode, s32_t duration,
__ASSERT(img && img_count > 0, "Invalid parameters");
disp->text = 0;
disp->text = 0U;
disp->img_count = img_count;
disp->img = img;
disp->img_sep = 0;
disp->cur_img = 0;
disp->img_sep = 0U;
disp->cur_img = 0U;
disp->loop = !!(mode & MB_DISPLAY_FLAG_LOOP);
switch (mode & MODE_MASK) {
@ -407,9 +407,9 @@ void mb_display_print(struct mb_display *disp, u32_t mode,
}
disp->str = disp->str_buf;
disp->text = 1;
disp->img_sep = 1;
disp->cur_img = 0;
disp->text = 1U;
disp->img_sep = 1U;
disp->cur_img = 0U;
disp->loop = !!(mode & MB_DISPLAY_FLAG_LOOP);
switch (mode & MODE_MASK) {

10
drivers/display/ssd1673.c
View file

@ -88,7 +88,7 @@ static inline int ssd1673_write_cmd(struct ssd1673_data *driver,
static inline void ssd1673_busy_wait(struct ssd1673_data *driver)
{
u32_t val = 0;
u32_t val = 0U;
gpio_pin_read(driver->busy, DT_SSD1673_BUSY_PIN, &val);
while (val) {
@ -181,7 +181,7 @@ static int ssd1673_update_display(const struct device *dev, bool initial)
}
if (initial) {
driver->numof_part_cycles = 0;
driver->numof_part_cycles = 0U;
driver->last_lut = SSD1673_LAST_LUT_INITIAL;
if (ssd1673_write_cmd(driver, SSD1673_CMD_UPDATE_LUT,
ssd1673_lut_initial,
@ -409,7 +409,7 @@ static int ssd1673_controller_init(struct device *dev)
ssd1673_busy_wait(driver);
tmp[0] = (SSD1673_RAM_YRES - 1);
tmp[1] = 0;
tmp[1] = 0U;
if (ssd1673_write_cmd(driver, SSD1673_CMD_GDO_CTRL, tmp, 2)) {
return -1;
}
@ -441,9 +441,9 @@ static int ssd1673_controller_init(struct device *dev)
}
ssd1673_set_orientation(driver);
driver->numof_part_cycles = 0;
driver->numof_part_cycles = 0U;
driver->last_lut = SSD1673_LAST_LUT_INITIAL;
driver->contrast = 0;
driver->contrast = 0U;
return 0;
}

6
drivers/dma/dma_cavs.c
View file

@ -58,9 +58,9 @@ static void dw_dma_isr(void *arg)
struct dw_dma_dev_data *const dev_data = DEV_DATA(dev);
struct dma_chan_data *chan_data;
u32_t status_tfr = 0;
u32_t status_block = 0;
u32_t status_err = 0;
u32_t status_tfr = 0U;
u32_t status_block = 0U;
u32_t status_err = 0U;
u32_t status_intr;
u32_t channel;

2
drivers/dma/dma_qmsi.c
View file

@ -133,7 +133,7 @@ static int dma_qmsi_chan_config(struct device *dev, u32_t channel,
struct dma_qmsi_driver_data *data = dev->driver_data;
qm_dma_transfer_t qmsi_transfer_cfg = { 0 };
qm_dma_channel_config_t qmsi_cfg = { 0 };
u32_t temp = 0;
u32_t temp = 0U;
int ret = 0;
if (config->block_count != 1) {

6
drivers/dma/dma_sam_xdmac.c
View file

@ -243,9 +243,9 @@ static int sam_xdmac_config(struct device *dev, u32_t channel,
| XDMAC_CC_SIF_AHB_IF1
| XDMAC_CC_DIF_AHB_IF1
| XDMAC_CC_PERID(cfg->dma_slot);
channel_cfg.ds_msp = 0;
channel_cfg.sus = 0;
channel_cfg.dus = 0;
channel_cfg.ds_msp = 0U;
channel_cfg.sus = 0U;
channel_cfg.dus = 0U;
channel_cfg.cie =
(cfg->complete_callback_en ? XDMAC_CIE_BIE : XDMAC_CIE_LIE)
| (cfg->error_callback_en ? XDMAC_INT_ERR : 0);

2
drivers/entropy/entropy_mcux_rnga.c
View file

@ -14,7 +14,7 @@
static u8_t entropy_mcux_rnga_get_uint8(void)
{
u32_t random;
u8_t output = 0;
u8_t output = 0U;
int i;
RNGA_SetMode(RNG, kRNGA_ModeNormal);

6
drivers/entropy/entropy_nrf5.c
View file

@ -192,9 +192,9 @@ static int rng_pool_put(struct rng_pool *rngp, u8_t byte)
static void rng_pool_init(struct rng_pool *rngp, u16_t size, u8_t threshold)
{
rngp->first_alloc = 0;
rngp->first_read = 0;
rngp->last = 0;
rngp->first_alloc = 0U;
rngp->first_read = 0U;
rngp->last = 0U;
rngp->mask = size - 1;
rngp->threshold = threshold;
}

28
drivers/ethernet/eth_dw.c
View file

@ -106,7 +106,7 @@ static void eth_rx(struct device *dev)
release_desc:
/* Return ownership of the RX descriptor to the device. */
context->rx_desc.own = 1;
context->rx_desc.own = 1U;
/* Request that the device check for an available RX descriptor, since
* ownership of the descriptor was just transferred to the device.
@ -146,7 +146,7 @@ static void eth_tx_data(struct eth_runtime *context, u8_t *data, u16_t len)
eth_write(context->base_addr, REG_ADDR_TX_DESC_LIST,
(u32_t)&context->tx_desc);
context->tx_desc.own = 1;
context->tx_desc.own = 1U;
/* Request that the device check for an available TX descriptor, since
* ownership of the descriptor was just transferred to the device.
@ -257,27 +257,27 @@ static int eth_initialize_internal(struct net_if *iface)
/* Initialize receive descriptor. */
context->rx_desc.rdes0 = 0;
context->rx_desc.rdes1 = 0;
context->rx_desc.rdes0 = 0U;
context->rx_desc.rdes1 = 0U;
context->rx_desc.buf1_ptr = (u8_t *)context->rx_buf;
context->rx_desc.first_desc = 1;
context->rx_desc.last_desc = 1;
context->rx_desc.own = 1;
context->rx_desc.first_desc = 1U;
context->rx_desc.last_desc = 1U;
context->rx_desc.own = 1U;
context->rx_desc.rx_buf1_sz = sizeof(context->rx_buf);
context->rx_desc.rx_end_of_ring = 1;
context->rx_desc.rx_end_of_ring = 1U;
/* Install receive descriptor. */
eth_write(base_addr, REG_ADDR_RX_DESC_LIST, (u32_t)&context->rx_desc);
/* Initialize transmit descriptor. */
context->tx_desc.tdes0 = 0;
context->tx_desc.tdes1 = 0;
context->tx_desc.tdes0 = 0U;
context->tx_desc.tdes1 = 0U;
context->tx_desc.buf1_ptr = NULL;
context->tx_desc.tx_buf1_sz = 0;
context->tx_desc.first_seg_in_frm = 1;
context->tx_desc.last_seg_in_frm = 1;
context->tx_desc.tx_end_of_ring = 1;
context->tx_desc.tx_buf1_sz = 0U;
context->tx_desc.first_seg_in_frm = 1U;
context->tx_desc.last_seg_in_frm = 1U;
context->tx_desc.tx_end_of_ring = 1U;
/* Install transmit descriptor. */
eth_write(context->base_addr, REG_ADDR_TX_DESC_LIST,

12
drivers/ethernet/eth_enc28j60.c
View file

@ -115,10 +115,10 @@ static void eth_enc28j60_read_reg(struct device *dev, u16_t reg_addr,
.buffers = &rx_buf,
.count = 1
};
u8_t rx_size = 2;
u8_t rx_size = 2U;
if (reg_addr & 0xF000) {
rx_size = 3;
rx_size = 3U;
}
rx_buf.len = rx_size;
@ -130,7 +130,7 @@ static void eth_enc28j60_read_reg(struct device *dev, u16_t reg_addr,
*value = buf[rx_size - 1];
} else {
LOG_DBG("Failure while reading register 0x%04x", reg_addr);
*value = 0;
*value = 0U;
}
}
@ -513,12 +513,12 @@ static int eth_enc28j60_rx(struct device *dev)
do {
struct net_buf *pkt_buf = NULL;
struct net_buf *last_buf = NULL;
u16_t frm_len = 0;
u16_t frm_len = 0U;
u8_t info[RSV_SIZE];
struct net_pkt *pkt;
u16_t next_packet;
u8_t rdptl = 0;
u8_t rdpth = 0;
u8_t rdptl = 0U;
u8_t rdpth = 0U;
/* remove read fifo address to packet header address */
eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXRDPTL);

8
drivers/ethernet/eth_mcux.c
View file

@ -182,7 +182,7 @@ static inline struct net_if *get_iface(struct eth_context *ctx, u16_t vlan_tag)
static void eth_mcux_phy_enter_reset(struct eth_context *context)
{
const u32_t phy_addr = 0;
const u32_t phy_addr = 0U;
/* Reset the PHY. */
ENET_StartSMIWrite(ENET, phy_addr, PHY_BASICCONTROL_REG,
@ -193,7 +193,7 @@ static void eth_mcux_phy_enter_reset(struct eth_context *context)
static void eth_mcux_phy_start(struct eth_context *context)
{
const u32_t phy_addr = 0;
const u32_t phy_addr = 0U;
#ifdef CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG
LOG_DBG("phy_state=%s", phy_state_name(context->phy_state));
#endif
@ -259,7 +259,7 @@ static void eth_mcux_phy_event(struct eth_context *context)
bool link_up;
phy_duplex_t phy_duplex = kPHY_FullDuplex;
phy_speed_t phy_speed = kPHY_Speed100M;
const u32_t phy_addr = 0;
const u32_t phy_addr = 0U;
#ifdef CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG
LOG_DBG("phy_state=%s", phy_state_name(context->phy_state));
@ -532,7 +532,7 @@ static void eth_rx(struct device *iface)
struct net_buf *prev_buf;
struct net_pkt *pkt;
const u8_t *src;
u32_t frame_length = 0;
u32_t frame_length = 0U;
status_t status;
unsigned int imask;
u16_t vlan_tag = NET_VLAN_TAG_UNSPEC;

34
drivers/ethernet/eth_sam_gmac.c
View file

@ -195,8 +195,8 @@ static inline void gmac_desc_append_w1(struct gmac_desc *desc, u32_t value)
*/
static void ring_buf_reset(struct ring_buf *rb)
{
rb->head = 0;
rb->tail = 0;
rb->head = 0U;
rb->tail = 0U;
}
/*
@ -270,8 +270,8 @@ static int rx_descriptors_init(Gmac *gmac, struct gmac_queue *queue)
__ASSERT_NO_MSG(rx_frag_list->buf);
rx_desc_list->tail = 0;
rx_frag_list->tail = 0;
rx_desc_list->tail = 0U;
rx_frag_list->tail = 0U;
for (int i = 0; i < rx_desc_list->len; i++) {
rx_buf = net_pkt_get_reserve_rx_data(0, K_NO_WAIT);
@ -308,8 +308,8 @@ static void tx_descriptors_init(Gmac *gmac, struct gmac_queue *queue)
{
struct gmac_desc_list *tx_desc_list = &queue->tx_desc_list;
tx_desc_list->head = 0;
tx_desc_list->tail = 0;
tx_desc_list->head = 0U;
tx_desc_list->tail = 0U;
for (int i = 0; i < tx_desc_list->len; i++) {
gmac_desc_set_w0(&tx_desc_list->buf[i], 0);
@ -602,8 +602,8 @@ static void rx_error_handler(Gmac *gmac, struct gmac_queue *queue)
/* Stop reception */
gmac->GMAC_NCR &= ~GMAC_NCR_RXEN;
queue->rx_desc_list.tail = 0;
queue->rx_frag_list.tail = 0;
queue->rx_desc_list.tail = 0U;
queue->rx_frag_list.tail = 0U;
for (int i = 0; i < queue->rx_desc_list.len; i++) {
gmac_desc_set_w1(&queue->rx_desc_list.buf[i], 0);
@ -829,8 +829,8 @@ static void gmac_setup_ptp_clock_divisors(Gmac *gmac)
}
nit = min_cycles - 1;
cns = 0;
acns = 0;
cns = 0U;
acns = 0U;
while ((cns + 2) * nit < min_period) {
cns++;
@ -985,9 +985,9 @@ static int nonpriority_queue_init(Gmac *gmac, struct gmac_queue *queue)
/* Setup RX/TX completion and error interrupts */
gmac->GMAC_IER = GMAC_INT_EN_FLAGS;
queue->err_rx_frames_dropped = 0;
queue->err_rx_flushed_count = 0;
queue->err_tx_flushed_count = 0;
queue->err_rx_frames_dropped = 0U;
queue->err_rx_flushed_count = 0U;
queue->err_tx_flushed_count = 0U;
LOG_INF("Queue %d activated", queue->que_idx);
@ -1035,9 +1035,9 @@ static int priority_queue_init(Gmac *gmac, struct gmac_queue *queue)
/* Enable RX/TX completion and error interrupts */
gmac->GMAC_IERPQ[queue_index] = GMAC_INTPQ_EN_FLAGS;
queue->err_rx_frames_dropped = 0;
queue->err_rx_flushed_count = 0;
queue->err_tx_flushed_count = 0;
queue->err_rx_frames_dropped = 0U;
queue->err_rx_flushed_count = 0U;
queue->err_tx_flushed_count = 0U;
return 0;
}
@ -1096,7 +1096,7 @@ static struct net_pkt *frame_get(struct gmac_queue *queue)
struct net_buf *last_frag = NULL;
u8_t *frag_data;
u32_t frag_len;
u32_t frame_len = 0;
u32_t frame_len = 0U;
u16_t tail;
u8_t wrap;

4
drivers/ethernet/phy_sam_gmac.c
View file

@ -39,7 +39,7 @@ static void mdio_bus_disable(Gmac *gmac)
/* Wait PHY operation complete. */
static int mdio_bus_wait(Gmac *gmac)
{
u32_t retries = 100; /* will wait up to 1 s */
u32_t retries = 100U; /* will wait up to 1 s */
while (!(gmac->GMAC_NSR & GMAC_NSR_IDLE)) {
if (retries-- == 0) {
@ -109,7 +109,7 @@ static int phy_write(const struct phy_sam_gmac_dev *phy, u8_t reg_addr,
static int phy_soft_reset(const struct phy_sam_gmac_dev *phy)
{
u32_t phy_reg;
u32_t retries = 12;
u32_t retries = 12U;
int retval;
/* Issue a soft reset */

4
drivers/flash/flash_sam0.c
View file

@ -145,7 +145,7 @@ static int flash_sam0_write_page(struct device *dev, off_t offset,
static int flash_sam0_erase_row(struct device *dev, off_t offset)
{
*FLASH_MEM(offset) = 0;
*FLASH_MEM(offset) = 0U;
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY;
return flash_sam0_check_status(offset);
@ -318,7 +318,7 @@ static int flash_sam0_write_protection(struct device *dev, bool enable)
for (offset = 0; offset < CONFIG_FLASH_SIZE * 1024;
offset += LOCK_REGION_SIZE) {
*FLASH_MEM(offset) = 0;
*FLASH_MEM(offset) = 0U;
if (enable) {
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_LR |

12
drivers/flash/flash_stm32f3x.c
View file

@ -12,10 +12,10 @@
static int flash_stm32_erase(struct device *dev, off_t offset, size_t size)
{
u32_t first_page_addr = 0;
u32_t last_page_addr = 0;
u32_t first_page_addr = 0U;
u32_t last_page_addr = 0U;
u16_t no_of_pages = size / CONFIG_FLASH_PAGE_SIZE;
u16_t page_index = 0;
u16_t page_index = 0U;
/* Check offset and size alignment. */
if (((offset % CONFIG_FLASH_PAGE_SIZE) != 0) ||
@ -67,15 +67,15 @@ static int flash_stm32_read(struct device *dev, off_t offset,
static int flash_stm32_write(struct device *dev, off_t offset,
const void *data, size_t len)
{
u16_t halfword = 0;
u16_t halfword = 0U;
u32_t address =
CONFIG_FLASH_BASE_ADDRESS + offset;
u8_t remainder = 0;
u8_t remainder = 0U;
if ((len % 2) != 0) {
remainder = 1;
remainder = 1U;
}
len = len / 2;

20
drivers/flash/soc_flash_nios2_qspi.c
View file

@ -92,9 +92,9 @@ static int flash_nios2_qspi_erase(struct device *dev, off_t offset, size_t len)
break;
}
block_offset = 0; /* block offset in byte addressing */
offset_in_block = 0; /* offset into current sector to erase */
length_to_erase = 0; /* length to erase in current sector */
block_offset = 0U; /* block offset in byte addressing */
offset_in_block = 0U; /* offset into current sector to erase */
length_to_erase = 0U; /* length to erase in current sector */
/* calculate current sector/block offset in byte addressing */
block_offset = erase_offset & ~(qspi_dev->sector_size - 1);
@ -161,7 +161,7 @@ static int flash_nios2_qspi_write_block(struct device *dev, int block_offset,
{
struct flash_nios2_qspi_config *flash_cfg = dev->driver_data;
alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
u32_t buffer_offset = 0; /* offset into data buffer to get write data */
u32_t buffer_offset = 0U; /* offset into data buffer to get write data */
u32_t remaining_length = len; /* length left to write */
u32_t write_offset = mem_offset; /* offset into flash to write too */
u32_t word_to_write, padding, bytes_to_copy;
@ -173,7 +173,7 @@ static int flash_nios2_qspi_write_block(struct device *dev, int block_offset,
word_to_write = NIOS2_QSPI_BLANK_WORD;
/* bytes to pad the next word that is written */
padding = 0;
padding = 0U;
/* number of bytes from source to copy */
bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE;
@ -260,7 +260,7 @@ static int flash_nios2_qspi_write(struct device *dev, off_t offset,
alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
u32_t block_offset, offset_in_block, length_to_write;
u32_t write_offset = offset; /* address of next byte to write */
u32_t buffer_offset = 0; /* offset into source buffer */
u32_t buffer_offset = 0U; /* offset into source buffer */
u32_t remaining_length = len; /* length of data left to be written */
s32_t rc = 0, i;
@ -284,9 +284,9 @@ static int flash_nios2_qspi_write(struct device *dev, off_t offset,
break;
}
block_offset = 0; /* block offset in byte addressing */
offset_in_block = 0; /* offset into current sector to write */
length_to_write = 0; /* length to write to current sector */
block_offset = 0U; /* block offset in byte addressing */
offset_in_block = 0U; /* offset into current sector to write */
length_to_write = 0U; /* length to write to current sector */
/* calculate current sector/block offset in byte addressing */
block_offset = write_offset & ~(qspi_dev->sector_size - 1);
@ -324,7 +324,7 @@ static int flash_nios2_qspi_read(struct device *dev, off_t offset,
{
struct flash_nios2_qspi_config *flash_cfg = dev->driver_data;
alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
u32_t buffer_offset = 0; /* offset into data buffer to get read data */
u32_t buffer_offset = 0U; /* offset into data buffer to get read data */
u32_t remaining_length = len; /* length left to read */
u32_t read_offset = offset; /* offset into flash to read from */
u32_t word_to_read, bytes_to_copy;

8
drivers/flash/soc_flash_nrf.c
View file

@ -407,9 +407,9 @@ static int erase_op(void *context)
struct flash_context *e_ctx = context;
#if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC)
u32_t ticks_begin = 0;
u32_t ticks_begin = 0U;
u32_t ticks_diff;
u32_t i = 0;
u32_t i = 0U;
if (e_ctx->enable_time_limit) {
ticks_begin = ticker_ticks_now_get();
@ -464,9 +464,9 @@ static int write_op(void *context)
u32_t count;
#if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC)
u32_t ticks_begin = 0;
u32_t ticks_begin = 0U;
u32_t ticks_diff;
u32_t i = 1;
u32_t i = 1U;
if (w_ctx->enable_time_limit) {
ticks_begin = ticker_ticks_now_get();

4
drivers/flash/soc_flash_qmsi.c
View file

@ -115,7 +115,7 @@ static int flash_qmsi_write(struct device *dev, off_t addr,
{
qm_flash_t flash = QM_FLASH_0;
qm_flash_region_t reg;
u32_t data_word = 0, offset = 0, f_addr = 0;
u32_t data_word = 0U, offset = 0U, f_addr = 0U;
if ((!is_aligned_32(len)) || (!is_aligned_32(addr))) {
return -EINVAL;
@ -173,7 +173,7 @@ static int flash_qmsi_erase(struct device *dev, off_t addr, size_t size)
{
qm_flash_t flash = QM_FLASH_0;
qm_flash_region_t reg;
u32_t page = 0;
u32_t page = 0U;
/* starting address needs to be a 2KB aligned address */
if (addr & QM_FLASH_ADDRESS_MASK) {

2
drivers/flash/spi_flash_w25qxxdv.c
View file

@ -184,7 +184,7 @@ static int spi_flash_wb_write(struct device *dev, off_t offset,
static int spi_flash_wb_write_protection_set(struct device *dev, bool enable)
{
struct spi_flash_data *const driver_data = dev->driver_data;
u8_t reg = 0;
u8_t reg = 0U;
int ret;
SYNC_LOCK();

6
drivers/gpio/gpio_cc2650.c
View file

@ -227,7 +227,7 @@ static int gpio_cc2650_config(struct device *port, int access_op,
return gpio_cc2650_config_pin(pin, flags);
}
const u32_t nb_pins = 32;
const u32_t nb_pins = 32U;
for (u8_t i = 0; i < nb_pins; ++i) {
if (pin & 0x1 &&
@ -257,7 +257,7 @@ static int gpio_cc2650_write(struct device *port, int access_op,
if (access_op == GPIO_ACCESS_BY_PIN) {
gpio_cc2650_write_pin(pin, value);
} else {
const u32_t nb_pins = 32;
const u32_t nb_pins = 32U;
for (u32_t i = 0; i < nb_pins; ++i) {
if (pin & 0x1) {
@ -279,7 +279,7 @@ static int gpio_cc2650_read(struct device *port, int access_op,
gpio_cc2650_read_pin(pin, value);
*value >>= pin;
} else {
const u32_t nb_pins = 32;
const u32_t nb_pins = 32U;
for (u32_t i = 0; i < nb_pins; ++i) {
if (pin & 0x1) {

2
drivers/gpio/gpio_cc32xx.c
View file

@ -158,7 +158,7 @@ static int gpio_cc32xx_disable_callback(struct device *dev,
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables &= ~(1 << pin);
} else {
data->pin_callback_enables = 0;
data->pin_callback_enables = 0U;
}
return 0;

4
drivers/gpio/gpio_gecko.c
View file

@ -74,7 +74,7 @@ static int gpio_gecko_configure(struct device *dev,
GPIO_P_TypeDef *gpio_base = config->gpio_base;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_Mode_TypeDef mode;
unsigned int out = 0;
unsigned int out = 0U;
/* Check for an invalid pin configuration */
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
@ -94,7 +94,7 @@ static int gpio_gecko_configure(struct device *dev,
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
mode = gpioModeInputPull;
out = 1; /* pull-up*/
out = 1U; /* pull-up*/
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
mode = gpioModeInputPull;
/* out = 0 means pull-down*/

8
drivers/gpio/gpio_imx.c
View file

@ -65,7 +65,7 @@ static int imx_gpio_configure(struct device *dev,
GPIO_Init(config->base, &pin_config);
GPIO_SetIntEdgeSelect(config->base, pin, double_edge);
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < 32; i++) {
for (i = 0U; i < 32; i++) {
pin_config.pin = i;
GPIO_Init(config->base, &pin_config);
GPIO_SetIntEdgeSelect(config->base, i, double_edge);
@ -126,7 +126,7 @@ static int imx_gpio_enable_callback(struct device *dev,
GPIO_SetPinIntMode(config->base, pin, true);
} else {
data->pin_callback_enables = 0xFFFFFFFF;
for (i = 0; i < 32; i++) {
for (i = 0U; i < 32; i++) {
GPIO_SetPinIntMode(config->base, i, true);
}
}
@ -145,10 +145,10 @@ static int imx_gpio_disable_callback(struct device *dev,
GPIO_SetPinIntMode(config->base, pin, false);
data->pin_callback_enables &= ~BIT(pin);
} else {
for (i = 0; i < 32; i++) {
for (i = 0U; i < 32; i++) {
GPIO_SetPinIntMode(config->base, i, false);
}
data->pin_callback_enables = 0;
data->pin_callback_enables = 0U;
}
return 0;

8
drivers/gpio/gpio_mcux.c
View file

@ -34,8 +34,8 @@ static int gpio_mcux_configure(struct device *dev,
GPIO_Type *gpio_base = config->gpio_base;
PORT_Type *port_base = config->port_base;
port_interrupt_t port_interrupt = 0;
u32_t mask = 0;
u32_t pcr = 0;
u32_t mask = 0U;
u32_t pcr = 0U;
u8_t i;
/* Check for an invalid pin configuration */
@ -116,7 +116,7 @@ static int gpio_mcux_configure(struct device *dev,
if (access_op == GPIO_ACCESS_BY_PIN) {
port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < ARRAY_SIZE(port_base->PCR); i++) {
for (i = 0U; i < ARRAY_SIZE(port_base->PCR); i++) {
port_base->PCR[i] = (port_base->PCR[pin] & ~mask) | pcr;
}
}
@ -201,7 +201,7 @@ static int gpio_mcux_disable_callback(struct device *dev,
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables &= ~BIT(pin);
} else {
data->pin_callback_enables = 0;
data->pin_callback_enables = 0U;
}
return 0;

4
drivers/gpio/gpio_mcux_igpio.c
View file

@ -66,7 +66,7 @@ static int mcux_igpio_configure(struct device *dev,
if (access_op == GPIO_ACCESS_BY_PIN) {
GPIO_PinInit(config->base, pin, &pin_config);
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < 32; i++) {
for (i = 0U; i < 32; i++) {
GPIO_PinInit(config->base, i, &pin_config);
}
}
@ -140,7 +140,7 @@ static int mcux_igpio_disable_callback(struct device *dev,
data->pin_callback_enables &= ~BIT(pin);
} else {
GPIO_PortDisableInterrupts(config->base, 0);
data->pin_callback_enables = 0;
data->pin_callback_enables = 0U;
}
return 0;

8
drivers/gpio/gpio_nrfx.c
View file

@ -181,8 +181,8 @@ static int gpio_nrfx_config(struct device *port, int access_op,
: NRF_GPIO_PIN_INPUT_DISCONNECT;
if (access_op == GPIO_ACCESS_BY_PORT) {
from_pin = 0;
to_pin = 31;
from_pin = 0U;
to_pin = 31U;
} else {
from_pin = pin;
to_pin = pin;
@ -270,8 +270,8 @@ static int gpio_nrfx_pin_manage_callback(struct device *port,
u8_t to_pin;
if (access_op == GPIO_ACCESS_BY_PORT) {
from_pin = 0;
to_pin = 31;
from_pin = 0U;
to_pin = 31U;
} else {
from_pin = pin;
to_pin = pin;

6
drivers/gpio/gpio_pcal9535a.c
View file

@ -154,7 +154,7 @@ static int _setup_pin_dir(struct device *dev, int access_op,
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
union gpio_pcal9535a_port_data *port = &drv_data->reg_cache.dir;
u16_t bit_mask;
u16_t new_value = 0;
u16_t new_value = 0U;
int ret;
switch (access_op) {
@ -206,7 +206,7 @@ static int _setup_pin_pullupdown(struct device *dev, int access_op,
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
union gpio_pcal9535a_port_data *port;
u16_t bit_mask;
u16_t new_value = 0;
u16_t new_value = 0U;
int ret;
/* If disabling pull up/down, there is no need to set the selection
@ -299,7 +299,7 @@ static int _setup_pin_polarity(struct device *dev, int access_op,
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
union gpio_pcal9535a_port_data *port = &drv_data->reg_cache.pol_inv;
u16_t bit_mask;
u16_t new_value = 0;
u16_t new_value = 0U;
int ret;
switch (access_op) {

2
drivers/gpio/gpio_qmsi.c
View file

@ -336,7 +336,7 @@ static inline int gpio_qmsi_disable_callback(struct device *port,
if (access_op == GPIO_ACCESS_BY_PIN) {
context->pin_callbacks &= ~BIT(pin);
} else {
context->pin_callbacks = 0;
context->pin_callbacks = 0U;
}
if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {

2
drivers/gpio/gpio_qmsi_ss.c
View file

@ -329,7 +329,7 @@ static inline int ss_gpio_qmsi_disable_callback(struct device *port,
if (access_op == GPIO_ACCESS_BY_PIN) {
context->pin_callbacks &= ~BIT(pin);
} else {
context->pin_callbacks = 0;
context->pin_callbacks = 0U;
}
if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {

14
drivers/gpio/gpio_sch.c
View file

@ -89,17 +89,17 @@ static void _gpio_pin_config(struct device *dev, u32_t pin, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data;
u8_t active_high = 0;
u8_t active_low = 0;
u8_t active_high = 0U;
u8_t active_low = 0U;
_set_bit_gen(info->regs, pin, 1);
_set_bit_gio(info->regs, pin, !(flags & GPIO_DIR_MASK));
if (flags & GPIO_INT) {
if (flags & GPIO_INT_ACTIVE_HIGH) {
active_high = 1;
active_high = 1U;
} else {
active_low = 1;
active_low = 1U;
}
LOG_DBG("Setting up pin %d to active_high %d and "
@ -217,7 +217,7 @@ static void _gpio_sch_manage_callback(struct device *dev)
if (!sys_slist_is_empty(&gpio->callbacks) && gpio->cb_enabled) {
if (!gpio->poll) {
LOG_DBG("Starting SCH GPIO polling thread");
gpio->poll = 1;
gpio->poll = 1U;
k_thread_create(&gpio->polling_thread,
gpio->polling_stack,
GPIO_SCH_POLLING_STACK_SIZE,
@ -226,7 +226,7 @@ static void _gpio_sch_manage_callback(struct device *dev)
K_PRIO_COOP(1), 0, 0);
}
} else {
gpio->poll = 0;
gpio->poll = 0U;
}
}
@ -290,7 +290,7 @@ static int gpio_sch_disable_callback(struct device *dev,
_write_gtpe(0, info->regs);
_write_gtne(0, info->regs);
gpio->cb_enabled = 0;
gpio->cb_enabled = 0U;
}
_gpio_sch_manage_callback(dev);

10
drivers/gpio/gpio_shell.c
View file

@ -48,7 +48,7 @@ static const struct args_number args_no = {
static int cmd_gpio_conf(const struct shell *shell, size_t argc, char **argv)
{
u8_t index = 0;
u8_t index = 0U;
int type = GPIO_DIR_OUT;
struct device *dev;
@ -85,8 +85,8 @@ static int cmd_gpio_get(const struct shell *shell,
size_t argc, char **argv)
{
struct device *dev;
u8_t index = 0;
u32_t value = 0;
u8_t index = 0U;
u32_t value = 0U;
int rc;
if (argc == args_no.get && isdigit((unsigned char)argv[args_indx.index][0])) {
@ -120,8 +120,8 @@ static int cmd_gpio_set(const struct shell *shell,
size_t argc, char **argv)
{
struct device *dev;
u8_t index = 0;
u8_t value = 0;
u8_t index = 0U;
u8_t value = 0U;
if (argc == args_no.set &&
isdigit((unsigned char)argv[args_indx.index][0]) &&

16
drivers/gpio/gpio_sifive.c
View file

@ -339,14 +339,14 @@ static int gpio_sifive_init(struct device *dev)
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
/* Ensure that all gpio registers are reset to 0 initially */
gpio->in_en = 0;
gpio->out_en = 0;
gpio->pue = 0;
gpio->rise_ie = 0;
gpio->fall_ie = 0;
gpio->high_ie = 0;
gpio->low_ie = 0;
gpio->invert = 0;
gpio->in_en = 0U;
gpio->out_en = 0U;
gpio->pue = 0U;
gpio->rise_ie = 0U;
gpio->fall_ie = 0U;
gpio->high_ie = 0U;
gpio->low_ie = 0U;
gpio->invert = 0U;
/* Setup IRQ handler for each gpio pin */
cfg->gpio_cfg_func();

20
drivers/i2c/i2c_atmel_sam3.c
View file

@ -131,13 +131,13 @@ static u32_t clk_div_calc(struct device *dev)
switch (I2C_SPEED_GET(dev_data->dev_config)) {
case I2C_SPEED_STANDARD:
i2c_clk = 100000 * 2;
i2c_h_min_time = 4000;
i2c_l_min_time = 4700;
i2c_h_min_time = 4000U;
i2c_l_min_time = 4700U;
break;
case I2C_SPEED_FAST:
i2c_clk = 400000 * 2;
i2c_h_min_time = 600;
i2c_l_min_time = 1300;
i2c_h_min_time = 600U;
i2c_l_min_time = 1300U;
break;
default:
/* Return 0 as error */
@ -159,7 +159,7 @@ static u32_t clk_div_calc(struct device *dev)
cldiv_min = (i2c_l_min_time * mck / 1000) - 4 + 1;
chdiv_min = (i2c_h_min_time * mck / 1000) - 4 + 1;
ckdiv = 0;
ckdiv = 0U;
while (cldiv > 255) {
ckdiv++;
@ -195,7 +195,7 @@ static int i2c_sam3_runtime_configure(struct device *dev, u32_t config)
u32_t clk;
dev_data->dev_config = config;
reg = 0;
reg = 0U;
/* Calculate clock dividers */
clk = clk_div_calc(dev);
@ -288,7 +288,7 @@ static inline void transfer_setup(struct device *dev, u16_t slave_address)
/* 7-bit slave addressing */
mmr = TWI_MMR_DADR(slave_address);
iadr = 0;
iadr = 0U;
}
cfg->regs->TWI_MMR = mmr;
@ -361,7 +361,7 @@ static inline int msg_read(struct device *dev)
* reading from slave. If the previous message is also read,
* there is no need to set the START bit again.
*/
ctrl_reg = 0;
ctrl_reg = 0U;
if (dev_data->xfr_flags & I2C_MSG_RESTART) {
ctrl_reg = TWI_CR_START;
}
@ -390,7 +390,7 @@ static inline int msg_read(struct device *dev)
if (dev_data->xfr_len > 1) {
last_len = dev_data->xfr_len - 1;
} else {
last_len = 1;
last_len = 1U;
/* Set STOP bit for last byte.
* The extra check here is to prevent setting
@ -453,7 +453,7 @@ static int i2c_sam3_transfer(struct device *dev,
struct i2c_sam3_dev_data * const dev_data = dev->driver_data;
struct i2c_msg *cur_msg = msgs;
u8_t msg_left = num_msgs;
u32_t pflags = 0;
u32_t pflags = 0U;
int ret = 0;
int xfr_ret;

2
drivers/i2c/i2c_bitbang.c
View file

@ -172,7 +172,7 @@ static bool i2c_write_byte(struct i2c_bitbang *context, u8_t byte)
static u8_t i2c_read_byte(struct i2c_bitbang *context)
{
unsigned int byte = 1;
unsigned int byte = 1U;
do {
byte <<= 1;

4
drivers/i2c/i2c_cc32xx.c
View file

@ -94,10 +94,10 @@ static int i2c_cc32xx_configure(struct device *dev, u32_t dev_config_raw)
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
bitrate_id = 0;
bitrate_id = 0U;
break;
case I2C_SPEED_FAST:
bitrate_id = 1;
bitrate_id = 1U;
break;
default:
return -EINVAL;

40
drivers/i2c/i2c_dw.c
View file

@ -51,7 +51,7 @@ static inline void _i2c_dw_data_ask(struct device *dev)
/* No more bytes to request, so command queue is no longer needed */
if (dw->request_bytes == 0) {
regs->ic_intr_mask.bits.tx_empty = 0;
regs->ic_intr_mask.bits.tx_empty = 0U;
return;
}
@ -126,14 +126,14 @@ static void _i2c_dw_data_read(struct device *dev)
static int _i2c_dw_data_send(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
u32_t data = 0;
u32_t data = 0U;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;
/* Nothing to send anymore, mask the interrupt */
if (dw->xfr_len == 0) {
regs->ic_intr_mask.bits.tx_empty = 0;
regs->ic_intr_mask.bits.tx_empty = 0U;
dw->state &= ~I2C_DW_CMD_SEND;
@ -282,13 +282,13 @@ static int _i2c_dw_setup(struct device *dev, u16_t slave_address)
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;
ic_con.raw = 0;
ic_con.raw = 0U;
/* Disable the device controller to be able set TAR */
regs->ic_enable.bits.enable = 0;
regs->ic_enable.bits.enable = 0U;
/* Disable interrupts */
regs->ic_intr_mask.raw = 0;
regs->ic_intr_mask.raw = 0U;
/* Clear interrupts */
value = regs->ic_clr_intr;
@ -300,19 +300,19 @@ static int _i2c_dw_setup(struct device *dev, u16_t slave_address)
* to both 0 or both 1
*/
LOG_DBG("I2C: host configured as Master Device");
ic_con.bits.master_mode = 1;
ic_con.bits.slave_disable = 1;
ic_con.bits.master_mode = 1U;
ic_con.bits.slave_disable = 1U;
} else {
return -EINVAL;
}
ic_con.bits.restart_en = 1;
ic_con.bits.restart_en = 1U;
/* Set addressing mode - (initialization = 7 bit) */
if (I2C_ADDR_10_BITS & dw->app_config) {
LOG_DBG("I2C: using 10-bit address");
ic_con.bits.addr_master_10bit = 1;
ic_con.bits.addr_slave_10bit = 1;
ic_con.bits.addr_master_10bit = 1U;
ic_con.bits.addr_slave_10bit = 1U;
}
/* Setup the clock frequency and speed mode */
@ -361,7 +361,7 @@ static int _i2c_dw_setup(struct device *dev, u16_t slave_address)
*
* TODO: extend the threshold for multi-byte RX.
*/
regs->ic_rx_tl = 0;
regs->ic_rx_tl = 0U;
/* Set TX fifo threshold level.
* TX_EMPTY interrupt is triggered only when the
@ -371,7 +371,7 @@ static int _i2c_dw_setup(struct device *dev, u16_t slave_address)
* cause some pauses during transfers, but this keeps
* the device from interrupting often.
*/
regs->ic_tx_tl = 0;
regs->ic_tx_tl = 0U;
if (regs->ic_con.bits.master_mode) {
/* Set address of target slave */
@ -388,9 +388,9 @@ static int _i2c_dw_setup(struct device *dev, u16_t slave_address)
*/
if (I2C_MODE_MASTER & dw->app_config) {
if (I2C_ADDR_10_BITS & dw->app_config) {
regs->ic_tar.bits.ic_10bitaddr_master = 1;
regs->ic_tar.bits.ic_10bitaddr_master = 1U;
} else {
regs->ic_tar.bits.ic_10bitaddr_master = 0;
regs->ic_tar.bits.ic_10bitaddr_master = 0U;
}
}
@ -429,7 +429,7 @@ static int i2c_dw_transfer(struct device *dev,
}
/* Enable controller */
regs->ic_enable.bits.enable = 1;
regs->ic_enable.bits.enable = 1U;
/*
* While waiting at device_sync_sem, kernel can switch to idle
@ -452,7 +452,7 @@ static int i2c_dw_transfer(struct device *dev,
dw->xfr_buf = cur_msg->buf;
dw->xfr_len = cur_msg->len;
dw->xfr_flags = cur_msg->flags;
dw->rx_pending = 0;
dw->rx_pending = 0U;
/* Need to RESTART if changing transfer direction */
if ((pflags & I2C_MSG_RW_MASK)
@ -469,7 +469,7 @@ static int i2c_dw_transfer(struct device *dev,
if ((dw->xfr_flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
dw->state |= I2C_DW_CMD_SEND;
dw->request_bytes = 0;
dw->request_bytes = 0U;
} else {
dw->state |= I2C_DW_CMD_RECV;
dw->request_bytes = dw->xfr_len;
@ -513,8 +513,8 @@ static int i2c_dw_transfer(struct device *dev,
static int i2c_dw_runtime_configure(struct device *dev, u32_t config)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
u32_t value = 0;
u32_t rc = 0;
u32_t value = 0U;
u32_t rc = 0U;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;

10
drivers/i2c/i2c_esp32.c
View file

@ -170,7 +170,7 @@ static int i2c_esp32_configure(struct device *dev, u32_t dev_config)
const struct i2c_esp32_config *config = dev->config->config_info;
struct i2c_esp32_data *data = dev->driver_data;
unsigned int key = irq_lock();
u32_t v = 0;
u32_t v = 0U;
int ret;
ret = i2c_esp32_configure_pins(config->pins.scl,
@ -344,7 +344,7 @@ i2c_esp32_write_addr(struct device *dev,
{
const struct i2c_esp32_config *config = dev->config->config_info;
struct i2c_esp32_data *data = dev->driver_data;
u32_t addr_len = 1;
u32_t addr_len = 1U;
i2c_esp32_reset_fifo(config);
@ -437,7 +437,7 @@ static int i2c_esp32_read_msg(struct device *dev, u16_t addr,
return ret;
}
for (i = 0; i < to_read; i++) {
for (i = 0U; i < to_read; i++) {
u32_t v = sys_read32(I2C_DATA_APB_REG(config->index));
*msg.buf++ = v & I2C_FIFO_RDATA;
@ -469,7 +469,7 @@ static int i2c_esp32_write_msg(struct device *dev, u16_t addr,
int ret;
/* Copy data to TX fifo */
for (i = 0; i < to_send; i++) {
for (i = 0U; i < to_send; i++) {
sys_write32(*msg.buf++,
I2C_DATA_APB_REG(config->index));
}
@ -514,7 +514,7 @@ static int i2c_esp32_transfer(struct device *dev, struct i2c_msg *msgs,
addr &= BIT_MASK(data->dev_config & I2C_ADDR_10_BITS ? 10 : 7);
addr <<= 1;
for (i = 0; i < num_msgs; i++) {
for (i = 0U; i < num_msgs; i++) {
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = i2c_esp32_write_msg(dev, addr, msgs[i]);
} else {

2
drivers/i2c/i2c_gecko.c
View file

@ -95,7 +95,7 @@ static int i2c_gecko_transfer(struct device *dev, struct i2c_msg *msgs,
struct i2c_gecko_data *data = DEV_DATA(dev);
I2C_TransferSeq_TypeDef seq;
I2C_TransferReturn_TypeDef ret = -EIO;
u32_t timeout = 300000;
u32_t timeout = 300000U;
if (!num_msgs) {
return 0;

2
drivers/i2c/i2c_gpio.c
View file

@ -58,7 +58,7 @@ static void i2c_gpio_set_sda(void *io_context, int state)
static int i2c_gpio_get_sda(void *io_context)
{
struct i2c_gpio_context *context = io_context;
u32_t state = 1; /* Default high as that would be a NACK */
u32_t state = 1U; /* Default high as that would be a NACK */
gpio_pin_read(context->gpio, context->sda_pin, &state);
return state;

2
drivers/i2c/i2c_handlers.c
View file

@ -29,7 +29,7 @@ static u32_t copy_msgs_and_transfer(struct device *dev,
/* Validate the buffers in each message struct. Read options require
* that the target buffer be writable
*/
for (i = 0; i < num_msgs; i++) {
for (i = 0U; i < num_msgs; i++) {
Z_OOPS(Z_SYSCALL_MEMORY(copy[i].buf, copy[i].len,
copy[i].flags & I2C_MSG_READ));
}

6
drivers/i2c/i2c_imx.c
View file

@ -135,9 +135,9 @@ static int i2c_imx_configure(struct device *dev, u32_t dev_config_raw)
/* Initialize I2C state structure content. */
transfer->txBuff = 0;
transfer->rxBuff = 0;
transfer->cmdSize = 0;
transfer->txSize = 0;
transfer->rxSize = 0;
transfer->cmdSize = 0U;
transfer->txSize = 0U;
transfer->rxSize = 0U;
transfer->isBusy = false;
transfer->currentDir = i2cDirectionReceive;
transfer->currentMode = i2cModeSlave;

2
drivers/i2c/i2c_ll_stm32.c
View file

@ -25,7 +25,7 @@ int i2c_stm32_runtime_configure(struct device *dev, u32_t config)
const struct i2c_stm32_config *cfg = DEV_CFG(dev);
struct i2c_stm32_data *data = DEV_DATA(dev);
I2C_TypeDef *i2c = cfg->i2c;
u32_t clock = 0;
u32_t clock = 0U;
#if defined(CONFIG_SOC_SERIES_STM32F3X) || defined(CONFIG_SOC_SERIES_STM32F0X)
LL_RCC_ClocksTypeDef rcc_clocks;

34
drivers/i2c/i2c_ll_stm32_v1.c
View file

@ -36,10 +36,10 @@ static inline void handle_sb(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
u8_t header = slave | HEADER;
if (data->current.is_restart == 0) {
data->current.is_restart = 1;
data->current.is_restart = 1U;
} else {
header |= I2C_REQUEST_READ;
data->current.is_restart = 0;
data->current.is_restart = 0U;
}
LL_I2C_TransmitData8(i2c, header);
@ -57,7 +57,7 @@ static inline void handle_addr(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
{
if (I2C_ADDR_10_BITS & data->dev_config) {
if (!data->current.is_write && data->current.is_restart) {
data->current.is_restart = 0;
data->current.is_restart = 0U;
LL_I2C_ClearFlag_ADDR(i2c);
LL_I2C_GenerateStartCondition(i2c);
@ -139,7 +139,7 @@ static inline void handle_btf(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
if (data->current.is_write) {
handle_txe(i2c, data);
} else {
u32_t counter = 0;
u32_t counter = 0U;
switch (data->current.len) {
case 2:
@ -151,7 +151,7 @@ static inline void handle_btf(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
LL_I2C_GenerateStopCondition(i2c);
}
for (counter = 2; counter > 0; counter--) {
for (counter = 2U; counter > 0; counter--) {
data->current.len--;
*data->current.buf = LL_I2C_ReceiveData8(i2c);
data->current.buf++;
@ -201,12 +201,12 @@ void stm32_i2c_error_isr(void *arg)
if (LL_I2C_IsActiveFlag_AF(i2c)) {
LL_I2C_ClearFlag_AF(i2c);
LL_I2C_GenerateStopCondition(i2c);
data->current.is_nack = 1;
data->current.is_nack = 1U;
k_sem_give(&data->device_sync_sem);
return;
}
data->current.is_err = 1;
data->current.is_err = 1U;
k_sem_give(&data->device_sync_sem);
}
@ -223,10 +223,10 @@ s32_t stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
data->current.len = msg->len;
data->current.buf = msg->buf;
data->current.flags = msg->flags;
data->current.is_restart = 0;
data->current.is_write = 1;
data->current.is_nack = 0;
data->current.is_err = 0;
data->current.is_restart = 0U;
data->current.is_write = 1U;
data->current.is_nack = 0U;
data->current.is_err = 0U;
data->slave_address = saddr;
LL_I2C_EnableIT_EVT(i2c);
@ -249,8 +249,8 @@ s32_t stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
LOG_DBG("%s: ERR %d", __func__,
data->current.is_err);
data->current.is_nack = 0;
data->current.is_err = 0;
data->current.is_nack = 0U;
data->current.is_err = 0U;
ret = -EIO;
}
@ -273,9 +273,9 @@ s32_t stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
data->current.len = msg->len;
data->current.buf = msg->buf;
data->current.flags = msg->flags;
data->current.is_restart = 0;
data->current.is_write = 0;
data->current.is_err = 0;
data->current.is_restart = 0U;
data->current.is_write = 0U;
data->current.is_err = 0U;
data->slave_address = saddr;
LL_I2C_EnableIT_EVT(i2c);
@ -289,7 +289,7 @@ s32_t stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
LL_I2C_DisableIT_BUF(i2c);
if (data->current.is_err) {
LOG_DBG("%s: ERR %d", __func__, data->current.is_err);
data->current.is_err = 0;
data->current.is_err = 0U;
ret = -EIO;
}

56
drivers/i2c/i2c_ll_stm32_v2.c
View file

@ -283,7 +283,7 @@ static void stm32_i2c_event(struct device *dev)
/* NACK received */
if (LL_I2C_IsActiveFlag_NACK(i2c)) {
LL_I2C_ClearFlag_NACK(i2c);
data->current.is_nack = 1;
data->current.is_nack = 1U;
goto end;
}
@ -326,13 +326,13 @@ static int stm32_i2c_error(struct device *dev)
if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
LL_I2C_ClearFlag_ARLO(i2c);
data->current.is_arlo = 1;
data->current.is_arlo = 1U;
goto end;
}
if (LL_I2C_IsActiveFlag_BERR(i2c)) {
LL_I2C_ClearFlag_BERR(i2c);
data->current.is_err = 1;
data->current.is_err = 1U;
goto end;
}
@ -378,9 +378,9 @@ int stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
data->current.len = msg->len;
data->current.buf = msg->buf;
data->current.is_write = 1;
data->current.is_nack = 0;
data->current.is_err = 0;
data->current.is_write = 1U;
data->current.is_nack = 0U;
data->current.is_err = 0U;
data->current.msg = msg;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
@ -400,18 +400,18 @@ error:
if (data->current.is_arlo) {
LOG_DBG("%s: ARLO %d", __func__,
data->current.is_arlo);
data->current.is_arlo = 0;
data->current.is_arlo = 0U;
}
if (data->current.is_nack) {
LOG_DBG("%s: NACK", __func__);
data->current.is_nack = 0;
data->current.is_nack = 0U;
}
if (data->current.is_err) {
LOG_DBG("%s: ERR %d", __func__,
data->current.is_err);
data->current.is_err = 0;
data->current.is_err = 0U;
}
return -EIO;
@ -426,10 +426,10 @@ int stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
data->current.len = msg->len;
data->current.buf = msg->buf;
data->current.is_write = 0;
data->current.is_arlo = 0;
data->current.is_err = 0;
data->current.is_nack = 0;
data->current.is_write = 0U;
data->current.is_arlo = 0U;
data->current.is_err = 0U;
data->current.is_nack = 0U;
data->current.msg = msg;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
@ -449,18 +449,18 @@ error:
if (data->current.is_arlo) {
LOG_DBG("%s: ARLO %d", __func__,
data->current.is_arlo);
data->current.is_arlo = 0;
data->current.is_arlo = 0U;
}
if (data->current.is_nack) {
LOG_DBG("%s: NACK", __func__);
data->current.is_nack = 0;
data->current.is_nack = 0U;
}
if (data->current.is_err) {
LOG_DBG("%s: ERR %d", __func__,
data->current.is_err);
data->current.is_err = 0;
data->current.is_err = 0U;
}
return -EIO;
@ -492,7 +492,7 @@ int stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
{
const struct i2c_stm32_config *cfg = DEV_CFG(dev);
I2C_TypeDef *i2c = cfg->i2c;
unsigned int len = 0;
unsigned int len = 0U;
u8_t *buf = msg->buf;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
@ -529,7 +529,7 @@ int stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
{
const struct i2c_stm32_config *cfg = DEV_CFG(dev);
I2C_TypeDef *i2c = cfg->i2c;
unsigned int len = 0;
unsigned int len = 0U;
u8_t *buf = msg->buf;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
@ -558,21 +558,21 @@ int stm32_i2c_configure_timing(struct device *dev, u32_t clock)
I2C_TypeDef *i2c = cfg->i2c;
u32_t i2c_hold_time_min, i2c_setup_time_min;
u32_t i2c_h_min_time, i2c_l_min_time;
u32_t presc = 1;
u32_t timing = 0;
u32_t presc = 1U;
u32_t timing = 0U;
switch (I2C_SPEED_GET(data->dev_config)) {
case I2C_SPEED_STANDARD:
i2c_h_min_time = 4000;
i2c_l_min_time = 4700;
i2c_hold_time_min = 500;
i2c_setup_time_min = 1250;
i2c_h_min_time = 4000U;
i2c_l_min_time = 4700U;
i2c_hold_time_min = 500U;
i2c_setup_time_min = 1250U;
break;
case I2C_SPEED_FAST:
i2c_h_min_time = 600;
i2c_l_min_time = 1300;
i2c_hold_time_min = 375;
i2c_setup_time_min = 500;
i2c_h_min_time = 600U;
i2c_l_min_time = 1300U;
i2c_hold_time_min = 375U;
i2c_setup_time_min = 500U;
break;
default:
return -EINVAL;

2
drivers/i2c/i2c_mcux.c
View file

@ -83,7 +83,7 @@ static void i2c_mcux_master_transfer_callback(I2C_Type *base,
static u32_t i2c_mcux_convert_flags(int msg_flags)
{
u32_t flags = 0;
u32_t flags = 0U;
if (!(msg_flags & I2C_MSG_STOP)) {
flags |= kI2C_TransferNoStopFlag;

4
drivers/i2c/i2c_qmsi_ss.c
View file

@ -127,7 +127,7 @@ DEVICE_DEFINE(i2c_ss_0, DT_I2C_SS_0_NAME, i2c_qmsi_ss_init,
static void i2c_qmsi_ss_config_irq_0(void)
{
u32_t mask = 0;
u32_t mask = 0U;
/* Need to unmask the interrupts in System Control Subsystem (SCSS)
* so the interrupt controller can route these interrupts to
@ -184,7 +184,7 @@ DEVICE_DEFINE(i2c_ss_1, DT_I2C_SS_1_NAME, i2c_qmsi_ss_init,
static void i2c_qmsi_ss_config_irq_1(void)
{
u32_t mask = 0;
u32_t mask = 0U;
/* Need to unmask the interrupts in System Control Subsystem (SCSS)
* so the interrupt controller can route these interrupts to

6
drivers/i2c/i2c_sam_twi.c
View file

@ -72,7 +72,7 @@ struct i2c_sam_twi_dev_data {
static int i2c_clk_set(Twi *const twi, u32_t speed)
{
u32_t ck_div = 0;
u32_t ck_div = 0U;
u32_t cl_div;
bool div_completed = false;
@ -197,8 +197,8 @@ static int i2c_sam_twi_transfer(struct device *dev, struct i2c_msg *msgs,
for (; num_msgs > 0; num_msgs--, msgs++) {
dev_data->msg.buf = msgs->buf;
dev_data->msg.len = msgs->len;
dev_data->msg.idx = 0;
dev_data->msg.twi_sr = 0;
dev_data->msg.idx = 0U;
dev_data->msg.twi_sr = 0U;
dev_data->msg.flags = msgs->flags;
/*

6
drivers/i2c/i2c_sam_twihs.c
View file

@ -72,7 +72,7 @@ struct i2c_sam_twihs_dev_data {
static int i2c_clk_set(Twihs *const twihs, u32_t speed)
{
u32_t ck_div = 0;
u32_t ck_div = 0U;
u32_t cl_div;
bool div_completed = false;
@ -199,8 +199,8 @@ static int i2c_sam_twihs_transfer(struct device *dev, struct i2c_msg *msgs,
for (int i = 0; i < num_msgs; i++) {
dev_data->msg.buf = msgs[i].buf;
dev_data->msg.len = msgs[i].len;
dev_data->msg.idx = 0;
dev_data->msg.twihs_sr = 0;
dev_data->msg.idx = 0U;
dev_data->msg.twihs_sr = 0U;
dev_data->msg.flags = msgs[i].flags;
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
read_msg_start(twihs, &dev_data->msg, addr);

14
drivers/i2s/i2s_cavs.c
View file

@ -259,11 +259,11 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
u32_t sstsa;
u32_t ssrsa;
u32_t ssto;
u32_t ssioc = 0;
u32_t ssioc = 0U;
u32_t mdiv;
u32_t i2s_m = 0;
u32_t i2s_n = 0;
u32_t frame_len = 0;
u32_t i2s_m = 0U;
u32_t i2s_n = 0U;
u32_t frame_len = 0U;
bool inverted_frame = false;
if ((dev_data->tx.state != I2S_STATE_NOT_READY) &&
@ -308,14 +308,14 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
ssc1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL | SSCR1_TSRE | SSCR1_RSRE;
/* sscr2 dynamic setting is LJDFD */
ssc2 = 0;
ssc2 = 0U;
/* sscr3 dynamic settings are TFT, RFT */
ssc3 = SSCR3_TX(CAVS_I2S_DMA_BURST_SIZE) |
SSCR3_RX(CAVS_I2S_DMA_BURST_SIZE);
/* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */
sspsp = 0;
sspsp = 0U;
/* sspsp2 no dynamic setting */
sspsp2 = 0x0;
@ -384,7 +384,7 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
i2s_n = mclk / 100;
/* set divider value of 1 which divides the clock by 2 */
mdiv = 1;
mdiv = 1U;
/* Select M/N divider as the clock source */
ssc0 |= SSCR0_ECS;

2
drivers/i2s/i2s_ll_stm32.c
View file

@ -775,7 +775,7 @@ static void tx_queue_drop(struct stream *stream)
{
size_t size;
void *mem_block;
unsigned int n = 0;
unsigned int n = 0U;
while (queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) {
k_mem_slab_free(stream->cfg.mem_slab, &mem_block);

18
drivers/i2s/i2s_sam_ssc.c
View file

@ -310,15 +310,15 @@ static int set_rx_data_format(const struct i2s_sam_dev_cfg *const dev_cfg,
const bool pin_rf_en = IS_ENABLED(CONFIG_I2S_SAM_SSC_0_PIN_RF_EN);
u8_t word_size_bits = i2s_cfg->word_size;
u8_t num_words = i2s_cfg->channels;
u8_t fslen = 0;
u32_t ssc_rcmr = 0;
u32_t ssc_rfmr = 0;
u8_t fslen = 0U;
u32_t ssc_rcmr = 0U;
u32_t ssc_rfmr = 0U;
bool frame_clk_master = !(i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE);
switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) {
case I2S_FMT_DATA_FORMAT_I2S:
num_words = 2;
num_words = 2U;
fslen = word_size_bits - 1;
ssc_rcmr = SSC_RCMR_CKI
@ -401,14 +401,14 @@ static int set_tx_data_format(const struct i2s_sam_dev_cfg *const dev_cfg,
Ssc *const ssc = dev_cfg->regs;
u8_t word_size_bits = i2s_cfg->word_size;
u8_t num_words = i2s_cfg->channels;
u8_t fslen = 0;
u32_t ssc_tcmr = 0;
u32_t ssc_tfmr = 0;
u8_t fslen = 0U;
u32_t ssc_tcmr = 0U;
u32_t ssc_tfmr = 0U;
switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) {
case I2S_FMT_DATA_FORMAT_I2S:
num_words = 2;
num_words = 2U;
fslen = word_size_bits - 1;
ssc_tcmr = SSC_TCMR_START_TF_FALLING
@ -729,7 +729,7 @@ static void tx_queue_drop(struct stream *stream)
{
size_t size;
void *mem_block;
unsigned int n = 0;
unsigned int n = 0U;
while (queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) {
k_mem_slab_free(stream->cfg.mem_slab, &mem_block);

8
drivers/ieee802154/ieee802154_cc1200.c
View file

@ -99,7 +99,7 @@ bool _cc1200_access_reg(struct cc1200_context *ctx, bool read, u8_t addr,
burst ? "burst" : "single");
*/
cmd_buf[0] = 0;
cmd_buf[0] = 0U;
if (burst) {
cmd_buf[0] |= CC1200_ACCESS_BURST;
@ -276,9 +276,9 @@ static bool write_reg_freq(struct cc1200_context *ctx, u32_t freq)
static u32_t rf_evaluate_freq_setting(struct cc1200_context *ctx, u32_t chan)
{
u32_t xtal = CONFIG_IEEE802154_CC1200_XOSC;
u32_t mult_10 = 100000;
u32_t factor = 1;
u32_t freq = 0;
u32_t mult_10 = 100000U;
u32_t factor = 1U;
u32_t freq = 0U;
u32_t rf, lo_div;
rf = ctx->rf_settings->chan_center_freq0 +

16
drivers/ieee802154/ieee802154_cc2520.c
View file

@ -261,7 +261,7 @@ static inline u8_t _cc2520_status(struct cc2520_context *ctx)
static bool verify_osc_stabilization(struct cc2520_context *cc2520)
{
u8_t timeout = 100;
u8_t timeout = 100U;
u8_t status;
do {
@ -499,7 +499,7 @@ static inline bool verify_txfifo_status(struct cc2520_context *cc2520,
static inline bool verify_tx_done(struct cc2520_context *cc2520)
{
u8_t timeout = 10;
u8_t timeout = 10U;
u8_t status;
do {
@ -575,9 +575,9 @@ static inline void insert_radio_noise_details(struct net_pkt *pkt, u8_t *buf)
*/
lqi = buf[1] & CC2520_FCS_CORRELATION;
if (lqi <= 50) {
lqi = 0;
lqi = 0U;
} else if (lqi >= 110) {
lqi = 255;
lqi = 255U;
} else {
lqi = (lqi - 50) << 2;
}
@ -816,7 +816,7 @@ static int cc2520_tx(struct device *dev,
u8_t *frame = frag->data - net_pkt_ll_reserve(pkt);
u8_t len = net_pkt_ll_reserve(pkt) + frag->len;
struct cc2520_context *cc2520 = dev->driver_data;
u8_t retry = 2;
u8_t retry = 2U;
bool status;
LOG_DBG("%p (%u)", frag, len);
@ -1195,7 +1195,7 @@ static int insert_crypto_parameters(struct cipher_ctx *ctx,
u8_t data[128];
u8_t *in_buf;
u8_t in_len;
u8_t m = 0;
u8_t m = 0U;
if (!apkt->pkt->out_buf || !apkt->pkt->out_buf_max) {
LOG_ERR("Out buffer needs to be set");
@ -1231,7 +1231,7 @@ static int insert_crypto_parameters(struct cipher_ctx *ctx,
in_buf = apkt->ad;
in_len = apkt->ad_len;
*auth_crypt = 0;
*auth_crypt = 0U;
} else {
in_buf = data;
@ -1246,7 +1246,7 @@ static int insert_crypto_parameters(struct cipher_ctx *ctx,
if (ctx->mode_params.ccm_info.tag_len) {
if ((ctx->mode_params.ccm_info.tag_len >> 2) > 3) {
m = 3;
m = 3U;
} else {
m = ctx->mode_params.ccm_info.tag_len >> 2;
}

24
drivers/ieee802154/ieee802154_kw41z.c
View file

@ -647,7 +647,7 @@ static void kw41z_isr(int unused)
{
u32_t irqsts = ZLL->IRQSTS;
u8_t state = kw41z_get_seq_state();
u8_t restart_rx = 1;
u8_t restart_rx = 1U;
u32_t rx_len;
/*
@ -676,7 +676,7 @@ static void kw41z_isr(int unused)
(unsigned int)ZLL->PHY_CTRL,
(unsigned int)seq_state, state);
restart_rx = 0;
restart_rx = 0U;
} else if ((!(ZLL->PHY_CTRL & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)) &&
(irqsts & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)) {
@ -713,7 +713,7 @@ static void kw41z_isr(int unused)
rx_len = rx_len * 2 + 12 + 22 + 2;
kw41z_tmr3_set_timeout(rx_len);
}
restart_rx = 0;
restart_rx = 0U;
}
/* Sequence done IRQ */
@ -725,7 +725,7 @@ static void kw41z_isr(int unused)
if (irqsts & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK) {
LOG_ERR("PLL unlock error");
kw41z_isr_seq_cleanup();
restart_rx = 1;
restart_rx = 1U;
}
/*
* TMR3 timeout, the autosequence has been aborted due to
@ -745,7 +745,7 @@ static void kw41z_isr(int unused)
(unsigned int)ZLL->PHY_CTRL, seq_state);
kw41z_isr_timeout_cleanup();
restart_rx = 1;
restart_rx = 1U;
if (state == KW41Z_STATE_TXRX) {
/* TODO: What is the right error for no ACK? */
@ -776,7 +776,7 @@ static void kw41z_isr(int unused)
rx_len);
}
}
restart_rx = 1;
restart_rx = 1U;
break;
case KW41Z_STATE_TXRX:
LOG_DBG("TXRX seq done");
@ -796,7 +796,7 @@ static void kw41z_isr(int unused)
}
k_sem_give(&kw41z_context_data.seq_sync);
restart_rx = 1;
restart_rx = 1U;
break;
case KW41Z_STATE_CCA:
@ -807,19 +807,19 @@ static void kw41z_isr(int unused)
atomic_set(
&kw41z_context_data.seq_retval,
-EBUSY);
restart_rx = 1;
restart_rx = 1U;
} else {
atomic_set(
&kw41z_context_data.seq_retval,
0);
restart_rx = 0;
restart_rx = 0U;
}
k_sem_give(&kw41z_context_data.seq_sync);
break;
default:
LOG_DBG("Unhandled state: %d", state);
restart_rx = 1;
restart_rx = 1U;
break;
}
}
@ -833,10 +833,10 @@ static void kw41z_isr(int unused)
irqsts, seq_state, state);
kw41z_tmr3_disable();
restart_rx = 0;
restart_rx = 0U;
if (state != KW41Z_STATE_IDLE) {
kw41z_isr_timeout_cleanup();
restart_rx = 1;
restart_rx = 1U;
/* If we are not running an automated
* sequence then handle event. TMR3 can expire
* during Recv/Ack sequence where the transmit

12
drivers/ieee802154/ieee802154_mcr20a.c
View file

@ -278,7 +278,7 @@ static int mcr20a_timer_set(struct mcr20a_context *mcr20a,
u8_t cmp_reg,
u32_t timeout)
{
u32_t now = 0;
u32_t now = 0U;
u32_t next;
bool retval;
@ -455,7 +455,7 @@ static inline int mcr20a_abort_sequence(struct mcr20a_context *mcr20a,
static inline int mcr20a_set_sequence(struct mcr20a_context *mcr20a,
u8_t seq)
{
u8_t ctrl1 = 0;
u8_t ctrl1 = 0U;
seq = set_bits_phy_ctrl1_xcvseq(seq);
ctrl1 = read_reg_phy_ctrl1(mcr20a);
@ -720,7 +720,7 @@ static void mcr20a_thread_main(void *arg)
struct mcr20a_context *mcr20a = dev->driver_data;
u8_t dregs[MCR20A_PHY_CTRL4 + 1];
bool set_new_seq;
u8_t ctrl1 = 0;
u8_t ctrl1 = 0U;
while (true) {
k_sem_take(&mcr20a->isr_sem, K_FOREVER);
@ -1153,7 +1153,7 @@ error:
static int mcr20a_start(struct device *dev)
{
struct mcr20a_context *mcr20a = dev->driver_data;
u8_t timeout = 6;
u8_t timeout = 6U;
u8_t status;
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
@ -1275,9 +1275,9 @@ error:
static int power_on_and_setup(struct device *dev)
{
struct mcr20a_context *mcr20a = dev->driver_data;
u8_t timeout = 6;
u8_t timeout = 6U;
u32_t status;
u8_t tmp = 0;
u8_t tmp = 0U;
if (!PART_OF_KW2XD_SIP) {
set_reset(dev, 0);

6
drivers/ieee802154/ieee802154_uart_pipe.c
View file

@ -165,8 +165,8 @@ out:
net_pkt_unref(pkt);
flush:
upipe->rx = false;
upipe->rx_len = 0;
upipe->rx_off = 0;
upipe->rx_len = 0U;
upipe->rx_off = 0U;
}
done:
*off = 0;
@ -284,7 +284,7 @@ static int upipe_tx(struct device *dev,
data = len;
uart_pipe_send(&data, 1);
for (i = 0; i < len; i++) {
for (i = 0U; i < len; i++) {
uart_pipe_send(pkt_buf+i, 1);
}

4
drivers/interrupt_controller/arcv2_irq_unit.c
View file

@ -117,7 +117,7 @@ static int _arc_v2_irq_unit_suspend(struct device *dev)
* by IRQ auxiliary registers. For that reason we skip those
* values in this loop.
*/
for (irq = 16; irq < CONFIG_NUM_IRQS; irq++) {
for (irq = 16U; irq < CONFIG_NUM_IRQS; irq++) {
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
ctx.irq_config[irq - 16] =
_arc_v2_aux_reg_read(_ARC_V2_IRQ_PRIORITY) << 2;
@ -146,7 +146,7 @@ static int _arc_v2_irq_unit_resume(struct device *dev)
* by IRQ auxiliary registers. For that reason we skip those
* values in this loop.
*/
for (irq = 16; irq < CONFIG_NUM_IRQS; irq++) {
for (irq = 16U; irq < CONFIG_NUM_IRQS; irq++) {
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
#ifdef CONFIG_ARC_HAS_SECURE
_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY,

4
drivers/interrupt_controller/dw_ictl.c
View file

@ -39,8 +39,8 @@ static int dw_ictl_initialize(struct device *port)
(struct dw_ictl_registers *)dw->base_addr;
/* disable all interrupts */
regs->irq_inten_l = 0;
regs->irq_inten_h = 0;
regs->irq_inten_l = 0U;
regs->irq_inten_h = 0U;
return 0;
}

2
drivers/interrupt_controller/ioapic_intr.c
View file

@ -176,7 +176,7 @@ void store_flags(unsigned int irq, u32_t flags)
u32_t restore_flags(unsigned int irq)
{
u32_t flags = 0;
u32_t flags = 0U;
if (sys_bitfield_test_bit((mem_addr_t) ioapic_suspend_buf,
BIT_POS_FOR_IRQ_OPTION(irq, IOAPIC_BITFIELD_HI_LO))) {

6
drivers/interrupt_controller/plic.c
View file

@ -195,18 +195,18 @@ static int plic_init(struct device *dev)
/* Ensure that all interrupts are disabled initially */
for (i = 0; i < PLIC_EN_SIZE; i++) {
*en = 0;
*en = 0U;
en++;
}
/* Set priority of each interrupt line to 0 initially */
for (i = 0; i < PLIC_IRQS; i++) {
*prio = 0;
*prio = 0U;
prio++;
}
/* Set threshold priority to 0 */
regs->threshold_prio = 0;
regs->threshold_prio = 0U;
/* Setup IRQ handler for PLIC driver */
IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,

10
drivers/interrupt_controller/shared_irq.c
View file

@ -29,7 +29,7 @@ static int isr_register(struct device *dev, isr_t isr_func,
const struct shared_irq_config *config = dev->config->config_info;
u32_t i;
for (i = 0; i < config->client_count; i++) {
for (i = 0U; i < config->client_count; i++) {
if (!clients->client[i].isr_dev) {
clients->client[i].isr_dev = isr_dev;
clients->client[i].isr_func = isr_func;
@ -50,7 +50,7 @@ static inline int enable(struct device *dev, struct device *isr_dev)
const struct shared_irq_config *config = dev->config->config_info;
u32_t i;
for (i = 0; i < config->client_count; i++) {
for (i = 0U; i < config->client_count; i++) {
if (clients->client[i].isr_dev == isr_dev) {
clients->client[i].enabled = 1;
irq_enable(config->irq_num);
@ -64,7 +64,7 @@ static int last_enabled_isr(struct shared_irq_runtime *clients, int count)
{
u32_t i;
for (i = 0; i < count; i++) {
for (i = 0U; i < count; i++) {
if (clients->client[i].enabled) {
return 0;
}
@ -82,7 +82,7 @@ static inline int disable(struct device *dev, struct device *isr_dev)
const struct shared_irq_config *config = dev->config->config_info;
u32_t i;
for (i = 0; i < config->client_count; i++) {
for (i = 0U; i < config->client_count; i++) {
if (clients->client[i].isr_dev == isr_dev) {
clients->client[i].enabled = 0;
if (last_enabled_isr(clients, config->client_count)) {
@ -100,7 +100,7 @@ void shared_irq_isr(struct device *dev)
const struct shared_irq_config *config = dev->config->config_info;
u32_t i;
for (i = 0; i < config->client_count; i++) {
for (i = 0U; i < config->client_count; i++) {
if (clients->client[i].isr_dev) {
clients->client[i].isr_func(clients->client[i].isr_dev);
}

2
drivers/ipm/ipm_quark_se.c
View file

@ -203,7 +203,7 @@ int quark_se_ipm_controller_initialize(struct device *d)
for (i = 0; i < QUARK_SE_IPM_CHANNELS; ++i) {
volatile struct quark_se_ipm *ipm = QUARK_SE_IPM(i);
ipm->sts = 0;
ipm->sts = 0U;
}
#endif

8
drivers/led/lp3943.c
View file

@ -241,10 +241,10 @@ static int lp3943_led_init(struct device *dev)
}
/* Hardware specific limits */
dev_data->min_period = 0;
dev_data->max_period = 1600;
dev_data->min_brightness = 0;
dev_data->max_brightness = 100;
dev_data->min_period = 0U;
dev_data->max_period = 1600U;
dev_data->min_brightness = 0U;
dev_data->max_brightness = 100U;
return 0;
}

12
drivers/led/lp5562.c
View file

@ -239,13 +239,13 @@ static int lp5562_get_engine_reg_shift(enum lp5562_led_sources engine,
{
switch (engine) {
case LP5562_SOURCE_ENGINE_1:
*shift = 4;
*shift = 4U;
break;
case LP5562_SOURCE_ENGINE_2:
*shift = 2;
*shift = 2U;
break;
case LP5562_SOURCE_ENGINE_3:
*shift = 0;
*shift = 0U;
break;
default:
return -EINVAL;
@ -275,7 +275,7 @@ static void lp5562_ms_to_prescale_and_step(struct led_data *data, u32_t ms,
* the step_time value never goes above the allowed 63.
*/
if (ms < 31) {
*prescale = 0;
*prescale = 0U;
*step_time = ms << 1;
return;
@ -285,7 +285,7 @@ static void lp5562_ms_to_prescale_and_step(struct led_data *data, u32_t ms,
* With a prescaler value set to 1 one step takes 15.6ms. So by dividing
* through 16 we get a decent enough result with low effort.
*/
*prescale = 1;
*prescale = 1U;
*step_time = ms >> 4;
return;
@ -750,7 +750,7 @@ static int lp5562_led_blink(struct device *dev, u32_t led,
struct led_data *dev_data = &data->dev_data;
int ret;
enum lp5562_led_sources engine;
u8_t command_index = 0;
u8_t command_index = 0U;
ret = lp5562_get_available_engine(dev, &engine);
if (ret) {

8
drivers/led/pca9633.c
View file

@ -184,10 +184,10 @@ static int pca9633_led_init(struct device *dev)
}
/* Hardware specific limits */
dev_data->min_period = 41;
dev_data->max_period = 10667;
dev_data->min_brightness = 0;
dev_data->max_brightness = 100;
dev_data->min_period = 41U;
dev_data->max_period = 10667U;
dev_data->min_brightness = 0U;
dev_data->max_brightness = 100U;
return 0;
}

2
drivers/led_strip/ws2812b_sw.c
View file

@ -30,7 +30,7 @@ static int send_buf(u8_t *buf, size_t len)
/* Initilization of i is strictly not needed, but it avoids an
* uninitialized warning with the inline assembly.
*/
u32_t i = 0;
u32_t i = 0U;
clock = device_get_binding(CONFIG_CLOCK_CONTROL_NRF5_M16SRC_DRV_NAME);
if (!clock) {

14
drivers/modem/wncm14a2a.c
View file

@ -424,13 +424,13 @@ static void net_buf_skipcrlf(struct net_buf **buf)
static u16_t net_buf_findcrlf(struct net_buf *buf, struct net_buf **frag,
u16_t *offset)
{
u16_t len = 0, pos = 0;
u16_t len = 0U, pos = 0U;
while (buf && !is_crlf(*(buf->data + pos))) {
if (pos + 1 >= buf->len) {
len += buf->len;
buf = buf->frags;
pos = 0;
pos = 0U;
} else {
pos++;
}
@ -457,7 +457,7 @@ static int net_pkt_setup_ip_data(struct net_pkt *pkt,
struct wncm14a2a_socket *sock)
{
int hdr_len = 0;
u16_t src_port = 0, dst_port = 0;
u16_t src_port = 0U, dst_port = 0U;
#if defined(CONFIG_NET_IPV6)
if (net_pkt_family(pkt) == AF_INET6) {
@ -767,7 +767,7 @@ static void on_cmd_sockread(struct net_buf **buf, u16_t len)
{
struct wncm14a2a_socket *sock = NULL;
struct net_buf *frag;
u8_t c = 0;
u8_t c = 0U;
u16_t pos;
int i, actual_length, hdr_len = 0;
size_t value_size;
@ -868,7 +868,7 @@ static void on_cmd_sockread(struct net_buf **buf, u16_t len)
return;
}
c = 0;
c = 0U;
} else {
c = c << 4;
}
@ -1019,7 +1019,7 @@ static void on_cmd_socknotifyev(struct net_buf **buf, u16_t len)
static int net_buf_ncmp(struct net_buf *buf, const u8_t *s2, size_t n)
{
struct net_buf *frag = buf;
u16_t offset = 0;
u16_t offset = 0U;
while ((n > 0) && (*(frag->data + offset) == *s2) && (*s2 != '\0')) {
if (offset == frag->len) {
@ -1027,7 +1027,7 @@ static int net_buf_ncmp(struct net_buf *buf, const u8_t *s2, size_t n)
break;
}
frag = frag->frags;
offset = 0;
offset = 0U;
} else {
offset++;
}

6
drivers/net/slip.c
View file

@ -161,7 +161,7 @@ static int slip_send(struct device *dev, struct net_pkt *pkt)
/* This writes ethernet header */
if (!send_header_once && ll_reserve) {
for (i = 0; i < ll_reserve; i++) {
for (i = 0U; i < ll_reserve; i++) {
slip_writeb_esc(*ptr++);
}
}
@ -173,7 +173,7 @@ static int slip_send(struct device *dev, struct net_pkt *pkt)
* link layer header always.
*/
send_header_once = true;
ll_reserve = 0;
ll_reserve = 0U;
ptr = frag->data;
}
#else
@ -181,7 +181,7 @@ static int slip_send(struct device *dev, struct net_pkt *pkt)
ptr = frag->data;
#endif
for (i = 0; i < frag->len; ++i) {
for (i = 0U; i < frag->len; ++i) {
c = *ptr++;
slip_writeb_esc(c);
}

2
drivers/neural_net/intel_gna.c
View file

@ -158,7 +158,7 @@ static int intel_gna_setup_page_table(void *physical, size_t size,
return -EINVAL;
}
for (page = 0; page < GNA_NUM_PAGES(size); page++) {
for (page = 0U; page < GNA_NUM_PAGES(size); page++) {
dir_index = GNA_VA_PG_DIR(virt_addr);
table_index = GNA_VA_PG_TABLE(virt_addr);
gna_page_table[dir_index].entry[table_index] =

6
drivers/pci/pci_interface.c
View file

@ -257,7 +257,7 @@ void pci_read(u32_t controller, union pci_addr_reg addr,
case 4:
default:
access_size = SYS_PCI_ACCESS_32BIT;
access_offset = 0;
access_offset = 0U;
break;
}
@ -348,7 +348,7 @@ void pci_write(u32_t controller, union pci_addr_reg addr,
case 4:
default:
access_size = SYS_PCI_ACCESS_32BIT;
access_offset = 0;
access_offset = 0U;
break;
}
@ -389,7 +389,7 @@ void pci_header_get(u32_t controller,
/* fill in the PCI header from the device */
for (i = 0; i < PCI_HEADER_WORDS; i++) {
for (i = 0U; i < PCI_HEADER_WORDS; i++) {
pci_ctrl_addr.field.reg = i;
pci_read(controller,
pci_ctrl_addr,

2
drivers/pinmux/pinmux_esp32.c
View file

@ -163,7 +163,7 @@ static int pinmux_initialize(struct device *device)
{
u32_t pin;
for (pin = 0; pin < ARRAY_SIZE(pin_mux_off); pin++) {
for (pin = 0U; pin < ARRAY_SIZE(pin_mux_off); pin++) {
pinmux_set(NULL, pin, 0);
}

10
drivers/pwm/pwm_led_esp32.c
View file

@ -111,7 +111,7 @@ static u8_t pwm_led_esp32_get_gpio_config(u8_t pin,
{
u8_t i;
for (i = 0; i < 16; i++) {
for (i = 0U; i < 16; i++) {
if (ch_cfg[i].gpio == pin) {
return i;
}
@ -180,10 +180,10 @@ static void pwm_led_esp32_duty_set(int speed_mode, int channel, int duty_val)
{
union pwm_led_esp32_duty duty;
duty.start = 0;
duty.direction = 1;
duty.cycle = 1;
duty.scale = 0;
duty.start = 0U;
duty.direction = 1U;
duty.cycle = 1U;
duty.scale = 0U;
pwm_led_esp32_duty_config(speed_mode, channel, duty_val << 4, duty);
}

8
drivers/pwm/pwm_nrf5_sw.c
View file

@ -42,7 +42,7 @@ static u32_t pwm_period_check(struct pwm_data *data, u8_t map_size,
}
/* fail if requested period does not match already running period */
for (i = 0; i < map_size; i++) {
for (i = 0U; i < map_size; i++) {
if ((data->map[i].pwm != pwm) &&
(data->map[i].pulse_cycles != 0) &&
(period_cycles != data->period_cycles)) {
@ -59,7 +59,7 @@ static u8_t pwm_channel_map(struct pwm_data *data, u8_t map_size,
u8_t i;
/* find pin, if already present */
for (i = 0; i < map_size; i++) {
for (i = 0U; i < map_size; i++) {
if (pwm == data->map[i].pwm) {
return i;
}
@ -176,11 +176,11 @@ static int pwm_nrf5_sw_pin_set(struct device *dev, u32_t pwm,
return 0;
pin_set_pwm_off:
data->map[channel].pulse_cycles = 0;
data->map[channel].pulse_cycles = 0U;
bool pwm_active = false;
/* stop timer if all channels are inactive */
for (channel = 0; channel < config->map_size; channel++) {
for (channel = 0U; channel < config->map_size; channel++) {
if (data->map[channel].pulse_cycles) {
pwm_active = true;
break;

4
drivers/pwm/pwm_qmsi.c
View file

@ -80,7 +80,7 @@ static int __set_one_port(struct device *dev, qm_pwm_t id, u32_t pwm,
* turned off. Let's use the minimum value which is 1 for this case.
*/
if (off == 0) {
off = 1;
off = 1U;
}
/* PWM mode, user-defined count mode, timer disabled */
@ -149,7 +149,7 @@ static int pwm_qmsi_pin_set(struct device *dev, u32_t pwm,
*/
if (low == 0) {
high--;
low = 1;
low = 1U;
}
return __set_one_port(dev, QM_PWM_0, pwm, high, low);

2
drivers/sensor/adt7420/adt7420.c
View file

@ -49,7 +49,7 @@ static int adt7420_attr_set(struct device *dev,
{
struct adt7420_data *drv_data = dev->driver_data;
const struct adt7420_dev_config *cfg = dev->config->config_info;
u8_t val8, reg = 0;
u8_t val8, reg = 0U;
u16_t rate;
s64_t value;

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