drivers: add spi support for atmel sam series soc
This driver is based on spi_sam0 Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
This commit is contained in:
qianfan Zhao
Kumar Gala
parent
92ef8582b9
commit
6e4963b978
4 changed files with 452 additions and 0 deletions
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@ -5,6 +5,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_INTEL spi_intel.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_mcux_lpspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SAM spi_sam.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SAM0 spi_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_NRFX_SPI spi_nrfx_spi.c)
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zephyr_library_sources_ifdef(CONFIG_NRFX_SPIM spi_nrfx_spim.c)
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@ -251,6 +251,8 @@ source "drivers/spi/Kconfig.mcux_dspi"
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source "drivers/spi/Kconfig.mcux_lpspi"
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source "drivers/spi/Kconfig.sam"
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source "drivers/spi/Kconfig.sam0"
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source "drivers/spi/Kconfig.nrfx"
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11
drivers/spi/Kconfig.sam
Normal file
11
drivers/spi/Kconfig.sam
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@ -0,0 +1,11 @@
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# Kconfig - Atmel SAM SPI
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#
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# Copyright (c) 2018 qianfan Zhao
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# SPDX-License-Identifier: Apache-2.0
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menuconfig SPI_SAM
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bool "Atmel SAM series SPI driver"
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depends on SOC_FAMILY_SAM
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select HAS_DTS_SPI
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help
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Enable support for the SAM SPI driver.
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438
drivers/spi/spi_sam.c
Normal file
438
drivers/spi/spi_sam.c
Normal file
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@ -0,0 +1,438 @@
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/*
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* Copyright (c) 2017 Google LLC.
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* Copyright (c) 2018 qianfan Zhao.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_sam);
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#include "spi_context.h"
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#include <errno.h>
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#include <device.h>
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#include <spi.h>
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#include <soc.h>
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#include <board.h>
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/* Device constant configuration parameters */
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struct spi_sam_config {
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Spi *regs;
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u32_t periph_id;
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struct soc_gpio_pin pins;
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};
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/* Device run time data */
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struct spi_sam_data {
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struct spi_context ctx;
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};
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static int spi_sam_configure(struct device *dev,
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const struct spi_config *config)
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{
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const struct spi_sam_config *cfg = dev->config->config_info;
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Spi *regs = cfg->regs;
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u32_t spi_mr = 0, spi_csr = 0;
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int div;
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if (SPI_OP_MODE_GET(config->operation) != SPI_OP_MODE_MASTER) {
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/* Slave mode is not implemented. */
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return -ENOTSUP;
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}
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/* Set master mode, disable mode fault detection, set fixed peripheral
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* select mode.
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*/
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spi_mr |= (SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS(config->slave));
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if ((config->operation & SPI_MODE_CPOL) != 0) {
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spi_csr |= SPI_CSR_CPOL;
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}
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if ((config->operation & SPI_MODE_CPHA) == 0) {
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spi_csr |= SPI_CSR_NCPHA;
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}
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if (SPI_WORD_SIZE_GET(config->operation) != 8) {
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return -ENOTSUP;
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} else {
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spi_csr |= SPI_CSR_BITS(SPI_CSR_BITS_8_BIT);
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}
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/* Use the requested or next higest possible frequency */
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div = SOC_ATMEL_SAM_MCK_FREQ_HZ / config->frequency;
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div = max(1, min(UINT8_MAX, div));
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spi_csr |= SPI_CSR_SCBR(div);
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regs->SPI_CR = SPI_CR_SPIDIS; /* Disable SPI */
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regs->SPI_MR = spi_mr;
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regs->SPI_CSR[config->slave] = spi_csr;
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regs->SPI_CR = SPI_CR_SPIEN; /* Enable SPI */
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return 0;
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}
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static bool spi_sam_transfer_ongoing(struct spi_sam_data *data)
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{
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return spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx);
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}
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static void spi_sam_shift_master(Spi *regs, struct spi_sam_data *data)
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{
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u8_t tx;
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u8_t rx;
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if (spi_context_tx_buf_on(&data->ctx)) {
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tx = *(u8_t *)(data->ctx.tx_buf);
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} else {
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tx = 0;
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}
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while ((regs->SPI_SR & SPI_SR_TDRE) == 0) {
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}
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regs->SPI_TDR = SPI_TDR_TD(tx);
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spi_context_update_tx(&data->ctx, 1, 1);
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while ((regs->SPI_SR & SPI_SR_RDRF) == 0) {
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}
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rx = (u8_t)regs->SPI_RDR;
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if (spi_context_rx_buf_on(&data->ctx)) {
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*data->ctx.rx_buf = rx;
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}
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spi_context_update_rx(&data->ctx, 1, 1);
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}
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/* Finish any ongoing writes and drop any remaining read data */
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static void spi_sam_finish(Spi *regs)
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{
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while ((regs->SPI_SR & SPI_SR_TXEMPTY) == 0) {
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}
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while (regs->SPI_SR & SPI_SR_RDRF) {
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(void)regs->SPI_RDR;
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}
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}
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/* Fast path that transmits a buf */
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static void spi_sam_fast_tx(Spi *regs, const struct spi_buf *tx_buf)
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{
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const u8_t *p = tx_buf->buf;
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const u8_t *pend = (u8_t *)tx_buf->buf + tx_buf->len;
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u8_t ch;
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while (p != pend) {
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ch = *p++;
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while ((regs->SPI_SR & SPI_SR_TDRE) == 0) {
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}
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regs->SPI_TDR = SPI_TDR_TD(ch);
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}
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spi_sam_finish(regs);
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}
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/* Fast path that reads into a buf */
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static void spi_sam_fast_rx(Spi *regs, const struct spi_buf *rx_buf)
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{
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u8_t *rx = rx_buf->buf;
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int len = rx_buf->len;
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if (len <= 0) {
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return;
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}
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/* See the comment in spi_sam_fast_txrx re: interleaving. */
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/* Write the first byte */
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regs->SPI_TDR = SPI_TDR_TD(0);
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len--;
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while (len) {
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while ((regs->SPI_SR & SPI_SR_TDRE) == 0) {
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}
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/* Load byte N+1 into the transmit register */
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regs->SPI_TDR = SPI_TDR_TD(0);
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len--;
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/* Read byte N+0 from the receive register */
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while ((regs->SPI_SR & SPI_SR_RDRF) == 0) {
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}
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*rx++ = (u8_t)regs->SPI_RDR;
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}
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/* Read the final incoming byte */
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while ((regs->SPI_SR & SPI_SR_RDRF) == 0) {
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}
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*rx = (u8_t)regs->SPI_RDR;
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spi_sam_finish(regs);
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}
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/* Fast path that writes and reads bufs of the same length */
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static void spi_sam_fast_txrx(Spi *regs,
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const struct spi_buf *tx_buf,
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const struct spi_buf *rx_buf)
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{
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const u8_t *tx = tx_buf->buf;
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const u8_t *txend = (u8_t *)tx_buf->buf + tx_buf->len;
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u8_t *rx = rx_buf->buf;
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size_t len = rx_buf->len;
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if (len <= 0) {
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return;
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}
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/*
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* The code below interleaves the transmit writes with the
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* receive reads to keep the bus fully utilised. The code is
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* equivalent to:
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*
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* Transmit byte 0
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* Loop:
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* - Transmit byte n+1
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* - Receive byte n
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* Receive the final byte
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*/
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/* Write the first byte */
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regs->SPI_TDR = SPI_TDR_TD(*tx++);
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while (tx != txend) {
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while ((regs->SPI_SR & SPI_SR_TDRE) == 0) {
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}
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/* Load byte N+1 into the transmit register. TX is
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* single buffered and we have at most one byte in
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* flight so skip the DRE check.
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*/
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regs->SPI_TDR = SPI_TDR_TD(*tx++);
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/* Read byte N+0 from the receive register */
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while ((regs->SPI_SR & SPI_SR_RDRF) == 0) {
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}
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*rx++ = (u8_t)regs->SPI_RDR;
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}
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/* Read the final incoming byte */
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while ((regs->SPI_SR & SPI_SR_RDRF) == 0) {
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}
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*rx = (u8_t)regs->SPI_RDR;
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spi_sam_finish(regs);
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}
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/* Fast path where every overlapping tx and rx buffer is the same length */
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static void spi_sam_fast_transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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const struct spi_sam_config *cfg = dev->config->config_info;
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size_t tx_count = 0;
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size_t rx_count = 0;
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Spi *regs = cfg->regs;
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struct spi_buf *tx = NULL, *rx = NULL;
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if (tx_bufs) {
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tx = tx_bufs->buffers;
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tx_count = tx_bufs->count;
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}
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if (rx_bufs) {
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rx = rx_bufs->buffers;
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rx_count = rx_bufs->count;
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}
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while (tx_count != 0 && rx_count != 0) {
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if (tx->buf == NULL) {
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spi_sam_fast_rx(regs, rx);
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} else if (rx->buf == NULL) {
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spi_sam_fast_tx(regs, tx);
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} else {
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spi_sam_fast_txrx(regs, tx, rx);
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}
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tx++;
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tx_count--;
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rx++;
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rx_count--;
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}
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for (; tx_count != 0; tx_count--) {
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spi_sam_fast_tx(regs, tx++);
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}
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for (; rx_count != 0; rx_count--) {
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spi_sam_fast_rx(regs, rx++);
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}
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}
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/* Returns true if the request is suitable for the fast
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* path. Specifically, the bufs are a sequence of:
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*
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* - Zero or more RX and TX buf pairs where each is the same length.
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* - Zero or more trailing RX only bufs
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* - Zero or more trailing TX only bufs
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*/
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static bool spi_sam_is_regular(const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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const struct spi_buf *tx = NULL;
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const struct spi_buf *rx = NULL;
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size_t tx_count = 0;
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size_t rx_count = 0;
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if (tx_bufs) {
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tx = tx_bufs->buffers;
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tx_count = tx_bufs->count;
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}
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if (rx_bufs) {
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rx = rx_bufs->buffers;
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rx_count = rx_bufs->count;
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}
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if (!tx || !rx) {
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return true;
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}
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while (tx_count != 0 && rx_count != 0) {
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if (tx->len != rx->len) {
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return false;
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}
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tx++;
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tx_count--;
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rx++;
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rx_count--;
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}
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return true;
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}
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static int spi_sam_transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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const struct spi_sam_config *cfg = dev->config->config_info;
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struct spi_sam_data *data = dev->driver_data;
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Spi *regs = cfg->regs;
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int err;
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spi_context_lock(&data->ctx, false, NULL);
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err = spi_sam_configure(dev, config);
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if (err != 0) {
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goto done;
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}
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data->ctx.config = config;
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spi_context_cs_configure(&data->ctx);
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spi_context_cs_control(&data->ctx, true);
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/* This driver special cases the common send only, receive
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* only, and transmit then receive operations. This special
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* casing is 4x faster than the spi_context() routines
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* and allows the transmit and receive to be interleaved.
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*/
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if (spi_sam_is_regular(tx_bufs, rx_bufs)) {
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spi_sam_fast_transceive(dev, config, tx_bufs, rx_bufs);
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} else {
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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do {
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spi_sam_shift_master(regs, data);
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} while (spi_sam_transfer_ongoing(data));
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}
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spi_context_cs_control(&data->ctx, false);
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done:
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spi_context_release(&data->ctx, err);
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return err;
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_sam_transceive_async(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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return -ENOTSUP;
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_sam_release(struct device *dev,
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const struct spi_config *config)
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{
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struct spi_sam_data *data = dev->driver_data;
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static int spi_sam_init(struct device *dev)
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{
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const struct spi_sam_config *cfg = dev->config->config_info;
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struct spi_sam_data *data = dev->driver_data;
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soc_pmc_peripheral_enable(cfg->periph_id);
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soc_gpio_configure(&cfg->pins);
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spi_context_unlock_unconditionally(&data->ctx);
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/* The device will be configured and enabled when transceive
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* is called.
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*/
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return 0;
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}
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static const struct spi_driver_api spi_sam_driver_api = {
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.transceive = spi_sam_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_sam_transceive_async,
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#endif
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.release = spi_sam_release,
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};
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#define SPI_SAM_DEFINE_CONFIG(n) \
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static const struct spi_sam_config spi_sam_config_##n = { \
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.regs = (Spi *)CONFIG_SPI_##n##_BASE_ADDRESS, \
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.periph_id = CONFIG_SPI_##n##_PERIPHERAL_ID, \
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.pins = PINS_SPI##n, \
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}
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#define SPI_SAM_DEVICE_INIT(n) \
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SPI_SAM_DEFINE_CONFIG(n); \
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static struct spi_sam_data spi_sam_dev_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_sam_dev_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_sam_dev_data_##n, ctx), \
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}; \
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DEVICE_AND_API_INIT(spi_sam_##n, \
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CONFIG_SPI_##n##_NAME, \
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&spi_sam_init, &spi_sam_dev_data_##n, \
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&spi_sam_config_##n, POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, &spi_sam_driver_api)
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#if CONFIG_SPI_0_BASE_ADDRESS
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SPI_SAM_DEVICE_INIT(0);
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#endif
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#if CONFIG_SPI_1_BASE_ADDRESS
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SPI_SAM_DEVICE_INIT(1);
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#endif
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