Disabling multithreading is not possible when enabling SMP (logically)
so depend on SMP being disabled to enable
ARCH_HAS_SINGLE_THREAD_SUPPORT.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This change suppress the warning:
variable 'ie' is used uninitialized whenever switch default is
taken [-Wsometimes-uninitialized]
Signed-off-by: William Tambe <williamt@cadence.com>
For RISCV vector table needs to be aligned depending on
CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN. This was missing
when using LTO making issues when direct ISR were in use.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
use CONFIG_RISCV_ISA_EXT_F to set CONFIG_CPU_HAS_FPU.
Same for CONFIG_RISCV_ISA_EXT_D and
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
`CONFIG_EXTRA_EXCEPTION_INFO` that was added in #78065 doesn't
seem necessary, as we were already storing and printing the
callee-saved-registers before that. All `CONFIG_EXTRA_EXCEPTION_INFO`
does in RISCV is to add an additional `_callee_saved_t *csf` in the
`struct arch_esf`, which overhead is negligible to what's being enabled
by `CONFIG_EXCEPTION_DEBUG`.
Let's remove `CONFIG_EXTRA_EXCEPTION_INFO`, and have that extra
`_callee_saved_t *csf` in the `struct arch_esf` as long as
`CONFIG_EXCEPTION_DEBUG` is enabled.
TL;DR: it doesn't make sense to not enable `CONFIG_EXTRA_EXCEPTION_INFO`
when `CONFIG_EXCEPTION_DEBUG` is enabled, so let's merge them.
Then, since `*csf` is always available in the `struct arch_esf` when
`CONFIG_EXCEPTION_DEBUG=y`, we can simply rely on that pointer in
`z_riscv_fatal_error()` instead of an additional argument in
`z_riscv_fatal_error_csf()`, rendering the latter redundant and thus
can be removed.
Additionally, save the callee-saved registers before jumping to
to `z_riscv_fault()`, so that callee-saved-registers are printed on
generic CPU exception as well.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Fixes local ISR generation so that devices actually boot, also
allows enabling LTO for these builds (tested working on nrf54l15
flpr device)
Signed-off-by: Jamie McCrae <spam@helper3000.net>
Let's move the null pointer trap first so to give set_pmp_entry() the
opportunity to use a single-slot TOR entry.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Adds a new kconfig CONFIG_MEM_DOMAIN_HAS_THREAD_LIST so that
only the architectures requiring to keep track of threads in
memory domains will have the necessary list struct inside
the memory domain structs. Saves a few bytes for those arch
not needing this.
Also rename the struct fields to be most descriptive of what
they are.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Refactor the code to read all PMP address CSRs (pmpaddr0 through
pmpaddrN) into a new helper function, `z_riscv_pmp_read_addr`.
This change encapsulates the register reading loop, improving code
organization and potential reusability. The new function includes size
assertions
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Allow to configure the MMU for non-cacheable normal memories.
This mode is needed for instance by net samples to access to
to non word-aligned memory.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Replace `sizeof(unsigned long)` with `PMPCFG_STRIDE` (defined as
`__riscv_xlen / 8`) for dimensioning PMP configuration register arrays
(`pmpcfg_regs`).
The size of PMP configuration registers should be derived directly from
the target architecture's XLEN. Using `sizeof(unsigned long)` can cause
size mismatches, particularly with static analysis tools like SonarQube.
These tools might assume a host-specific size for `unsigned long`,
leading to spurious out-of-bounds access warnings when analyzing code
for different RISCV base architectures (e.g., RV32 vs. RV64).
This change ensures the array sizing is correctly and consistently tied
to the target's register width (XLEN).
Signed-off-by: Firas Sammoura <fsammoura@google.com>
soc_prep_hook() is always called from z_prep_c() which is implemented
as a C function. As such, there is no need to check for the associated
CONFIG_SOC_PREP_HOOK since the platform/hooks.h header will define hooks
as no-op function-like macros if their associated Kconfig isn't enabled.
Remove the Kconfig check from all arch implementations of z_prep_c() and
call soc_prep_hook() directly instead, to avoid duplicating the Kconfig
check already performed in platform/hooks.h
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Introduce `z_riscv_pmp_write_config` to abstract writing to pmpcfg
registers. This function handles the differing register layouts and slot
counts between RV32 and RV64 architectures, writing to the appropriate
pmpcfg0, pmpcfg1, pmpcfg2, or pmpcfg3 CSRs as needed based on
CONFIG_PMP_SLOTS.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
arch_mem_map() takes in some flags to describe the to-be mapped
memory regions' permissions and cache status. When the flags are
translated, they become attributes in PTEs. So for functions
being called by arch_mem_map() and beyond, rename flags to
attrs to better describe its purpose.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In functions which manipulate both L1 and L2 tables, make
the variable names obvious by prefixing them with l1_ or l2_.
This is mainly done to avoid confusion when reading through
those functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The assert error messages when l2_page_table_map() fails are not
correct. It returns false when it cannot allocate new L2 table,
and it is not able the address having already mapped. So correct
the error message.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is simply done to conserve code space in the vector text
areas. These vector text areas are very small and we should
only put code that is absolutely necessary for interrupt and
exception entrance. The saving of PS into the thread struct
can be deferred a bit. So do that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
xtensa_asm2_s.h is not exactly a C header. Rename it to
xtensa_asm2.inc.S to clearly state that it is has assembly
code in it as its main purpose is to declare assembly macros.
This is being done to keep checkpatch.pl from treating it as
C file and complaining about non-C syntax.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the block of FPU and HIFI registers in the Base Save
Area (BSA), used during interrupts and exceptions, to the end of
the block. This is done to minimize code usage in the vector
text section. During interrupt entrance, the code stores a small
set of registers first before jumping to the long handler. When
the offset to these registers from the beginning of BSA is small
enough, the compiler will emit S32I.N instead of S32I. This
saves us one byte per store (2 vs 3 bytes). This is mainly done
to avoid overflowing the vector text area.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a function to handle DTLB multihit exception when
userspace is enabled, as this exception may be raised due to
the same page being able to accessed by both kernel and user
threads. The auto-refill DTLBs may contain entries for same
page, one for kernel and one for user under some situations.
We need to invalidate those existing DTLB entries so that
hardware can reload from the page table.
This is an alternative to the kconfig invalidating DTLBs on
every swap: CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP.
Although this does not have extra processing per context
switching, exception handling itself has a high cost. So
care needs to be taken on whether to enable that kconfig.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When a page can be accessed by both kernel and user threads,
the autofill DTLB may contain an entry for kernel thread.
This will result in load/store ring exception when it is
accessed by user thread later. In this case, we need to
invalidate all associated TLBs related to kernel access so
hardware can reload the page table the correct permission
for user thread.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This saves the EXCCAUSE and EXCVADDR into BSA during exception.
These will then be used during exception handling. The reason
for doing this instead of reading from both registers during
exception handing is that another exception will override
the value in these register (e.g. DTLB miss). When returning to
the previous exception handler, these register no longer
contains the original exception cause and address. We need to
save it so that we are actually handling the orignal exception.
Coredump also now uses the EXCCAUSE and EXCVADDR from BSA
instead of reading the registers.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The software bits inside PTE are used to store original PTE
attributes and ring value, and those bits are used to
restore PTE to previous state.
This modifies reset_region() to properly restore attributes
and ring value when resetting memory regions to the same as
when the system boots.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
RX26T MCU support mapped interrupt features, add dependency config to
enable zephyr library source from hal
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:
1. Rename Kconfig name
CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
a. arch/riscv/custom/thead/Kconfig: for T-Head extension
b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
(e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Update OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom
CSR common code. Move these stuff to 'arch/riscv/custom/openisa':
1. Rename 'soc_ri5cy.h' to 'ri5cy_csr.h' for CSR definitions.
2. Rename 'soc_zero_riscy.h' to 'zero_riscy_csr.h' for CSR definitions.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move compiler option '-march=rv32imcxpulpv2' to common code.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h',
allowing other SoCs using the CVA6 core to reuse the same CSR definitions.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to
'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Rework Andes-specific CSR to use RISC-V custom CSR common code.
Move these stuff to 'arch/riscv/custom/andes':
1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions.
2. Replace '_start' with '__reset' hook for low-level CSR initialization.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move 'EXECIT' CSR support to common code.
5. Move PMA CSR driver to common code.
6. Use RISC-V common linker.ld instead of SoC-specific linker.ld.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
RISC-V allows custom CSR implementation. Some SoCs from different vendors
may share the same core or the same custom CSR definitions and drivers.
This patch introduces 'arch/riscv/custom', which centralizes support
for custom CSRs, allowing code reuse across SoCs that come from different
vendors. Currently supported thess custom CSR:
1. Andes
2. Nuclei
3. OpenHWGroup CVA6
4. OpenISA RI5CY
5. OpenISA Zero-riscy
6. T-Head Xuantie
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The PMP initialization and thread seeding logic in arch/riscv/core/pmp.c
did not correctly handle scenarios where the global PMP entries span
across multiple `pmpcfg` hardware registers.
The `global_pmp_cfg` array, intended to store the hardware register
values, was hardcoded to size 1. This is only sufficient if all global
PMP entries fall within the range covered by the first `pmpcfg` register
(e.g., pmpcfg0). When more global entries are used, their configurations
reside in subsequent `pmpcfg` registers (pmpcfg1, pmpcfg2, etc.).
The code was only saving/restoring and checking `global_pmp_cfg[0]`,
leading to loss of configuration for entries mapped to higher `pmpcfg`
registers.
This patch fixes this by:
1. Resizing the `global_pmp_cfg` array to
`CONFIG_PMP_SLOTS / PMPCFG_STRIDE` to correctly accommodate values
from all potentially used `pmpcfg` CSRs.
2. In `z_riscv_pmp_init`, using `memcpy` to save the entire contents of
the local `pmp_cfg` array (derived from initial setup) into the
`global_pmp_cfg` array.
3. In `z_riscv_pmp_thread_init`, using `memcpy` to restore the entire
saved global configuration from `global_pmp_cfg` into a thread's
`pmp_cfg` array.
4. Updating the SMP consistency assertion in `z_riscv_pmp_init` to
compare the contents of the array element @ `index / PMPCFG_STRIDE`
of the `pmp_cfg` arrays.
These changes ensure that the configurations from all relevant `pmpcfg`
registers are preserved and correctly propagated to thread contexts.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Factor out the logic for reading PMP configuration registers (pmpcfgX)
from dump_pmp_regs into a new static inline helper function,
z_riscv_pmp_read_config.
This new function encapsulates the architecture-specific (RV32/RV64)
and slot-count-specific reads of the pmpcfg CSRs, improving code
organization and potential reusability.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Specifying undefined symbol on linker invocation requests the linker to
search and include the symbol.
This ensures the symbol will be present in final output.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Use the privileged stack when starting K_USER threads in arch_new_thread().
Threads entering user mode with k_thread_user_mode_enter() keep their
existing flow. To support both cases, z_arm_userspace_enter() now takes an
internal ABI flag (sp_is_priv) indicating whether PSP already points to
the privileged stack.
Also fix calculation of the privileged stack top: use priv_stack_end
directly instead of priv_stack_start + CONFIG_PRIVILEGED_STACK_SIZE, which
failed to account for guard/FPU offsets applied to priv_stack_start.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The arrays used for M-mode Physical Memory Protection (PMP),
specifically for the stack guard feature (CONFIG_PMP_STACK_GUARD),
were previously sized using the hardcoded PMP_M_MODE_SLOTS macro,
defined as 8. This affected arrays in both the _thread_arch
struct (m_mode_pmpaddr_regs, m_mode_pmpcfg_regs) and local
variables within the z_riscv_pmp_stackguard_disable function.
This commit changes the array sizing to use the Kconfig option
CONFIG_PMP_SLOTS. This option reflects the total number of PMP
slots available and configured for the target hardware.
Using CONFIG_PMP_SLOTS ensures these arrays are dimensioned
according to the system's actual capabilities, providing better
flexibility and correctness over a fixed size.
The PMP_M_MODE_SLOTS macro definition has been removed from
thread.h as it is no longer used.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Introduce hook for customize reset.S code even before stack is
initialized or RAM is accessed. Hook can be enabled using
CONFIG_SOC_EARLY_RESET_HOOK=y.
Hook implementation is by soc_early_reset_hook() function which should
be provided by custom code.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Currently, CORTEX_M_DWT option does not refresh its value when
TIMING_FUNCTIONS, on which it depends, is selected via menuconfig.
This occurs because during the early west build steps the
aarch32-specific Kconfig file is parsed with TIMING_FUNCTIONS=n,
resulting in CORTEX_M_DWT being set to 'n' (not set) in .config.
Later, when the user runs west with -t menuconfig and sets
TIMING_FUNCTIONS=y using the menus or any other option that selects
TIMING_FUNCTIONS=y indirectly, CORTEX_M_DWT is already set to 'n' and
remains set as such. That is inconvenient, and, moreoever, since
CORTEX_M_DWT gets set if TIMING_FUNCTIONS is set in prj.conf, the
current behavior is not consistent, i.e. via the menuconfig setting
TIMING_FUNCTIONS=y doesn't imply selecting CORTEX_M_DWT automatically.
This commit addresses this issue by selecting CORTEX_M_DWT=y if
TIMING_FUNCTIONS becomes set to 'y', otherwise allowing it to be set via
the prompt. This is possible by making the CORTEX_M_DWT prompt
conditional. Hence, in menuconfig, if TIMING_FUNCTIONS gets set
CORTEX_M_DWT is set automatically. If TIMING_FUNCTIONS is not set, a
prompt is presented to allow selecting CORTEX_M_DWT manually.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
- add NXP_BOARD_SPECIFIC_MPU_SETTINGS kconfig to provide a switch
for developer if they want to use private mpu settings
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==1 | NXP default setting
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==0 | User specific
- Use DT function to get memory base address and region size for cm7
- CM33 use dts to set mpu settings
- Add REGION_CUSTOMED_MEMORY_SIZE macro provide a common mapping ways
to map actual memory_size_kb to "region_size"
- The settings of the unified memory on cm33/cm7 cores:
ocram1/flexspi2 -> REGION_RAM_NOCACHE_ATTR
ocram2/dtcm -> REGION_RAM_NOCACHE_ATTR
flexspi/itcm -> REGION_FLASH_ATTR
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The config PM_S2RAM_CUSTOM_MARKING is not an optional config for a
user to select, it is required by some soc implementations of S2RAM,
in which case it must be selected by the soc.
Refactor the configuration to be HAS_PM_S2RAM_CUSTOM_MARKING, and
make the currently only soc which needs it select it. Then update
samples which previously had to select this option for this soc.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Several static functions in ptables.c always return 0, make them void
to improve readability.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
