This is an X86 specific option and should not appear as generic debug
option.
Fixeszephyrproject-rtos/zephyr#52929
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add semihosting support for Xtensa architecture.
Existing semihosting instructions are based on ARM, so they are
converted to Xtensa codes before the semihosting call is invoked.
Return codes of read, write and seek calls had to be converted to match
semihosting API definitions.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Move semihost_x_args structs to include/semihost_types.h so that
semihost implementations can access their elements if needed.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
When calling device_get_binding(NULL) from userspace, this eventually
funnels down to a call to arch_user_string_nlen() where it tried to
verify that the kernel has access to this address (0x0). But since
this originates from userspace, we really want to know if this is
accessible from userspace, so using arch_buffer_validate() instead
of xtensa_mem_kernel_has_access() is preferable.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Support booting from any usable core in systems with partially
fused-off CPUs. Update get_cpu_logic_id to iterate over the actual
number of enabled CPUs using DT_CHILD_NUM_STATUS_OKAY(DT_PATH(cpus))
instead of CONFIG_MP_MAX_NUM_CPUS.
Resize the voting[] array based on DT_CHILD_NUM_STATUS_OKAY to ensure
each CPU can vote correctly.
Signed-off-by: urvashi sharma <urvashis@qti.qualcomm.com>
This fixes GDB backtracing by forcibly spilling all registers,
and faking values for WINDOWSTART and WINDOWBASE. This is
effectively telling GDB that only A0-A3 and AR0-AR3 contain
active data and other physical registers do not. GDB then must
rely on spilled values on stack. Otherwise, GDB will try to
look at all AR* registers for previous frame(s). Since we
do not save all AR* register values, there is nothing for GDB
to look at, and thus failing to unwind stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Inside copy_to_ctx(), we are typecasting the stack pointer into
a 32-bit array pointer, and there was unbalanced const between
two sides. Since we should not be modifying anything inside
that array, add const to the 32-bit array pointer too. So now
the compiler will not complain about discarding the const
qualifier.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The calculation of number of high registers is not entirely
correct. We need to get past the pointer to BSA in the stack
frame before reaching the high registers. The location address
difference between the BSA and start of high registers then
can be used to calculate how many high registers in the stack
frame. So correct the start location of high registers in
the calculation as it was incorrect before. Though the result
would be the same as further divisions would mask this error.
However, it is better to correct this for readability.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With experience it becomes clear, that failing to resolve symbols
during the linking process is likely fatal for the module loading and
a simple warning isn't enough. Fail loading instead.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
move mov r7, #0 to use it on both branches as aarch64
implementation uses wzr which returns 0 on read
but r7 might have an undefined value after a reset.
Signed-off-by: Julien Racki <julien.racki@st.com>
The difference between __irq_disable() and irq_lock() is that the former
essentially translates to `cpsid i`, whereas `irq_lock()` translates to
setting BASEPRI (on cores with BASEPRI). This means that using
irq_lock() does not disable zero-latency interrupts (ZLIs), which
reduces the potential execution latency of ZLIs.
In both isr_wrapper and _arch_isr_direct_pm() (which is just
really an implementation of ISR_DIRECT_PM()), we were using
__irq_disable() to disable all interrups, including ZLIs. But the code
executed with interrupts disabled handles waking up from idle, and so
must only be protected against regular interrupts being executed, not
ZLIs, which should have no effect on the correct execution of the code.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Allow to specify a human readable full name for archs that can then be
leveraged e.g. in the documentation.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
riscv_cpu_wake_flag and riscv_cpu_sp are variables, not functions, so
they should use the GDATA macro instead of the GTEXT macro. Otherwise,
the linker will warn when LTO is enabled:
ld.bfd: warning: type of symbol `riscv_cpu_wake_flag' changed from 2 to
1 in /tmp/cc39w5oK.ltrans0.ltrans.o
ld.bfd: warning: type of symbol `riscv_cpu_sp' changed from 2 to 1 in
/tmp/cc39w5oK.ltrans0.ltrans.o
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
In the commit 573a712bed patch "arm64:
reset: disable cache and MMU for safety", it disables D-Cache and MMU
for safety, but in some cases, for example the code is loaded into memory
by hardware debugger, we need to flush D-Cache before disable it in
order to make sure the data is coherent in the system, otherwise it
will report "Synchronous Abort" when D-Cache is disabled.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This reverts commit 573a712bed.
The original patch disable cache and MMU, but in some cases, for example
the code is loaded into memory by hardware debugger, we need to flush
D-Cache before disable it in order to make sure the data is coherent
in the system, otherwise it will report "Synchronous Abort" when D-Cache
is disabled.
This patch revert the old one and the following patch will flush
the cache before disable it.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Added new configuration item to optionally enable APIs for operation
all data cache, by default these APIs are disabled.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Commit 87719828ac introduced FSR definitions
for ARMv7-A/R; however, the value 16 which is documented in the ARM[1] as
a "TLB Conflict Abort", was introduced as "TLB Conflict Fault" instead and
described as a "Table Conflict Fault".
Update all affected files to use the ARM's naming for this error instead.
[1] Architecture Reference Manual (Document ID: ARM DDI 0406C.d)
"ARM Architecture Reference Manual for ARMv7-A and ARMv7-R Edition"
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Introduce a Kconfig choice to select Pointer Authentication and Branch
Target Identification (PACBTI) features on Armv8.1-M Mainline CPUs.
The available options map to supported `-mbranch-protection` levels
(`standard`, `pac-ret`, `bti`, and combinations) documented at
https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
These options enable hardware-assisted control-flow integrity mechanisms on
targets like Cortex-M85, and require a toolchain with PACBTI support, such
as GCC 14.2 or newer.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Instead of both checking CONFIG_BOARD_QEMU_X86 and
CONFIG_BOARD_QEMU_X86_64, simply check for CONFIG_QEMU_TARGET.
This also helps qemu_x86_tiny, qemu_x86_lakemont and any
future/downstream QEMU targets to keep things simple.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
the device_state need realocate when boot as second core.
as the relocation does not know the alignment, this could
be a case that the next data is mis-place after relocation.
fix this by add a alignment in device_state section.
still need revert aec0355380
reported in #86871fixes: #82841
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Due to erratum 1013783-B, speculative accesses might be performed
to normal memory unmapped in the MPU. This can be avoided by using
MPU region 0 to cover all unmapped memory and make this region
execute-never and inaccessible.
Note that this applies when CPU Cortex-M7 implements MPU and D-cache.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This adds a new kconfig and corresponding code to allow flushing
auto-refill data TLBs when page tables are swapped (e.g. during
context switching). This is mainly used to avoid multi-hit TLB
exception raised by certain memory access pattern. If memory is
only marked for user mode access but not inside a memory domain,
accessing that page in kernel mode would result in a TLB being
filled with kernel ASID. When going back into user mode, access
to the memory would result in another TLB being filled with
the user mode ASID. Now there are two entries on the same memory
page, and the multi-hit TLB exception will be raised if that
memory page is accessed. This type of access is better served
using memory partition and memory domain to share data. However,
this type of access is not prohibited but highly discouraged.
Wrapping the code in kconfig is simply because of the execution
penalty as there will be unnecessary TLB refilling being done.
So only enable this if necessary.
Fixes#88772
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch fixes memory corruption that can happen when running in
multi-thread and multi-core environment with heavy scheduling stress.
In SMP configuration, we must ensure that all thread's context is
stored before writing the switch_handle flag. Otherwise some of the
thread context writes could be delayed after another CPU begins to
schedule this thread which could lead to memory corruptions.
Signed-off-by: Sylvain Chouleur <schouleur@snapchat.com>
Initializing the C++ stack unwinding data structures takes quite a bit
of stack space. Increase the TEST_EXTRA_STACK_SIZE when using these.
Signed-off-by: Keith Packard <keithp@keithp.com>
Zephyr switched to using CMSIS_6 module in f726cb51
which breaks certain boards like `nucleo_h745zi_q/stm32h745xx/m7` when
CONFIG_CORTEX_M_DWT, CONFIG_TIMING_FUNCTIONS are enabled and cmsis from
`module/hal/cmsis` is not available (deleted explicitly after west
update).
This commit adds a provision to be able to use CMSIS_6 macros when the
module cmsis is not available.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Stack walking on x86_64 can run with compiler optimization and
does not need CONFIG_NO_OPTIMIZATIONS as long as frame pointers
are not omitted. So remove the "depends on" for x86_64
from CONFIG_ARCH_HAS_STACKWALK.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Building gdbstub for xtensa is failing currently with multiple
failures like
arch/xtensa/core/gdbstub.c:432:24: error: invalid operands to \
binary - (have 'int *' and 'const struct arch_esf *')
432 | if ((int *)bsa - stack > 4) {
Fix them by using appropriate pointer types.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The original 'arch_pm_s2ram_resume' implementation saved lr on the stack
using 'push {lr}' and restored it using 'pop {lr}'. However, the Thumb-1
'pop' does not support lr as a target register, so this code would not
compile for ARMv6-M or ARMv8-M Baseline. r0 was added to these push/pop
later in 2590c48d40.
In 474d4c3249, arch_pm_s2ram* functions were
modified to no longer use the stack, which incidentally "fixed" this issue.
b4fb5d38eb reverted this commit and brought
back 'pop {r0, lr}' as-is, without taking compatibility into account.
Modify the sequence to use "pop {r0, pc}" which is supported on all
ARM M-profile implementations (v6/v7/v8 Baseline/v8 Mainline), and
add comments to (hopefully) prevent this issue from re-appearing.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
On the Xilinx MPSoC (Cortex-R5) platform, erratic operation was often
seen when an operation which disabled the dcache, such as sys_reboot,
was performed. Usually this manifested as an undefined instruction trap
due to the CPU jumping to an invalid memory address.
It appears the problem was due to dirty cache lines being present at the
time the cache is disabled. Once the cache is disabled, the CPU will
ignore the cache contents and read the possibly out-of-date data in main
memory. Likewise, since the cache was being cleaned after it was already
disabled, if the CPU had already written through changes to some memory
locations, cleaning the cache at that point would potentially overwrite
those changes with older data.
The fact that the arch_dcache_flush_and_invd_all function was being
called to do the cleaning and invalidation also contributed to this
problem, because it is a non-inline function which means the compiler
will generate memory writes to the stack when the function is called and
returns. Corruption of the stack can result in the CPU ending up jumping
to garbage addresses when trying to return from functions.
To avoid this problem, the cache is now cleaned and invalidated prior to
the dcache being disabled. This is done by directly calling the
L1C_CleanInvalidateDCacheAll function, which, as it is declared as force
inline, should help ensure there are no memory accesses, which would
populate new cache lines, between the cache cleaning and disabling the
cache.
Ideally, for maximum safety, the cache cleaning and cache disabling
should be done in assembler code, to guarantee that there are no memory
accesses generated by the compiler during these operations. However, the
present change does appear to solve this issue.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This file previously defined an MPU access permission mode of 0x7 which
corresponded to privileged read-only, unprivileged read-only, similar to
mode 0x6. However, it appears that at least Cortex-R5 does not support
this mode, defining 0x7 as UNP (Unpredictable) or a value which should
not be used.
This value was in turn referenced by the REGION_FLASH_ATTR macro, which
caused the offending value to be used when a memory region was declared
as DT_MEM_ARM(ATTR_MPU_FLASH) in the device tree, causing such regions
to not work properly on Cortex-R5.
Since 0x6 is supported by both Cortex-M and Cortex-R and does the same
thing, there is no reason to use 0x7. Remove the RO_Msk definition which
referenced it, and change REGION_FLASH_ATTR to use P_RO_U_RO_Msk instead.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add Kconfig option to dump only a portion of stack from the
current stack pointer to the stack end. This is enough to
let gdb reconstruct the stack trace and can significantly
reduce the dump size. This is crucial if the core dump needs
to be sent over radio.
Additionally, add another option to set the limit for the
dumped stack portion.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
This ASSERT fails because the comparison is made between the physical
APIC ID and the virtual CPU's LAPIC ID. If CPU-1 is assigned to ACRN,
it considers that CPU as its CPU-0.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
