Functions in assembler file pm_s2ram.S are declared with the usual:
SECTION_FUNC(TEXT, <function name>)
Note the first argument (section name) is `TEXT` in capital letters which
a define in `include/zephyr/linker/sections.h` should replace with `text`,
such that the functions are placed in section `.text.<function name>` which
matches the ".text.*" pattern in linker script. However, this file is not
included by pm_s2ram.S: as such, the substitution never happens and the
functions go in `.TEXT.<function name>` instead! This has not caused issues
thanks to a workaround in the Cortex-M linker script, which also has
".TEXT.*" as input section name pattern (unlike all other archs!), but is a
bug nonetheless.
Fix this issue by adding the missing include which ensures the functions
are placed in sections with the proper name.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The eponymous function in __aeabi_read_tp.S is declared using:
SECTION_FUNC(TEXT, __aeabi_read_tp)
Note the first argument (section name) is `TEXT` in capital letters which
a define in `include/zephyr/linker/sections.h` should replace with `text`,
such that the function is placed in section `.text.__aeabi_read_tp` which
matches the ".text.*" pattern in linker script. However, this file is not
included by __aeabi_read_tp.S: as such, the substitution never happens and
the function goes in `.TEXT.__aeabi_read_tp` instead! This has not caused
issues thanks to a workaround in the Cortex-M linker script, which also
has ".TEXT.*" as input section name pattern (unlike all other archs!), but
is a bug nonetheless.
Fix this issue by adding the missing include which ensures the function
is placed in a section with the proper name.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The Zephyr kernel's generic `z_fatal_error()` function, which is
invoked by architecture-specific fatal error handlers, is not
guaranteed to be non-returning. For instance, it can return if an
essential thread aborts itself.
The RISC-V port's `z_riscv_fatal_error` function was previously
inconsistently marked as `FUNC_NORETURN`. This commit removes this
attribute to align with the core kernel behavior, allowing the
function to return if `z_fatal_error()` returns.
Specific changes include:
- Removed `FUNC_NORETURN` from `z_riscv_fatal_error` declarations
in `fatal.c` and `kernel_arch_func.h`.
- Removed `CODE_UNREACHABLE` after the call to `z_fatal_error`
within `z_riscv_fatal_error` as it can now return.
- In `isr.S`, changed `tail z_riscv_fatal_error` to
`call z_riscv_fatal_error` in the exception entry, followed by
a jump to `check_reschedule` to handle the return path.
- Added `CODE_UNREACHABLE` at call sites of `z_riscv_fatal_error`
(e.g., in `z_riscv_fault`, `z_check_user_fault`,
`arch_irq_spurious`) where the context ensures the call is
effectively terminal.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Cortex-R5F Technical Reference Manual by Arm says DMINLINE is the Log2 of
the minimum number of words (one word = four bytes) in a cache line.
For instance, say DMINLINE is 3, which means the cache line size is
2^3=8 words or 32 bytes, however with the current calculation, it comes
out to be 16 bytes. Therefore, we fix this calculation by correctly
calculating the number of bytes for the cache line size.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
The arch_float_disable() function was not clearing the K_FP_REGS flag
from thread->base.user_options after disabling FPU access. This caused
the float_disable test to fail as it verifies the flag is properly
cleared after FPU disable.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Since we have split source files for page table related stuff
and MMU related stuff, move the MMU initialization functions
from the page table source file into MMU source file.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds doxygen doc to the page table source file as
we are missing quite a bit of documentation there.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This changes the existing comments for functions into doxygen
style documentation for functions. Also adds missing doxygen
doc for functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
1. it reguires that there are floating point registers,
so the extention f is required. (zfinx uses the int regs instead)
2. RV32E doesn't supports hardware floating-point calling convention.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Introduce the missing flag to compile code with Zbkb extension,
which has already been supported by the GCC 12 in current SDK.
Signed-off-by: Andy Lin <andylinpersonal@gmail.com>
Upgrades the thread user_options to 16 bits from an 8-bit value to
provide more space for future values.
Also, as the size of this field has changed, the values for the
existing architecture specific thread options have also shifted
from the upper end of the old 8-bit field, to the upper end of
the new 16-bit field.
Fixes#101034
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
If there are not enough free L2 tables to map all predefined
memory regions at boot, halt the system in case assertion is
not enabled. Without all the needed memory regions mapped,
it is very unlikely that anything will run properly.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds some debug logs when we are allocating page tables.
This provides a more visible way of seeing whether
we need to have more free tables.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add an assertions to halt the system if L2 table allocation
fails when we need to duplicate an existing L2 table, as it is
a must-have and must-success operation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
As per Zephyr guidelines re: inclusive language, the term
"master" is replaced with "primary".
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Preserve EXCCAUSE and EXCVADDR values on entry to _Level1Vector.
Restore EXCCAUSE when exiting TLB miss exception handling in the double
exception handler.
During first-level exception handling, a LoadStoreTLBMissException may
occur during the initial register dump to BSA. It modifies EXCCAUSE and
EXCVADDR registers before they are saved in BSA. Therefore, these values
must be captured as early as possible.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Remove saving EXCCAUSE register in BSA through the _Level1Vector handler.
These value are later overwritten by the ODD_REG_SAVE macro called by
EXCINT_HANDLER, so saving it here is pointless.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add infrastructure for SoCs to define additional PMP regions
that need protection beyond the standard ROM region. This uses
iterable sections to collect region definitions at link time.
The PMP_SOC_REGION_DEFINE macro allows SoCs to register memory
regions with specific permissions. These regions become global
PMP entries shared between M-mode and U-mode.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
After commit 02770ad963 ("debug: EXCEPTION_STACK_TRACE should depend
on arch Kconfigs"), the ARM64_EXCEPTION_STACK_TRACE isn't used any more,
remove it.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
soc_per_core_init_hook() is usually called from arch_kernel_init() and
arch_secondary_cpu_init() which are C functions. As such, there is no need
to check for CONFIG_SOC_PER_CORE_INIT_HOOK since platform/hooks.h provides
a no-op function-like macro implementation if the Kconfig option is not
enabled.
Remove the Kconfig option check from all files.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Ensure callee registers included in coredump.
Push callee registers onto stack for
CONFIG_ARMV6_M_ARMV8_M_BASELINE as well
when CONFIG_EXTRA_EXCEPTION_INFO enabled.
Effectively a complement to df6b8c3 by mholden.
Signed-off-by: Andy Lin <andylinpersonal@gmail.com>
Minor improvements in this cmake:
Add a comment to clarify why we set one option, and move an if
into an else with a comment of what is doing.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This variable is not set to anything.
This line has always been just bogus.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
NO_POSIX_CHEATS was a macro used to avoid including the content of a
header (`posix_cheats.h`) which allowed building applications in the
POSIX architecture without the native simulator, avoiding collisions
between some embedded symbols and those from the host C library.
Support for this way of building, and this header and macro were
removed in e150ffb92c, but these users
were forgotten. This was harmless, but let's just clean it up now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Use void * cleanly: avoid needless type-casts and use void * for
generic pointers instead of uint8_t *.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- CONFIG_ARM_MPU_SRAM_WRITE_THROUGH: enables Write-Through cache policy
for SRAM regions instead of default Write-Back
Includes corresponding MPU attribute macros for ARMv7-M and ARMv8-M
architectures. Maintains backward compatibility with existing
configurations.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
doc: dts: api: remove documentation of chosen `zephyr,ccm`
The `zephyr,ccm` chosen was an ST-specific property which has been replaced
by the generic `zephyr,dtcm`. Remove region initialization code from the
common arch init code (+ BSS zeroing from common XIP init code).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
During L2 page table duplication, there are cases where we
should copy the table over instead of restoring the PTEs.
Add the ability to copy the table over.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a spinlock to guard page table counter updates.
For some reasons, without this, xt-clang generated code would
result in incorrect counter update possibly due to memory
access ordering (though GCC generated code works fine without
the spin lock).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS instead.
The new kconfig reflects more correctly on what is going on
in hardware. Also, this is not enabled by default if CPU
cache is not coherent. CPU cache can be incoherent and yet
there are no mirrored memory regions. Those relying on this
deprecated default behavior has their config adding
CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes the following kconfigs:
() CONFIG_XTENSA_RPO_CACHE
() CONFIG_XTENSA_CACHED_REGION
() CONFIG_XTENSA_UNCACHED_REGION
The associated feature is actually SoC specific and not general
architecture feature. Since the only user of these have its own
implementation, we can now safely remove these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This re-implements the CONFIG_XTENSA_RPO_CACHE and its cached
and uncached region support in the SoC layer. This is in
preparation for removing RPO cache in the architecture layer
as this is a SoC feature and not an architecture feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows SoC to define their custom cache related functions
and are used by sys_cache_*() functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_mem_coherent() is cache related so it is better to move it
under cache subsys. It is renamed to sys_cache_is_mem_coherent()
to reflect this change.
The only user of arch_mem_coherent() is Xtensa. However, it is
not an architecture feature. That's why it is moved to the cache
subsys.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Zephyr linker script usually puts something before
z_mapped_start (where .text is), for example, vecbase vectors.
So we need to reserve those space or else k_mem_map() would be
mapping those which may result in faults.
To avoid mapping there, CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES
needs to be used. Since it is common when MMU is enabled, we
should enable it by default using imply. All current Xtensa
MMU SoCs all have this selected anyway. Using 'imply' instead
of 'select' is to allow it to be disabled if so desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes CONFIG_XTENSA_MMU_DOUBLE_MAP and its associated
code. The double mapping of a page into both cached and
uncached memory regions should be done in SoC and application,
as it gives finer control on what actually is being mapped.
For example, if a page only needs to mapped in cached region,
there is no need to map it in the uncached region. This may
save the need to allocate a L2 page table for it, and saves
some memory.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds kconfig CONFIG_XTENSA_MMU_USE_DEFAULT_MAPPINGS for arch
code to initialize the page tables with a few default mappings
covering text, data, BSS and RODATA. Disabling this allows
the SoC to customize and fine-tune the mappings if needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
