z_riscv_fatal_error() may return: when a fatal error is handled (for
example an expected fault in ztest aborting the current thread), the
generic z_fatal_error() returns and the exception exit path in isr.S
takes care of rescheduling. isr.S explicitly sets the return address
to no_reschedule before tail-calling z_riscv_fault for this reason.
The CODE_UNREACHABLE hint made LLVM place a trapping instruction
(unimp) right after the call. When the handler returned, the CPU
executed the unimp and re-entered the fault path, so tests raising
expected faults hung in an endless fatal error loop when built with
clang. GCC builds only worked by chance, falling through into
whatever code the compiler laid out after the call.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Right now, the SBI hard-codes the usage of ld/sd instructions, which are
not available on 32-bit platforms. This commit changes this to sr/lr from
`asm_macros.inc`, which automatically resolves them to proper load/store
instructions on 32-bit and 64-bit configurations. It also ensures proper
timer handling through 32-bit registers.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Co-authored-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Add an AArch64 PMUv3 implementation behind CONFIG_ARM64_PMUV3 (pmuv3.c):
probe ID_AA64DFR0_EL1, calibrate CPU frequency (PMCCNTR_EL0 vs the
generic timer), and provide per-CPU counter configuration, enable/disable,
overflow handling, and cycle counter access. Initialization is explicit
via pmu_init() on each logical CPU that uses the PMU (no SYS_INIT).
Introduce include/zephyr/pmu.h for the portable pmu_*() API.
Architectural PMUv3 event codes (PMU_EVT_* in 0x00-0x1F) and
PMCR/PMUSERENR bit defines live in include/zephyr/arch/arm64/pmuv3.h for
AArch64 builds.
Add ARCH_HAS_PMU in arch/Kconfig (Cortex-A profiles select it); enable
CONFIG_ARM64_PMUV3 for the PMUv3 driver backend. Register access uses
explicit MRS/MSR inlines instead of read_sysreg()/write_sysreg()
statement expressions for static analysis.
Builds for versal_apu, versalnet_apu, and versal2_apu. On QEMU, PMU
access is often unavailable (-ENOTSUP). On Versal Net APU hardware with
PMU usable at the current EL, initialization succeeds.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
The backtrace code was either calling the arch exception dump
hook or printk based on the value of its own config called
CONFIG_XTENSA_BACKTRACE_EXCEPTION_DUMP.
However, this made fault output inconsistent when CONFIG_LOG is enabled
because other output (like xtensa_dump_stack()) would use the macro
EXCEPTION_DUMP(), which would use LOG_ERR instead of printk. Fault output
would be a mix of log lines for register dumps and printk lines for
backtrace (no domains, timestamps, etc).
This commit changes backtrace to use the EXCEPTION_DUMP() macro so output
now is consistent. It also fixes an issue where if printk was going to
the logging subsystem (CONFIG_LOG_PRINTK=y), because the printk calls in
backtrace had no '\n' termination, the output would be lost in the log
format buffer.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Use <> operator to include a Zephyr header file instead of "" that
is intended to local header files, not header files relative to
specifically defined search paths.
This change was made running the sed shell command below:
$ sed -i -E 's/#include "zephyr\/([^"]+)\.h"/#include <zephyr\/\1.h>/g' \
`grep -rsl "#include \"zephyr/" arch/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add RISCV_ISA_EXT_ZK (Scalar Cryptography) and RISCV_ISA_EXT_ZKS
(ShangMi Suite) Kconfig options, and append them to the GCC march
flag when enabled.
Signed-off-by: Liu Qian <liuqian.andy@picoheart.com>
CONFIG_XTENSA_SYSCALL_USE_HELPER currently only routes the 4/5/6-argument
syscall invocations through out-of-line helper functions. Toolchains that
reject inline-asm fixed-register operands in inlinable functions still
fail to build the 0-3 argument variants.
Add xtensa_syscall_helper_args_0..3 and route arch_syscall_invoke0..3
through them, gated behind a new opt-in
CONFIG_XTENSA_SYSCALL_USE_HELPER_ALL (default n, depends on
XTENSA_SYSCALL_USE_HELPER). This keeps the default behaviour unchanged -
the 0-3 argument syscalls stay on the inline fast path - and only routes
the low-argument variants through the helpers for toolchains that need
it, so there is no performance impact unless the option is explicitly
enabled. The inline-asm fast path is preserved under the #else branch.
Signed-off-by: Hiren Virapara <Hiren.Virapara@amd.com>
On ARM64, synchronous exceptions leave DAIF.I set independently of the
kernel IRQ lock. The generic arch_irq_unlock(key) fallback is therefore
insufficient to re-enable IRQ delivery during the coredump window.
Override arch_coredump_fatal_irq_unlock/lock to directly manipulate the
DAIF register: save current DAIF in the cookie, then clear DAIF.I so
that NIC TX-done interrupts can fire while the UDP coredump backend
drains its send queue. arch_coredump_fatal_irq_lock restores the saved
DAIF value and returns a fresh arch_irq_lock() key for the remainder of
z_fatal_error().
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, I/DCACHE_LINE_SIZE are redefined and set to the given
default value even if the dependency D/ICACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
The arm_core_mpu_enable() and arm_core_mpu_disable() functions were
defined in the ARM MPU driver but never declared in a header.
As a result, callers had to provide their own local `extern`
declarations to use them.
Add documented prototypes for both functions to
include/zephyr/arch/arm/mpu/arm_mpu.h and drop the redundant `extern`
declarations in arm_core_mpu.c and the userspace memory protection
test.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Complier complains that idx_e may be used uninitialized.
So set the default as 0 so that the for loop where it can be
used uninitialized would be an no-op.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some issues found with previous region add mechanism:
() Previous mechanism cannot add new entry before the first
enabled entry.
() There are some cases where inserting a region would not
preserve access rights and memory type correctly.
This reworks the mechanism to fix these issue. Also remove
assertion within mpu_map_region_add() and let the caller
decide what to do.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With the xtensa_mpu_mem_type_ranges[] array, the SoC or board
should be the one dictating memory types of various memory
regions. There is no need for this kconfig to be there and
we can use the defaults for the architecture.
Note that the previous P_NA_U_NA access rights are replaced
with the default one, as it should reflect the background map
where it is be used.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If xtensa_user_stack_perms() fails to add stack space to the MPU
map, we must bail as the MPU map would not have the correct
permissions for the thread stack. However, ASSERT() cannot be
used at this point as we are running in privilege stack and yet
the thread has K_USER option set. Logging would go through
the syscall path (due to K_USER bit), and arch_buffer_validate()
on the runtime built assertion string would fail due to it being
in the privilege stack. So use arch_syscall_oops() here to bail
or else we would get cryptic error messages.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Having different signature for xtensa_mpu_map_write() based on
kconfig is error-prone. So fix that.
Rename xtensa_mpu_map_write() to xtensa_map_thread_map_write()
to reflect this change and to signify that it takes thread
pointer as argument.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The userspace code calls xtensa_mpu_map_write() anyway after
calling xtensa_user_stack_perms(), so there is no need to
write the MPU map whiling setting user stack permissions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rework consolidate_entries() to make it more robust. Now it only
checks a pair of entries at a time to see if one can be removed.
If so, remove one and restart the whole process. The previous
mechanism does not look back at previous entries (as index is
monotonically increasing) and we may miss some opportunities to
further compact the map.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Similar to find_boot_permission(), find_memory_type() needs to
go through the whole xtensa_mpu_mem_type_ranges[] array to find
the memory type. This allows defining a big region earlier and
then gradually having smaller region for finer control.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
CONFIG_LINKER_USE_PINNED_SECTION is the second half of the selective
kernel-pinning model removed in issue #108773. With the kernel image
now always resident at boot (previous commit), the __pinned_*
attribute family is a no-op: every page they would have segregated is
already pinned by z_mem_manage_init()'s whole-image loop, so the
tagging contract neither adds safety nor remains maintainable.
Drop it.
Mechanical removals:
* All ~219 in-tree uses of __pinned_text, __pinned_rodata,
__pinned_data, __pinned_bss, __pinned_noinit, and __pinned_func
across arch/x86, drivers/interrupt_controller, drivers/timer,
arch/common, kernel, lib/libc, subsys/portability/posix, tests, and
the syscall code generator (scripts/build/gen_syscalls.py).
* The assembly aliases PINNED_TEXT/RODATA/DATA/BSS/NOINIT used in
arch/x86/core/ia32/*.S and drivers/interrupt_controller/
intc_loapic_spurious.S become plain TEXT/RODATA/DATA/BSS/NOINIT.
* K_KERNEL_PINNED_STACK_DEFINE, K_KERNEL_PINNED_STACK_ARRAY_DEFINE,
K_KERNEL_PINNED_STACK_ARRAY_DECLARE, K_THREAD_PINNED_STACK_DEFINE,
and K_THREAD_PINNED_STACK_ARRAY_DEFINE are removed. The few
in-tree callers (kernel/init.c, arch/arm/core/cortex_a_r/smp.c,
arch/arm64/core/fatal.c, arch/rx/core/prep_c.c,
arch/x86/core/prep_c.c, kernel/include/kernel_internal.h,
tests/bluetooth/hci_uart_async) move to the corresponding
non-pinned macros.
Machinery removals:
* Kconfig.zephyr drops CONFIG_LINKER_USE_PINNED_SECTION.
qemu_x86_tiny and qemu_x86_atom_virt drop their =y overrides.
* include/zephyr/linker/section_tags.h drops the __pinned_* macro
definitions (both arms). __isr collapses to an empty macro since
its only purpose was to alias __pinned_func.
* include/zephyr/linker/sections.h drops PINNED_TEXT_SECTION_NAME,
PINNED_BSS_SECTION_NAME, etc. and the bare PINNED_TEXT/RODATA/etc.
forwarders, plus the _APP_SMEM_PINNED_SECTION_NAME constant.
* include/zephyr/linker/linker-defs.h drops the lnkr_pinned_*
externs, the _app_smem_pinned_* externs, and the lnkr_is_pinned()
/ lnkr_is_region_pinned() inline helpers.
* include/zephyr/linker/utils.h drops the lnkr_pinned_rodata branch
in linker_is_in_rodata().
* include/zephyr/linker/app_smem_pinned{,_aligned,_unaligned}.ld
are deleted; cmake/linker/ld/target_configure.cmake stops
configuring them.
* boards/qemu/x86/qemu_x86_tiny.ld and
include/zephyr/arch/x86/ia32/linker.ld drop their pinned-section
blocks and the now-redundant #ifndef CONFIG_LINKER_USE_PINNED_SECTION
conditionals throughout the body. The
LIB_KERNEL_IN_SECT / LIB_ARCH_X86_IN_SECT / LIB_ZEPHYR_IN_SECT /
LIB_C_IN_SECT / LIB_DRIVERS_IN_SECT / LIB_SUBSYS_LOGGING_IN_SECT /
LIB_ZEPHYR_OBJECT_FILE_IN_SECT / ZEPHYR_KERNEL_FUNCS_IN_SECT macros
in qemu_x86_tiny.ld are deleted; they existed only to feed the
pinned text/rodata/data/bss/noinit sections.
* kernel/mmu.c drops the mark_linker_section_pinned(lnkr_pinned_start,
...) call. The mark_linker_section_pinned() helper survives but is
now gated only on CONFIG_LINKER_USE_BOOT_SECTION.
* arch/common/init.c and include/zephyr/arch/common/init.h drop
arch_bss_zero_pinned(); arch/x86/core/ia32/crt0.S drops the call
to it.
* arch/x86/core/userspace.c drops the eager k_mem_page_in() of the
thread's privileged stack on user-mode entry. With the kernel
image fully resident the stack is already mapped.
* arch/x86/gen_mmu.py drops map_region("lnkr_pinned") and the
set_region_perms() calls for lnkr_pinned_text / lnkr_pinned_rodata.
* CMakeLists.txt drops the LINKER_USE_PINNED_SECTION block that
generated APP_SMEM_PINNED_* variables and the
pinned_partitions target property feeding gen_app_partitions.py.
cmake/modules/extensions.cmake removes the PINNED_RODATA /
PINNED_RAM_SECTIONS / PINNED_DATA_SECTIONS zephyr_linker_sources()
location keywords and their snippet files.
scripts/build/gen_app_partitions.py drops --pinoutput /
--pinpartitions arguments and the pinned-output branch.
subsys/testsuite/coverage/CMakeLists.txt drops its
CONFIG_DEMAND_PAGING-conditional fork.
* scripts/build/gen_kobject_list.py drops the
app_smem_pinned_start / _end fallback for kobject placement
validation.
* tests/arch/x86/pagetables and tests/kernel/mem_protect/userspace
drop their lnkr_pinned_text / lnkr_pinned_rodata branches.
* include/zephyr/arch/x86/ia32/arch.h folds IRQSTUBS_TEXT_SECTION
to the unconditional ".text.irqstubs" form.
* tests/subsys/llext/src/syscalls_ext.c drops a stale comment about
syscalls landing in .pinned_text.
Targeted retentions:
* arch/x86/core/bootargs.c keeps multiboot_cmdline and efi_bootargs
in .noinit (was __pinned_noinit, which decayed to __noinit when
LINKER_USE_PINNED_SECTION was unset). The multiboot and zefi loader
paths write these buffers before Zephyr's BSS-zero step, so
zeroing them at boot loses the cmdline.
* arch/x86/core/ia32/fatal.c keeps _df_esf and _df_stack in .noinit.
They are scratch space written by the double-fault handler and have
no zero-init requirement; keeping them in .noinit also preserves
the historical post-noinit alignment that gen_mmu.py relies on
(z_mapped_size is computed before CMake-injected iterable sections
are appended to the linker script, so the post-noinit page padding
is what keeps those sections within the mapped region).
* include/zephyr/arch/x86/ia32/syscall.h and
include/zephyr/arch/x86/arch.h wrap the per-arch
arch_syscall_invoke* / arch_is_user_context / arch_k_cycle_get_*
implementations in @cond INTERNAL_HIDDEN. The public Doxygen
contract lives on the prototypes in
include/zephyr/arch/arch_interface.h; the per-arch implementations
are internal. Without this, removing the __pinned_func attribute
exposes the implementations to the doxygen-coverage delta check
as 10 newly-undocumented APIs.
Documentation updates are deferred to a separate commit.
Issue: #108773
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
With qemu_x86_tiny moved off the =n side of this knob in the previous
commit, no in-tree configuration sets
CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT=n anymore. The mode it
selected is also unsafe by construction (issue #108773), so there is
nothing to deprecate -- drop the Kconfig symbol and every #ifdef on
it.
Consequences:
* z_mem_manage_init() pins the whole Zephyr image unconditionally and
no longer calls arch_bss_zero() after demand-paging init. The
pinning loop's TODO about "we will need linker regions for a subset
of kernel code/data pages which are pinned in memory and may not be
evicted" is replaced with a brief note that the kernel image is
always resident now and that pageable kernel regions go through
__ondemand_*.
* arch/x86/core/ia32/crt0.S always calls arch_bss_zero() once
arch_bss_zero_boot and arch_bss_zero_pinned have run.
* kernel/kheap.c and kernel/userspace/userspace.c drop the
pre-kernel/post-kernel "skip non-pinned" dance and zero/init each
heap and app-shmem partition unconditionally at PRE_KERNEL_1.
* arch/x86/core/userspace.c drops the eager k_mem_page_in() of the
thread's privileged stack before dropping to user mode -- with the
full kernel image resident the stack is already mapped.
* arch/x86/gen_mmu.py always maps the Zephyr image with FLAG_P set
(and lnkr_boot_* / lnkr_pinned_* regions just inherit that).
* CMakeLists.txt no longer force-pins z_libc_partition into
pinned_partitions for app_smem.
* The EVICTION_LRU gate
"depends on LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT" goes away;
LRU is now safe by construction on any DEMAND_PAGING board and
becomes the default whenever ARCH_SUPPORTS_EVICTION_TRACKING.
* DEMAND_PAGING_PAGE_FRAMES_RESERVE loses its conditional default of
32 frames; the new model needs no reserve.
* boards/qemu/x86/qemu_x86_tiny.ld drops the FLASH MEMORY region and
the flash_load_offset block that arranged the demand-paged
generic-section layout. boards/qemu/x86/board.cmake drops the
8 MB-RAM bump and the --map flash gen_mmu argument that paired with
that mode.
* tests/arch/x86/pagetables and tests/kernel/fatal/exception drop the
code paths that were guarded on =n.
* tests/kernel/mem_protect/demand_paging/mem_map.lru replaces its
CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT=y override with an
explicit CONFIG_EVICTION_LRU=y, since the symbol it relied on is
gone.
The __pinned_* tagging convention still expands to its actual linker
sections under CONFIG_LINKER_USE_PINNED_SECTION; that symbol and the
~219 in-tree __pinned_* annotations are cleaned up in the following
commit.
Issue: #108773
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
TLS area must be defined also when multithreading is disabled. Not doing
so whould cause access to libc variables like 'errno' to fail with a
crash.
This commit adds the TLS area for the single thread case by reserving
some space at the top of the main stack area.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
As a part of the AIA specification two new extensions were introduced:
Smaia (Supervisor Machine AIA) and Ssaia (Supervisor Software AIA).
Support is added for these 2 extensions
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Add macros to read and write CSRs with immediates and use them for
setting userspace blocker in PMP instead of the existing helpers.
This makes the code simpler than with the large switch statement
and should be a bit more efficient.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
Move EXECUTE_XOR_WRITE back into userspace and update the comment
to reflect that it only applies to memory partitions.
PMP_DATA_EXECUTION_PREVENTION is now independent from it and no
longer a requirement.
For full protection both options should be enabled. Otherwise,
some data areas my be left executable and writable at the same
time.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
When set_userspace_blocker is called on context switches between
user and kernel, read only the required pmpcfg register instead
of all.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
CONFIG_EXECUTE_XOR_WRITE now depends on
PMP_DATA_EXECUTION_PREVENTION, which in turn selects
PMP_KERNEL_MODE_DYNAMIC if user space is enabled. Another new
config PMP_KERNEL_MODE_DYNAMIC_CATCHALL indicates whether dynamic
catch-all programming is required.
This simplifies the code structure.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
Remove userspace blocker in z_riscv_pmp_kernelmode_enable. This way
data execution will not only be blocked in kernel threads but also
during kernel execution in syscalls on behalf of user threads.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
CONFIG_EXECUTE_XOR_WRITE is a basic countermeasure to prevent code
injection attacks by making data non-executable. This can be done
on RISC-V with PMP by removing the executable permission.
Since PMP slots are statically prioritized, we can add a region
covering the whole address space into the last register giving
only read-write access. This will be overridden by any other
configured register with lower index so that the code region
remains executable.
In order to make this register apply to kernel threads in M mode,
it needs to be locked, but this means we cannot remove it anymore.
For CONFIG_USERSPACE we therefore need to reserve another register
so that we can add another address space-wide region with higher
priority without any permission to override the last one and limit
user threads to their assigned regions. This needs to be removed
when switching from user to kernel threads, which is done in the
new function z_riscv_pmp_usermode_disable.
This feature simplifies CONFIG_PMP_KERNEL_MODE_DYNAMIC because we
already have a catch-all register for kernel threads.
Does not work with CONFIG_CODE_DATA_RELOCATION for now and requires
PMP region locking.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
Replace the opt-in locked marker with a legacy unlocked marker. With
this, SoC PM hooks use the locked IRQ contract by default, and only
legacy SoCs that still unmask interrupts from PM hooks select
PM_STATE_SET_IRQ_UNLOCKED.
Drop the old locked marker selections from already migrated NXP SoCs and
update the PM test expectation accordingly.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
This commit fixes a silent SMP hang on platforms where CPUs are
reported as MADT Type 9 (x2APIC) entries with non-sequential APIC
IDs. Zephyr only queried Type 0 (xAPIC) entries, leaving
x86_cpu_loapics[] as zero and sending the startup IPI to the wrong
CPU.
Add Type 9 (x2APIC) as the preferred MADT lookup in arch_cpu_start()
when CONFIG_X2APIC is enabled, with Type 0 (xAPIC) retained as
fallback for platforms that only publish xAPIC entries.
Signed-off-by: S Swetha <s.swetha@intel.com>
This commit introduces a fix for a silent SMP hang on systems that
report CPUs as MADT Type 9 (x2APIC) entries. On such systems, the
hardware operates in x2APIC mode where the xAPIC MMIO registers are
inaccessible. Secondary CPUs were reading their APIC ID from the
xAPIC MMIO register, causing an access fault and looping forever in
unknown_loapic_id, resulting in a silent SMP hang.
Read the 32-bit APIC ID from MSR 0x802 via rdmsr when CONFIG_X2APIC
is enabled, falling back to the xAPIC MMIO register when
CONFIG_X2APIC is disabled.
Signed-off-by: S Swetha <s.swetha@intel.com>
This commit adds acpi_local_x2apic_get() to retrieve MADT Type 9
(x2APIC) local APIC entries by CPU index. Previously, only Type 0
(xAPIC) entries could be queried via acpi_local_apic_get(). On
systems that report CPUs exclusively as Type 9 entries, there was
no way to retrieve the 32-bit x2APIC ID needed for CPU startup.
The function iterates over enabled MADT Type 9 entries and returns
the entry corresponding to the requested CPU index.
Signed-off-by: S Swetha <s.swetha@intel.com>
arm_m_switch_stack_buffer is only defined when CONFIG_USE_SWITCH is
enabled. With link-time optimization or certain no-optimization builds
using Clang, the symbol is referenced unconditionally and the linker
fails with:
ld.lld: error: undefined symbol: arm_m_switch_stack_buffer
Move the reference inside a preprocessor guard so that the symbol is
only accessed when the kernel is built with CONFIG_USE_SWITCH.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A component should not rely on the API it is implementing.
In this case, the arch layer is implementing the arch cache API
(include/zephyr/arch/cache.h), that is used by the public sys cache
API (include/zephyr/cache.h), so it can't call the latter.
Furthermore, it does not implement arch_cache_data_line_size_get(),
so sys_cache_data_line_size_get() will always give the value of
CONFIG_DCACHE_LINE_SIZE.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add support for generating llext veneers for Arm baseline cores.
The veneer is AAPCS-compliant: r0-r3, r5-r11 and LR are preserved,
r4 is saved and restored, and only r12 (ip) is clobbered as
permitted by AAPCS.
Tested on RP2040 (Cortex-M0+) loading an extension that calls
__gnu_thumb1_case_uqi.
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
Enabling the FPU forces the choice between CONFIG_FP_HARDABI
and CONFIG_FP_SOFTABI. Both of these options allow the compiler
to generate FP instructions. As a result, all threads must have
the K_FP_REGS options bit set because we can not predict where
the compiler will generate those instructions.
The forced enablement is keyed off those ABI Kconfig options
and not FPU sharing nor the FPU enablement. This leaves the
option open for a future (as yet not implemented) case where
someone might want FPU support but not have the compiler generate
any FPU instructions at all.
Fixes#108793
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
The NMI is edge-triggered and not reflected in the INTERRUPT/INTENABLE
registers. Skip DEF_INT_C_HANDLER() for the NMI level and add a
dedicated xtensa_nmi_c() that directly invokes the registered ISR.
Update assembly vector dispatch to route the NMI level to the new
handler.
Signed-off-by: Sefa Celik <sefa.celik@analog.com>
Add support for the Cortex-A32 processor. The Cortex-A32 processor
is built on the ARMv8-A architecture and supports only the AArch32
execution state.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add CONFIG_AARCH32_ARMV8_A_MONITOR_INIT to perform early Monitor mode
(EL3 AArch32) initialization at reset, modelled after z_arm64_el3_init()
in the arm64 port.
On ARMv8-A AArch32 platforms booting bare-metal without Trusted
Firmware-A, the core resets into Secure SVC mode. Certain system
registers (such as ICC_MSRE for GICv3) are only accessible from Monitor
mode. This option briefly switches to Monitor mode at reset to configure
such registers before returning to Secure SVC mode.
Currently used to configure ICC_MSRE, which enables GICv3 CPU
interface system register access at lower privilege levels (equivalent
to ICC_SRE_EL3 in the arm64 port).
ICC_MSRE_INIT reuses the existing ICC_SRE_ELx_* bit definitions from
cpu.h as the AArch32 ICC_MSRE shares the same bitfield layout as its
AArch64 counterpart ICC_SRE_EL3.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add a new AARCH32_ARMV8_A Kconfig symbol for ARMv8-A processors
running in AArch32 execution state, modelled after the existing
ARMv8-R AArch32 support. ARMv8-A AArch32 execution state is used
by processors such as the Cortex-A32 that implement only the AArch32
state as well as by other ARMv8-A processors that support AArch32
at specific exception levels.
A dedicated Kconfig symbol is needed (compared to simply reusing
ARMV7_A)because ARMv8-A AArch32 shares some code paths with ARMv7-A
and others with ARMv8-R AArch32. This also means that rather than
introducing a new standalone architecture port, the implementation
selectively extends the code paths used by either of these
architectures based on the architectural requirements as detailed
below.
MMU/fault handling: The implementation uses the existing short
descriptor translation table format used by ARMv7-A, sharing
the MMU programming and FSR encodings.
exception modes stack initialization: ARMv8-A AArch32 implements the
same exception modes as ARMv7-A and so reuses the ARMv7-A exception
mode stack initialization framework directly.
VBAR programming: Unlike ARMv7-A, ARMv8-A AArch32 mandates the use of
VBAR to store the vector table base address. So extend the vector
table relocation support already used by ARMv8-R AArch32. Also map
the vectors region from arch-level code rather than requiring each
SoC to provide this.
Arm generic timer support: The Generic Timer is mandatory in ARMv8-A
AArch32 and is accessed via the system register interface rather than
the memory-mapped I/O interface used by some ARMv7-A implementations.
The system-register-based timer path is therefore shared with ARMv8-R
AArch32.
interrupt masking: Reuse the CPSR based interrupt masking used by
ARMv7-A and ARMv8-R AArch32.
SVC based fatal error path: Reuse the SVC based fatal error path
shared by ARMv7-A and ARMv8-R AArch32.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
We have two custom EXCCAUSE numbers to be used for raising
our own custom exceptions. Instead of having magic numbers
in the code, we give them names.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Initialize interrupt stacks for all secondary CPUs during z_prep_c()
when CONFIG_INIT_STACKS is enabled, preventing uninitialized stack
detection from reporting 100% usage on secondary CPU IRQ stacks.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Update common AIA coordinator shared by IMSIC and direct mode to
initialize based on which APLIC mode is configured in DT.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
