xtensa: gdbstub: add arch_gdb_post_memory_write()
This adds arch_gdb_post_memory_write() to deal with caching after GDB writing to memory. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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@ -7,6 +7,7 @@
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#include <zephyr/kernel.h>
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#include <kernel_internal.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/arch/xtensa/cache.h>
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#include <zephyr/debug/gdbstub.h>
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#include <xtensa_asm2_context.h>
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@ -987,3 +988,35 @@ void arch_gdb_init(void)
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*/
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__asm__ volatile ("_break.n 0");
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}
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void arch_gdb_post_memory_write(uintptr_t addr, size_t len, uint8_t align)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(len);
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ARG_UNUSED(align);
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#if defined(CONFIG_ICACHE) && defined(CONFIG_DCACHE)
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/*
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* Note that a GDB memory write can write to code memory to
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* insert breakpoints. We need to deal with this here so
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* that the instruction cache can actually see the modified
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* instructions.
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*
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* According to the ISA manual, after writing the instructions:
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* 1. Flush the data cache so the modified instructions are
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* in the main memory.
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* 2. Do ISYNC or MEMW or both (depending on which part of
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* manual you are reading).
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* 3. Invalidate the instruction cache corresponding to
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* the modified memory.
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* 4. Do another ISYNC.
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*/
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arch_dcache_flush_range(addr, len);
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__asm__ volatile("isync; memw");
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arch_icache_invd_range(addr, len);
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__asm__ volatile("isync");
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#endif /* CONFIG_ICACHE && CONFIG_DCACHE */
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}
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