Commit graph

6012 commits

Author SHA1 Message Date
Jisheng Zhang
13bdae0ad0 arch: arm: Add initial support for Cortex-M52 Core
Add initial support for the Cortex-M52 Core which is an implementation
of the Armv8.1-M mainline architecture.

The support is based on the Cortex-M55 support that already exists in
Zephyr.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
2025-08-06 12:15:23 +03:00
Fabio Baltieri
a763207962 arch: arm: dwt: use the cmsis_6 macro unconditionally
Always use the cmsis_6 version for DWT_LSR_Present_Msk and
DWT_LSR_Access_Msk, the old ones are not going to be available anymore
when Cortex-M is selected..

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2025-08-05 11:54:18 +01:00
Michele Sardo
958bec0df4 arch: arm: add Cortex-M MPU context save/restore API
Add struct z_mpu_context_retained and parameterized functions
z_arm_save_mpu_context() and z_arm_restore_mpu_context() to allow
saving and restoring MPU configuration to/from retained RAM.

This enables preserving MPU state across deep sleep or power-down
modes on Cortex-M devices.

The API is exposed under include/zephyr/arch/arm/mpu/arm_mpu.h
and implemented in arch/arm/core/mpu/arm_mpu.c.

Signed-off-by: Michele Sardo <msmttchr@gmail.com>
2025-08-04 17:04:01 -04:00
Peter Mitsis
4cc973986d arch: Update arch_is_in_isr() SMP implementations
Fixes a flaw in implementations of arch_is_in_isr() that could manifest
on SMP systems. If the reading of the current CPU's nested interrupt
count is not fully atomic on an SMP system, then an ill-timed context
switch could occur leaving the caller reading the nested interrupt
count of a different CPU.

This also applies a little defensive programming to cortex_a_r's
arch_is_in_nested_exception(). Although this routine is presently
only called with interrupts locked (which will prevent the thread
from migrating), switching to use _current_cpu instead of
arch_curr_cpu() is safer as should the routine ever be called
without meeting the locking criteria, it can be detected and fixed.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-08-02 13:19:56 +02:00
Peter Mitsis
85b8ae9b6a arch: xtensa: Fix arch_is_in_isr() race condition
Fixes a flaw in the the xtensa implementation of arch_is_in_isr()
that could manifest on SMP systems. If the reading of the current
CPU's nested interrupt count is not fully atomic on an SMP system,
then an ill-timed context switch could occur leaving the caller
reading the nested interrupt of a different CPU.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-08-02 13:19:21 +02:00
Lauren Murphy
a444f7ded8 llext: add reloc and symbols for mwdt
Adds relocation and symbols generated by MWDT while using it
for NSIM VPX5.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2025-08-01 19:36:59 +01:00
Gaetan Perrot
b59d9f2f85 arch: riscv: core: fpu: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-08-01 07:54:11 -04:00
Gaetan Perrot
470f3aff83 arch: riscv: core: pmp: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-08-01 07:54:11 -04:00
Gaetan Perrot
6f8453f39d arch: sparc: core: thread: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-08-01 07:54:11 -04:00
Gaetan Perrot
46341938eb arch: xtensa: core: thread: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-08-01 07:54:11 -04:00
Tom Hughes
ea5412ece4 arch: arm: cortex_m: Add debug.h header
Since #75677, it has not been possible to build with
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT enabled since there was no
declaration of z_arm_debug_enable_null_pointer_detection before its use
in arch/arm/core/cortex_m/prep_c.c.

This change creates an arch/arm/include/cortex_m/debug.h header that
contains declarations for the functions in
arch/arm/core/cortex_m/debug.c.

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-08-01 07:47:28 -04:00
Guennadi Liakhovetski
9ce6d3599c xtensa: export syscall helpers
When building with user space and LLEXT support, syscall helpers need
to be exported.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2025-08-01 07:45:16 -04:00
Mike J. Chen
2dc6793261 soc: imxrt5xx: add fusion f1 dsp backtrace support
Add needed backtrace helpders routines and enable
backtrace for the Xtensa Fusion F1 DSP in the
IMXRT595S.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2025-07-31 10:49:54 +01:00
Martin Hoff
d5f67d04ee arch: split dynamic interrupt symbol
This commit introduces the SRAM_SW_ISR_TABLE option which is selected by
DYNAMIC_INTERRUPT. It allows splitting the DYNAMIC_INTERRUPT option into
two parts:

 - One for the relocation of the ISR vector table in RAM
 - One for the inclusion of functions needed to install ISRs dynamically

The goal is to later only select the relocation of the ISR vector table in
RAM and not all the associated functions from the dynamic interrupt
mechanism.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2025-07-30 17:37:43 -04:00
Nicolas Pitre
e6ff6b0843 arm64: isr_wrapper.S: make GICv2 usable on SMP systems
GICC_IAR (GICv2) includes the source processor for SGIs in bits 12-10.
Mask them away otherwise IPIs sent from any CPU other than CPU0 will be
considered out of bounds.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2025-07-29 22:53:08 -04:00
Afonso Oliveira
b4eb116478 arch: riscv: decouple mtval usefulness for FP traps from QEMU target
Introduce CONFIG_RISCV_NO_MTVAL_ON_FP_TRAP to handle implementations
where the mtval CSR does not provide useful information during
floating-point illegal instruction exceptions.

The RISC-V specification states that mtval is "either set to zero or
written with exception-specific information" on traps. Some
implementations, including QEMU, do not populate mtval with the
faulting instruction value during FP-related illegal instruction
exceptions, making it unusable for FP exception handling.

Previously, this behavior was hardcoded for QEMU targets only, but
other CPU implementations may also lack useful mtval content for FP
traps. Decoupling this from CONFIG_QEMU_TARGET and allows other
platforms to properly declare this limitation.

The new Kconfig option defaults to enabled for QEMU targets to
maintain backward compatibility.

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
2025-07-29 22:52:37 -04:00
Mathieu Choplain
cba9dceff4 Revert "arch: arm: cortex_m: Add API for scb save and restore"
This reverts commit a90a47b1c9.

This commit was written with CMSIS 5 in mind, where some Cortex-M cores
have "SHP" in the SCB_Type, and some have "SHPR". This is not correct as
Zephyr is *supposed* to be using CMSIS 6 for Cortex-M... but CI actually
picks up CMSIS 5 instead (it includes both with CMSIS 5 taking priority).

The end result is that Zephyr's CI builds this happily but it causes build
failures on downstream users (e.g., example-application).

Revert the commit now, as it is not used yet by anyone. The revised version
using only "SHPR" shall be reintroduced once the CI issue has been fixed.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-07-25 11:20:12 +01:00
Michele Sardo
a90a47b1c9 arch: arm: cortex_m: Add API for scb save and restore
Add two API to save SCB context and restore it, typically
used in suspend to RAM use case.

The scb_context_t and the backup/restore functions are designed to only
handle SCB registers that are:
- Mutable: Their values can be changed by software.
- Configurable: They control system behavior or features.
- Stateful: Their values represent a specific configuration that an
            application might want to preserve and restore.

Register excluded from backup/restore are:
1.	CPUID (CPUID Base Register)
	Motivation for Exclusion: This is a read-only identification register.
2.	ICSR (Interrupt Control and State Register)
	Motivation for Exclusion (from restoration): While its current value
	can be read, directly restoring a saved	ICSR value is highly
	dangerous and generally unsafe in an RTOS context.
	Contains Read-Only Status Bits: A significant portion of ICSR
	consists of read-only bits (VECTACTIVE, VECTPENDING, ISRPREEMPT,
	TSRUNPEND). These bits reflect the current state of the exception
	system (e.g., which exception is active, which are pending) and are
	managed dynamically by the CPU and the RTOS.
	Forcing a previous state onto these bits would corrupt the live
	system's interrupt handling.
	Contains Write-Only Set/Clear Bits: Some bits are write-only to set
	or clear a pending interrupt (PENDSVSET, PENDSVCLR, SYSTICKSET,
	SYSTICKCLR). If these bits were set in the saved context, restoring
	them might immediately trigger an interrupt or change its pending state
	unexpectedly, outside the RTOS's control.
	RTOS Management: In Zephyr (and other RTOSes), the kernel tightly
	manages the interrupt and exception state.
	Direct manipulation of ICSR's volatile bits could conflict with the
	RTOS's internal state machine, leading to crashes or unpredictable
	behavior.
3.	CFSR (Configurable Fault Status Register)
	Motivation for Exclusion: This is a read-only status register that
	reports the current state of Memory Management, Bus Fault, and Usage
	Faults. It's used by fault handlers to determine the cause of a fault.
4.	HFSR (HardFault Status Register)
	Motivation for Exclusion: Similar to CFSR, this is a read-only status
	register that reports the current state	of HardFaults. It's for
	reporting, not for configuration or restoration.
5.	DFSR (Debug Fault Status Register)
	Motivation for Exclusion: This is a read-only status register that
	reports debug-related faults. It's primarily used by debuggers and
	is not part of the application's runtime context to be saved/restored.
6.	MMFAR (MemManage Fault Address Register)
	Motivation for Exclusion: This is a read-only register that stores the
	address that caused a Memory Management	fault. It's a diagnostic
	register, not a configurable parameter.
7.	BFAR (BusFault Address Register)
	Motivation for Exclusion: Similar to MMFAR, this is a read-only
	register that stores the address that caused a BusFault. It's a
	diagnostic register.
8.	AFSR (Auxiliary Fault Status Register)
	Motivation for Exclusion: This register is implementation-defined and
	read-only.

Signed-off-by: Michele Sardo <msmttchr@gmail.com>
2025-07-24 16:59:59 +01:00
Guennadi Liakhovetski
1dbca21fa2 gdb: xtensa: fix sparse warnings
Fix a sparse memory attribute mismatch.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2025-07-21 13:03:30 -04:00
Peter Mitsis
e50851d476 arch: xtensa: Add support for lazy HiFi ctx switching
When lazy HiFi context switching is enabled, the system starts with
the HiFi coprocessor disabled. Should the thread use that coprocessor,
it will generate an exception which in turn will enable the coprocessor
and save/restore the HiFi registers as appropriate. When switching
to a new thread, the HiFi coprocessor is again disabled.

For simplicity, there are no restrictions as to which thread is allowed
to use the coprocessor.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-07-20 12:25:17 -04:00
Peter Mitsis
d397a91c62 kernel: Add arch_coprocessors_disable()
The intent of arch_coprocessors_disable() is to replace
arch_float_disable() in halt_thread() for the FPU will not
always be the only coprocessor that will need to be disabled.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-07-20 12:25:17 -04:00
Peter Mitsis
6505cf2e54 arch: xtensa: Carve space for saved HiFi regs
As the BSA can not be used when lazy HiFi context switching is
used, a more permanent and predictable location in which to store
the registers is required. To this end ...
  1. reserve some space in the arch-specific portion of the k_thread
     structure for those registers.
  2. clear that region when the thread is created.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-07-20 12:25:17 -04:00
Peter Mitsis
cd351208d5 arch: xtensa: Refine HiFi sharing Kconfigs
Splits HiFi sharing into two different models.
 1. XTENSA_EAGER_HIFI_SHARING - unconditional save/restore
    of the HiFi registers when context switching
 2. XTENSA_LAZY_HIFI_SHARING - on demand save/restore of
    of the HiFi registers. If a thread does not use the
    HiFi registers, they are neither saved nor restored.

To maintain backwards compatibility, the eager model is the
default model when XTENSA_HIFI_SHARING is enabled.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-07-20 12:25:17 -04:00
Anas Nashif
0a4e27c45f xtensa: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
2b93450b59 sparc: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
9a7b28bc23 rx: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
effa4bb217 riscv: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
450f0bba7a mips: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
fbb701371d x86: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
2463996105 arm64: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
9867c0979c arm: use EXCEPTION_DUMP macro for fatal messages
instead of depending on logging for exceptions and fatal messages, use
macro and dump exceptions if printk is enable with no logging.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
89261db819 arch: arc: use common exception printing macros
ARC was using this method already in a custom way and was different from
all other architectures, lets make this generic.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Anas Nashif
81fe171ce7 arch: unify how we include exception.h
Just include <zephyr/arch/exception.h> in architecture code. The file
redirects to the correct implementation.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-19 15:49:28 -04:00
Stephanos Ioannidis
dc3c9f3560 arch: riscv: Introduce code model options
This commit introduces a new Kconfig choice for configuring the code model
used for compilation.

All three code models specified by the RISC-V ELF psABI specification are
supported: medlow, medany and large.

For RV32, the `medlow` code model is always selected.
For RV64, the `large` code model is selected if the SRAM or kernel VM base
address is greater than or equal to 4 GiB; otherwise, the `medany` code
model is selected.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2025-07-19 15:43:09 -04:00
Stephanos Ioannidis
f5000936a8 arch: riscv: Add Zicntr extension support
This commit introduces the support for the standard Zicntr extension, which
provides hardware counters.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2025-07-19 15:42:57 -04:00
Stephanos Ioannidis
58a6a696a0 arch: riscv: Add Zc* compressed instruction extension support
This commit adds the support for the following new Zc* series compressed
instruction extensions:

  Zca  - Subset of the C extension without FP loads and stores
  Zcb  - "Simple" instructions
  Zcd  - Double-precision floating-point instructions
  Zcf  - Single-precision floating-point instructions
  Zcmp - "Complex" instructions for embedded CPUs
  Zcmt - Table jump instructions for embedded CPUs

With the introduction of the Zc* extensions, the C extension now implies
the following Zc* extensions:

  * Zca, always
  * Zcf if F is specified (RV32 only)
  * Zcd if D is specified

The Zc* extensions that are implied by the C extension are not specified in
the GCC `-march` flag because they are redundant and can interfere with the
resolution of the correct multi-lib for the selected architecture unless
the the alternate mappings for the redundant forms are manually specified.

All the implementation details in this commit are based on the Zc* v1.0.0
specification, which is the ratified version.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2025-07-19 15:32:35 -04:00
Daniel DeGrasse
7b4d2759bf arch: arc: support CONFIG_ROM_START_OFFSET
Add support for CONFIG_ROM_START_OFFSET on ARC processors. Note that the
arc ISA requires vector table offset to be at a 1024 KiB boundary, so
the default ROM_START_OFFSET when using MCUBoot must be increased.

Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
2025-07-19 15:32:03 -04:00
Daniel DeGrasse
e22166f50b arch: common: add CONFIG_ARCH_SUPPORTS_ROM_OFFSET
Add CONFIG_ARCH_SUPPORTS_ROM_OFFSET, a convenience Kconfig to indicate
that CONFIG_ROM_START_OFFSET is supported on this architecture

Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
2025-07-19 15:32:03 -04:00
Michele Sardo
5981dc8ee1 arch: arm: cortex_m: Modifed FPU save and restore helpers
z_arm_save_fp_context and z_arm_restore_fp_context
save and restore fpu context regardless of the
CONFIG_FPU_SHARING setting.

This modification is required to support suspend to ram use cases
where save and restore of FPU state is needed to ensure proper bahaviour
after wakeup.

Signed-off-by: Michele Sardo <michele.sardo@st.com>
2025-07-19 13:45:07 -04:00
Yanir Levin
6df14b432e arc: cache: Support region operations, SLC, and entire cache operations
Added configurable support for L1 cache region operations,
which offers improved performance over line operations.
Added configurable support for SLC (system level cache).
Added support for entire cache operations: flush_all,
invd_all, flush_and_invd_all.

Reviewed-by: Aaron Komisar <aaron.komisar@tandemg.com>
Signed-off-by: Yanir Levin <ylevin@gsitechnology.com>
2025-07-19 09:42:20 +02:00
Alberto Escolar Piedras
e150ffb92c arch/posix: Remove support for CONFIG_NATIVE_APPLICATION
CONFIG_NATIVE_APPLICATION, which represents the way in which
native_posix and its kin were built, was deprecated in 4.1 after the
introduction of native_sim and CONFIG_NATIVE_LIBRARY.

We remove support for it now for 4.3.

Let's remove the architecture layer adaptation code and cmake support.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2025-07-19 09:38:15 +02:00
Gaetan Perrot
3962dab707 arch: arm64: core: fpu: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-07-11 08:18:43 -10:00
Gaetan Perrot
92826ff312 arch: arm64: core: fatal: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-07-11 08:18:29 -10:00
Gaetan Perrot
503011d0a2 arch: arm: core: cortex_a_r: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-07-09 00:26:17 -05:00
Gaetan Perrot
3aa477ba2e arch: arm: core: cortex_a_r: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-07-09 00:25:52 -05:00
Gaetan Perrot
3e9eea2cc1 arch: arm: core: cortex_m: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-07-08 18:35:14 -05:00
Gaetan Perrot
eb7fe02aac arch: arm: core: elf: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-07-08 18:35:00 -05:00
Gaetan Perrot
a4fc6723ac arch: arm: core: cortex_m: mark unused function argument
Use ARG_UNUSED() to mark unused function argument.

Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
2025-07-08 18:34:49 -05:00
Anas Nashif
7f282f7928 xtensa: tracing: instrument thread switching
Add missing call to thread_switched_in for the purpose of tracing.

Fixes zephyrproject-rtos/zephyr#76057

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-07-08 18:34:11 -05:00
Stephanos Ioannidis
d7d3ae5c3b arch: arm: cortex_m: Force literal pool placement in inline asm block
When LTO is enabled, linker may relocate literal pools out of Thumb LDR
instruction's reach causing "offset out of range" errors while linking.

This commit adds `.ltorg` directive in the inline asm blocks where absolute
addresses are loaded using the `ldr` instructions, in order to ensure that
the literal pool containing the absolute addresses are placed near the
`ldr` instructions.

Note that the `.ltorg` directive is recognised by all toolchains supported
by Zephyr and no toolchain abstraction is provided for now.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2025-07-07 10:13:06 -05:00