Commit graph

5846 commits

Author SHA1 Message Date
Daniel Leung
efb2a354a0 xtensa: coredump: support dumping privilege stack
Adds the bits to support dumping privilege stack during
coredump.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-21 11:29:39 +02:00
Daniel Leung
a3f4251ed5 x86: coredump: support dumping privilege stack
Adds the bits to support dumping privilege stack during
coredump.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-21 11:29:39 +02:00
Daniel Leung
4f52860fe0 debug: coredump: dump privileged stack
This adds the bits to call into architecture code to dump
the privileged stack for user threads.

The weak implementation is simply there as a stub until
all architectures have implemented the associated function.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-21 11:29:39 +02:00
Pisit Sawangvonganan
9955b0bd6f style: arch: remove unnecessary return statements
For code clarity, remove unnecessary `return` statements
in functions with a void return type they don't affect control flow.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-09-20 11:06:55 +02:00
Yong Cong Sin
b55f3c1c4f kernel: remove CONFIG_MP_NUM_CPUS
`CONFIG_MP_NUM_CPUS` has been deprecated for more than 2
releases, it's time to remove it.

Updated all usage of `CONFIG_MP_NUM_CPUS` to
`CONFIG_MP_MAX_NUM_CPUS`

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-19 18:28:37 +01:00
Tavish Naruka
b1af1928f8 cmake: set big-endian flags to TOOLCHAIN_*_FLAGS
Set -big-endian to both compiler and linker flags if
CONFIG_BIG_ENDIAN is set.

Signed-off-by: Tavish Naruka <t-naruka@ispace-inc.com>
2024-09-19 03:30:14 -04:00
Anas Nashif
7c90f1bca1 arch: arm64: init xen in arch_kernel_init()
Call xen_enlighten_init() from arch_kernel_init() instead of using
SYS_INIT.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
328f52b0ce x86: init spec_ctrl in prep_c, do not use SYS_INIT
Do not use SYS_INIT, call init script directly.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
7e225efab7 arch: initialize irq_offload during boot, do not use SYS_INIT
Do not use SYS_INIT for initializing irq_offload when enabled, instead
using a new interface that is called during the boot process for all
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
c9f7b512da arm: init null pointer detection in prep_c, do not use SYS_INIT
Do not use SYS_INIT for initializing null pointer detection, call
directly in prep_c.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
3e616cf4d3 arc: start secureshield in prep_c, do not use SYS_INIT
Initialize secureshield in prep_c instead of using SYS_INIT.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
2294da24d7 arc: start mpu in prep_c, do not use SYS_INIT
Initialize MPU in prep_c similar to how all other architectures do it,
avoid use of SYS_INIT.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Anas Nashif
6ec74d02b6 cache: add new interface arch_cache_init() for initializing cache
Add a new call for initializing cache on architectures that need that.
Avoid using SYS_INIT for this and instead call the hook in a fixed place
and run if implemented.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-17 20:05:22 -04:00
Christopher J. Champagne
63051bf71a xtensa: add kconfig to allow non-preemptible interrupts
This adds a kconfig to enable making the interrupts
non-preemptible by other interrupts. Enabling this will set
the INTLEVEL to the max non-debug level before clearing
the EXCM bit.

Signed-off-by: Christopher J. Champagne <christopher.j.champagne@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-17 14:54:19 -04:00
Weiwei Guo
88f6851a3d arch: common: Add user can specify the nocache location
nocache ram is usually used by DMA to transfer data between
peripherals and ram. Some chips use isolated nocache ram,
which does not necessarily have to be in RAMABLE-REGION.
By specifying the zephyr,nocache-ram options, users can specify
the region where nocache-ram is located. If the user does not
specify it, it defaults to RAMABLE-REGION.

Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
2024-09-17 09:45:35 +02:00
Gerard Marull-Paretas
a056b608f2 arch: arm: do not enable PLATFORM_SPECIFIC_INIT if SOC_RESET_HOOK=y
Otherwise we can't escape from DEPRECATED being selected, and so getting
build warnings. It doesn't make sense that the option replacing the
deprecated one is used to automatically enable it.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-09-16 15:12:18 -04:00
Daniel Leung
da5f7e1816 xtensa: mpu: update hardware if manipulating current domain
If adding/removing to the domain of the current running
thread, we need to update the hardware MPU regions or else
the addition or removal would not be reflected to current
running thread.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-16 09:55:53 +02:00
Daniel Leung
6bd0dcf920 xtensa: mpu: make sure write to MPU regions is atomic
This adds a spinlock to make sure writing to hardware MPU
regions is atomic, and cannot be interrupted until all
regions are written to hardware.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-16 09:55:53 +02:00
Yong Cong Sin
035c822253 arch: riscv: fill all IRQ stacks with 0xAA
Fill the memory of all CPU's IRQ stack with 0xAA on init, so
that `z_stack_space_get` can calculate the remaining space
correctly.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-13 09:17:34 +02:00
Adam Wojasinski
eb51529ab3 llext: Introduce AARCH64 relocation support
Adds support for all relocation type produced by GCC
on AARCH64 platform using partial linking (-r flag) or
shared link (-fpic and -shared flag).

Signed-off-by: Adam Wojasinski <awojasinski@baylibre.com>
2024-09-12 14:48:55 +02:00
Adam Wojasinski
44782ad2c1 llext: Move arm-specific relocation names from generic LLEXT file
Moved symbol definitions to the pleace where they are used.

Signed-off-by: Adam Wojasinski <awojasinski@baylibre.com>
2024-09-12 14:48:55 +02:00
Jiafei Pan
002ed73ff4 arm64: add sys_arch_reboot() support
If PSCI is enabled, it will leverage psci reset API to achieve system
reboot, otherwise a weak dump reboot API is provided, and platform
can override these APIs if platform specified implementation provided.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-09-12 10:03:52 +02:00
Nicolas Pitre
c99371e486 arm64: demand paging is supported
Test configs for UP and SMP are also included.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Nicolas Pitre
be279d878e arm64: demand_paging: add support for on-demand mappings
This makes ARM64 compatible with K_MEM_MAP_UNPAGED.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Nicolas Pitre
79428bc81d arm64: demand_paging: allow page fault processing with IRQs enabled
Convention is to call k_mem_page_fault() with IRQs enabled if they were
enabled when the fault occurred.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Nicolas Pitre
3e0feab245 arm64: demand_paging: add the k_mem_paging_eviction_accessed() call
Needed for the LRU eviction algorithm to be effective.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Nicolas Pitre
7bd6892750 arm64: mmu: access fault handler for demand paging
This has two purposes: maintain the accessed and dirty page states, or
call the generic demand paging fault handler otherwise.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Nicolas Pitre
322865773b arm64: mmu: architecture specific hooks for demand paging support
A page table entry used for demand paging is always from the last level
page table and never completely zeroed. Anything else is considered
ARCH_DATA_PAGE_NOT_MAPPED.

Loaded pages use a PTE_PAGE_DESC table entry type. Paged-out pages use a
PTE_INVALID_DESC table entry type and the physical address field is
reused to hold the backing store location token value.

ARCH_DATA_PAGE_ACCESSED corresponds to the AF flag. It is initially
unset and manually set to catch when pages are being accessed and
eventually do something about it.

ARCH_DATA_PAGE_DIRTY corresponds to the lack of the AP_RO flag.
Similarly to the AF flag, pages are initially made read-only to catch
writes.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Nicolas Pitre
4e0e52cbec arm64: mmu: be stricter about free page entries
Let's consider free entries as being completely zeroed. Future patches
for demand paging support will populate entries and still mark them as
"invalid" which should not be considered free. Current code always clear
entries to be freed so no issues there.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-09-11 20:18:51 -04:00
Martin Åberg
884a4e5a35 arch: Fix assert logic for installing shared interrupt
With this commit, it is now allowed to register any ISR and arg
combination for the same IRQ, except the case when the exact same
ISR-arg combination is already registered.

The previous assert logic had a restriction where the same ISR could not
be registered multiple times with different arguments.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2024-09-11 07:41:20 -04:00
Pisit Sawangvonganan
56b6ccb2f4 style: arch: comply with MISRA C:2012 Rule 15.6
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-09-11 07:40:35 -04:00
Yong Cong Sin
26d75ab796 arch: riscv: optionally stores a pointer to csf in struct arch_esf
The callee-saved-registers can be helpful to debug the state of
a core upon an exception, however, currently there's no way to
access that information in user-implemented
`k_sys_fatal_error_handler()`, even though the csf is already stored
in the stack.

This patch conditionally add a `csf` member in the `arch_esf` when
`CONFIG_EXTRA_EXCEPTION_INFO=y`*, which the `_isr_wrapper` would update
when a fatal error occurs before invoking `z_riscv_fatal_error_csf()`.

Functions such as `k_sys_fatal_error_handler()` would then be able
to access the callee-saved-registers at the time of exception via
`esf->csf`.

* For SoCs that select `RISCV_SOC_HAS_ISR_STACKING`, the
  `SOC_ISR_STACKING_ESF_DECLARE` has to include the `csf` member,
  otherwise the build would fail.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-10 11:43:40 +02:00
Daniel Leung
5ec60249ed x86: skip printing args when unwinding stack
On 32-bit x86, it was supposed to print the first argument to
the function during stack trace. However, it only works when
code optimizations are totally disabled (i.e. -O0). As such,
printing the args is not meaningful to aid with debugging.
So change it to simply print the function address, the same
as x86 64-bit.

Also, since unwind_stack() has exactly one caller, make it
ALWAYS_INLINE to skip a function call.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-09-09 18:41:04 -04:00
Yong Cong Sin
5365421fa1 arch: riscv: use string array instead of switch statement for cause
Get rid of the switch statement and use an string array
for the cause instead. This saves about ~600 bytes.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-09 15:23:43 +03:00
Yong Cong Sin
7844f5aebb arch: riscv: fatal: make cause_str reusable
Rename `cause_str` to `z_riscv_mcause_str` and make it non-static,
so that it can be used in user-implemented `k_sys_fatal_error_handler`.

Also, this function should return a constant string, so add `const`
to it.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-09 15:23:43 +03:00
Yong Cong Sin
951af0d457 arch: riscv: fatal: always print mcause & mtval
Relocate the logging of mcause & mtval from `_Fault` to
`z_riscv_fatal_error_csf` so that they are always printed
upon exception.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-09 15:23:43 +03:00
Anas Nashif
8c32a82e47 arch: arc: replace ARC_EARLY_SOC_INIT with PLATFORM_RESET_HOOK
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARC.

Replace soc_early_asm_init_percpu() with platform_reset()

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-09 10:07:33 +02:00
Anas Nashif
81cf87001c arch: arm: select PLATFORM_RESET_HOOK if is PLATFORM_SPECIFIC_INIT set
Temporary until usage of PLATFORM_SPECIFIC_INIT is removed in modules.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-09 10:07:33 +02:00
Anas Nashif
f519dd1411 arch: arm: replace PLATFORM_SPECIFIC_INIT with PLATFORM_RESET_HOOK
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.

Replace z_arm_platform_init() with platform_reset().

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-09 10:07:33 +02:00
Anas Nashif
e260d03686 init: introduce soc and board hooks
Introduce soc and board hooks to replace arch specific code
and replace usages of SYS_INIT for platform initialization.

include/zephyr/platform/hooks.h introduces the hooks to be implemented
by boards and SoCs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-09-09 10:07:33 +02:00
Yong Cong Sin
31ebb79c86 arch: multilevel_irq: fix interrupt bits check
The bits allocated for each aggregator level only need to be enough to
encode CONFIG_MAX_IRQ_PER_AGGREGATOR, instead of the combined number of
IRQs from all aggregators in that level.

Add additional check for L3 interrupts as well, if it is enabled.

Updated the assert in `z_get_sw_isr_table_idx()` to be more verbose.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-06 14:06:23 -05:00
Jakub Michalski
f568e2d3ca zefi: add bootargs support
Add bootargs support to zefi. This implements
get_bootargs() when both efi and bootargs are
selected in config.

Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-09-05 12:30:39 -05:00
Jakub Michalski
3b58d066e4 zefi: include autoconf.h
Zefi was only including include/zephyr but not the generated include
directory that contains autoconf.h. This commit fixes that.

Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-09-05 12:30:39 -05:00
Jakub Michalski
0cf726b8ef arch/x86: multiboot: add bootargs support
Add bootargs support for multiboot. This
implements get_bootargs() when multiboot and
bootargs are selected in config.

Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-09-05 12:30:39 -05:00
Mykyta Poturai
745c9543c6 xen: Make XEN_INTERFACE_VERSION configurable
Add Kconfig option to specify Xen interface version to use. This will
make it easier to switch between different versions of Xen.

Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
2024-09-04 12:52:16 +02:00
Magdalena Pastula
0237d375de arch: riscv: add an option for empty spurious interrupt handler
Add the possibility to disable fault handling in spurious
interrupt handler on RISCs and replacce it with an infinite loop.

Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
2024-09-02 12:35:57 -04:00
Yong Cong Sin
ed8dd0fa63 arch: riscv: stacktrace: undo the fp/sp alignment check in #76045
The change of alignment check in #76045 could be wrong and
isn't unnecessary to fix the stack traces output, undo it for
now.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-09-02 12:33:36 -04:00
Marcio Ribeiro
cb583995b8 arch: riscv: imply XIP config pushed to SoC level
'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig
files to allow riscv SoCs having XIP enabled (or not) at SoC level

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-31 06:47:52 -04:00
Daniel Leung
0962114f2b riscv: implements arch_thread_priv_stack_space_get
This implements arch_thread_priv_stack_space_get() so this can
be used to figure out how much privileged stack space is used.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-08-28 06:50:30 -04:00
Daniel Leung
bb313355f3 riscv: initialize privileged stack during thread init
This adds the bits to initialize the privileged stack when
a thread is transitioning to user mode. This prevents
information leaking if the stack is reused, and also aids
in calculating stack space usage during system calls.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-08-28 06:50:30 -04:00