This reverts commit 42036cdbca.
Architecture specific code should not do preemption checking before context
switch. This is already handled by the scheduler, so duplicating it would
be redundant and error prone. These checks used to be necessary, but the
scheduler has been rewritten since then and the checks were removed in
3a0cb2d35d (kernel: Remove legacy preemption checking, 2018-05-23).
The check this reverts was also incorrect, as it didn't take scheduler
locking nor meta-IRQs into account.
Fixes#80574
Signed-off-by: Kalle Kietäväinen <kalle.kietavainen@silabs.com>
Enable support for warm reboot for x86 arch as per the Reset Control
Register description.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
The exception fault handler function is named _Fault which is inconsistent
with all other arch-specific functions present in Zephyr. This patch
replaces the name with z_riscv_fault.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
The exception fault handler function is named _Fault which is inconsistent
with all other arch-specific functions present in Zephyr. This patch
replaces the name with z_nios2_fault.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
An existing comment references a function "irq_oflload()", which should be
written "irq_offload()".
This issue was detecte by the GitHub CI compliance check.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
The exception fault handler function is named _Fault which is inconsistent
with all other arch-specific functions present in Zephyr. This patch
replaces the name with z_mips_fault.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
The exception fault handler function is named _Fault which is inconsistent
with all other arch-specific functions present in Zephyr. This patch
replaces the name with z_arc_fault.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
ARM has deprecated usage of non-shareable device memory.
K_MEM_CACHE_NONE flag used by devices to map physical memory translates
to MT_DEVICE but no MATTR_SHARED attribute is set in such a request.
This results in mapping device memory that is non-shareable.
Depending on the memory interconnect of a SoC, mapping the device memory
as non-shareable can prevent access to the device. Such behavior has
been observed on the TI AM3358 SoC.
To comply with the ARM deprecation notice and prevent access issues to
device memory, all device memory is mapped as shareable.
Signed-off-by: Abe Kohandel <abe.kohandel@gmail.com>
This change initializes was_valid_access in the case that
CONFIG_X86_KPTI is selected. Previously, the variable was
causing an uninitialized variable warning that would be
escalated to an error when run with twister.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` had been deprecated since
#66877 for 2 releases, interrupt controller drivers should have been
updated to use the new `IRQ_PARENT_ENTRY_DEFINE()` macro. Remove it.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
`CONFIG_ARM64_ENABLE_FRAME_POINTER` had been deprecated since #72646
for 2 releases and served not functional effect, it's now time to
say goodbye.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
With our builds for Arm M7 we are selecting FPU_SHARING and
MPU_STACK_GUARD. For that setup, we have
ARM_MPU_REGION_MIN_ALIGN_AND_SIZE=64 and
MPU_STACK_GUARD_MIN_SIZE_FLOAT=128. So worst case scenario,
we are going to have stack that is 64-byte aligned and
128-byte guard at the bottom of the buffer.
Fixes: #83714
Signed-off-by: Maciej Kusio <rysiof@gmail.com>
The function prototype / extern declaration for
z_x86_kpti_is_access_ok() in x86_mmu.h was missing a semicolon.
Add it to avoid being surprised by compile errors in certain
circumstances.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
When RISCV_SOC_HAS_ISR_STACKING is used, it may
be needed to initialize custom hw stacked esf members.
Some initial values may need to be aligned with
hw stacking mechanism to avoid any side effects.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Fix `arch_timing_cycles_get()` to prevent overflow on 32bit cycles
rollover. Also make `arch_timing_counter_get()` to work 64bit when
`CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER` is set.
The issue was observable, for example when `tests/benchmarks/wait_queues`
or `tests/benchmarks/sched_queues` were executed on qemu for `mps2/an385`
and the benchmark has its iterations large enough as the default
BENCHMARK_NUM_ITERATIONS=1000.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
What is the change?
- Fixes#83660 allowing device to now enter suspend mode even if
CONFIG_DEBUG_THREAD_INFO is enabled.
Why is this needed?
- z_sys_post_kernel was cleared as part of #d778d5c
to "allow debuggers to display the correct thread state after
the first 3 instructions have run".
This is not required while resuming from suspend and
it prevents the device from entering suspend so,
move it out of resume path.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The RISC-V architecture-specific relocations need to check whether
each required relocation can fit into the modified instruction's
immediate. All immediates in RISC-V are encoded as two's complement.
The current truncation check has an off-by-one error for checking
the maximum negative distance, as two's complement encoding can
represent a negative value that is the maximum positive value plus
one, causing LLEXT to refuse loading valid code.
This commit adds an additional condition to the check that fixes
the aforementioned issue.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Define the generic _current directly and get rid of the generic
arch_current_get().
The SMP default implementation is now known as z_smp_current_get().
It is no longer inlined which saves significant binary size (about 10%
for some random test case I checked).
Introduce z_current_thread_set() and use it in place of
arch_current_thread_set() for updating the current thread pointer
given this is not necessarily an architecture specific operation.
The architecture specific optimization, when enabled, should only care
about its own things and not have to also update the generic
_current_cpu->current copy.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").
This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.
The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.
Hence this revert.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Previously, there were two separate Kconfig definitions
of ARM_MPU located at:
- arch/arm/core/mpu/Kconfig
- arch/arm64/core/cortex_r/Kconfig
This lead to incomplete default settings and unexpected
missing configurations.
This commit combines the two into a single unified definition
now located at arch/common/Kconfig to prevent this.
Signed-off-by: Samuel Chee <samche01@arm.com>
Xtensa cache line sizes aren't an obtuse area of pedantry like they
are in x86. Different cores already in Zephyr are already using
variant cache line sizes (64 and 128 bytes are both common).
And I tripped over this by using the wrong value because the kconfig
was being inherited (incorrectly) from a default somewhere.
Xtensa exposes the correct value in core-isa.h (well, unless the
toolchain/hal gets messed up). Add a check to make sure that our
platform kconfig gets it right.
Note that qemu/dc233c was already getting this wrong, leaving the
value at the kconfig default of zero. That was benign (qemu doesn't
provide any cache emulation for incoherent DMA), but needs to be
fixed.
Signed-off-by: Andy Ross <andyross@google.com>
Fix arch_timing_cycles_get() to prevent overflow on the clock rollover.
The issue is observable on tests/benchmarks/wait_queues and
tests/benchmarks/sched_queues with BENCHMARK_NUM_ITERATIONS is large
enough, e.g. default 1000.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
The return value of the system_off call is overwritten by the the call to
pm_s2ram_mark_check_and_clear. As arch_pm_s2ram_suspend needs to specify
why system_off failed, we need to make sure the rv of system_off is moved
to a safe register before calling pm_s2ram_mark_check_and_clear and moved
to r0 als rv of arch_pm_s2ram_suspend when the suspend call exits.
Signed-off-by: Hessel van der Molen <hvandermolen@dexels.com>
With dynamically linked / shared ELF objects the displacement
between file offsets and memory addresses can differ between
sections. Therefore we cannot use .text for all such relocations and
have to locate the respective section instead.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
To obtain a section header reference we don't need to calculate its
location in the ELF image, we already have a pointer to all section
headers, just use them.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently llext_link_plt() calculates offsets to relocation addresses
relative to the .text section and passes them to
arch_elf_relocate_global() and arch_elf_relocate_local(), where then
.text memory address is added to them. Instead it's more logical to
concentrate the entire calculation in the caller, which then also
removes the assumption, that all sections have the same VMA - LMA
offset from those functions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
With writable LLEXT but without pre-assigned section addresses
.bss section offset in its ELF header will not match .bss eventual
location as it's allocated on the heap. Use llext_loaded_sect_ptr()
to get a correct address in both cases.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The ARM Thumb-1 instruction set, used by ARMv6-M and ARMv8-M Baseline
cores, does not have a valid encoding for "immediate-to-register move
without affecting flags" instruction (i.e. `mov reg, imm`), and the only
valid variant of immediate-to-register move instruction for it is `movs`,
which affects the flags.
Since none of the register initialisation instructions used here are
flag-sensitive in their context, this commit changes `mov` to `movs`.
This fixes the compilation errors with Clang/LLVM, which is more picky
about the `mov` mnemonic usage and prints out an "invalid instruction"
error when `mov reg, imm` is specified in Thumb-1 mode.
Note that GNU assembler implicitly converts `mov reg, imm` to `movs reg,
imm` when assembling in Thumb-1 mode.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Moves the arch_swap() declaration out of kernel_arch_interface.h
and into the various architectures' kernel_arch_func.h. This
permits the arch_swap() to be inlined on ARM, but extern'd on
the other architectures that still implement arch_swap().
Inlining this function on ARM has shown at least a +5% performance
boost according to the thread_metric benchmark on the disco_l475_iot1
board.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
In some Cortex-M3 implementations SCB_VTOR bit[29] is called
the TBLBASE bit.
This enables setting VTOR to an SRAM address for qemu_cortex_m3
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Following the binding rename to "nxp,sysmpu", update the Kconfig
option to align with the binding name and to better reflect the
option's purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When not using CONFIG_XIP (CONFIG_XIP=n)
the FLASH_0 mpu region needs to be removed,
otherwise it will have the default base
address = 0, which means that MPU will try
to configure the region with address 0.
We don't want this as in some situations
address 0 can be a restricted memory region
such as ROM code.
Signed-off-by: Alexandru Lastur <alexandru.lastur@nxp.com>
This reverts commit 7c90f1bca1.
Xen initialization maps enlighten page to Zephyr memory and also
initializes Xen event channels. It is used for communication between
Xen domains and based on interrupt connected to domain virtual GIC.
Moving event channel initialization to arch_kernel_init() make it call
irq_enable() when GIC is not initialized. Since GIC is initialized
on PRE_KERNEL_1 stage, this lead to fatal error during boot.
Revert these changes to make xenvm operable again.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
The original idea of the syscall helpers is to workaround
an issue where the compiler could not correctly model register
usage with inline functions. It was supposed to be only used
when there are more then 3 arguments to syscalls. However,
during the original MMU code development, the helper got
expanded to cover "less then 2 arguments syscalls" as a way
for debugging syscall handling code and was never removed.
So fix that now by limiting the helper for syscalls with
more than 3 arguments.
Moreover, instead of using one helper with 6 arguments, now
we have separate implementations for both 4 and 5 arguments
syscall helpers. Now the compiler does not have to generate
code to always handle 6 arguments which saves a few code bytes
as there is no need to pass extra zeroes as arguments.
This has been verified to work with xt-clang RI-2022.10.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is currently selected by the arch, but some devices (in paticular
xtensa ones which have configurable interrupt setups) might not
actually be able to effect an irq_offload() from within an ISR even
though we have code for it.
Make this a default and not a select so that lower layers can override
the setting.
Signed-off-by: Andy Ross <andyross@google.com>
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.
To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.
`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Reset the the `gp` register to `_kernel->cpus[i].current` when
`CONFIG_USERSPACE` is enabled on exception to keep it sane.
Updated the testcase to test both `CONFIG_RISCV_GP` and
`CONFIG_RISCV_CURRENT_VIA_GP`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
In most implements, the msip base address is 0x2000000. But the address
is not fixed in all boards.
Signed-off-by: Yang Jialong <yangjialong@vcore.com>
On Arm Cortex R52, cache segregation policy controls the
number of L1 I/D cache ways that are allocated to Flash
and AXIM interface. Adding Kconfig options for configuring
it.
Writing to IMP_CSCTRL is only permitted before the caches
have been enabled, following a system reset.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This adds support for the single-vector trapping (SVT) model, defined by
SPARC-V8 Embedded (V8E) Architecture Specification. SVT is available in
most LEON processors.
With single-vector trapping enabled, all traps are vectored through a
single trap vector (TBR.A) rather than one 16-byte entry for each trap
type. This improves memory utilization because the full 4 KiB trap table
is not needed.
This implementation uses a two-level of lookup table to find the handler
for the trap type (0..255).
- Execution time is constant.
- Condition flags are preserved.
- The implementation footprint is 60 bytes .text and 284 bytes .rodata.
For comparison, a non-SVT table is always 4096 .text.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Enabling CONFIG_FPU and CONFIG_FPU_SHARING requires the
definition of `arch_float_disable` and `arch_float_enable`.
Signed-off-by: Matthias Alleman <matthias.alleman@basalte.be>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Implement `arch_curr_thread()` & `arch_set_curr_thread()`
with the global pointer (GP) register.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Add the following arch-specific APIs:
- arch_curr_thread()
- arch_set_curr_thread()
which allow SMP architectures to implement a faster "get current
thread pointer" than the default provided by the kernel. The 'set'
function is required for the 'get' to work, more on that later.
When `CONFIG_ARCH_HAS_CUSTOM_CURRENT_IMPL` is selected, calls to
`_current` & `k_sched_current_thread_query()` will be redirected to
`arch_curr_thread()`, which ideally should translate into a single
instruction read, avoiding the current
"lock > read CPU > read current thread > unlock" path in SMP
architectures and thus greatly improves the read performance.
However, since the kernel relies on a copy of the "current thread"s on
every CPU for certain operations (i.e. to compare the priority of the
currently scheduled thread on another CPU to determine if IPI should be
sent), we can't eliminate the copy of "current thread" (`current`) from
the `struct _cpu` and therefore the kernel now has to invoke
`arch_set_curr_thread()` in addition to what it has been doing. This
means that it will take slightly longer (most likely one instruction
write) to change the current thread pointer on the current
CPU.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
We hit some unaligned access faults running our internal tests.
Not every 32-bit instruction is 32-bit aligned; some are 16-bit aligned.
Make all reads and writes potentially unaligned to be on the safe side.
Signed-off-by: Ilya Tagunov <Ilya.Tagunov@synopsys.com>
Previously PMP was avaible only with Multithreading, since it's now
available without MT - add extra checks to prevent user/kernel mode
reconfiguration.
Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Without multithreading only two stacks present: ISR and main.
As any stack they also could overflow, so it make sense to add stack
guard for them also.
Remove stack guard dependency on multithreading and mark
`Z_RISCV_STACK_GUARD_SIZE` bytes at the beginning of stack as read-only
region with PMP entry.
Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
