Provide a network driver wrapped around the KSDK ENET and PHY
drivers.
The driver performs one shot PHY setup. There is no support for PHY
disconnect, reconnect or configuration change. The PHY setup,
implement via KSDK contains polled code that can block the
initialization thread for a few seconds.
There is no statistics collection for either normal operation or error
behaviour.
Origin: Original
Change-Id: Ia0f2e89a61348ed949976070353e823c178fcb24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Build breaks when enabling CONFIG_NEWLIB_LIBC because it has its own
sched.h file.
This is a bad symptom of a greater issue: the build system passes many
'-I<path>' options to the compiler, and that allows including header
files by simply specifying their names (when located somewhere else than
<zephyr>/include/) and can cause clashes when several files in different
locations have the same name, like in this case.
Fixes ZEP-1062.
Change-Id: I81d1d69ee6669a609cd0c420b1b8f870d17dcb67
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Builtin might not be available for ARMv6 (Cortex-M0/M0+) depending on
the toolchain used (not available by Zephyr's SDK GCC), so move the
atomic operations selection to the Cortex-M family Kconfig file.
Change-Id: I20a5a0c5fdd2bcff2d304139f5a7e8502fdb1cb3
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
When adding a thread to the ready queue, it is often known at that time
if the thread added will be the next one to run or not. So, instead of
simply updating the ready queues and the bitmask, also cache what that
thread is, so that when the scheduler is invoked, it can simply fetch it
from there. This is only done if there is a thread in the cache, since
the way the cache is updated is by comparing the priorities of the
thread being added and the cached thread.
When a thread is removed from the ready queue, if it is currently the
cached thread, it is also removed from the cache. The cache is not
updated at this time, since this would be a preemptive fetching that
could be overriden before the newly cached thread would even be
scheduled in.
Finally, when a thread is scheduled in, it now becomes the cached thread
since the fact that it is running means that by definition it was the
next one to run.
Doing this can speed up considerably some context switch times,
especially when a thread is preempted by an interrupt and the same
thread is scheduled when the interrupt exits.
Change-Id: I6dc8391cfca566699bb9b217eafe6bc6a063c8bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The unified kernel calls a function (_get_next_ready_thread) to fetch
the next thread to run: it thus must save caller-saved registers that
are expected to hold a value before calling such function.
The callee-saved registers are available after saving them in the
outgoing thread's stack, so use some of those instead to reduce the
number of registers to save before calling _get_next_ready_thread. Also,
save caller-saved registers in callee-saved registers instead of on the
stack to reduce memory accesses.
This issue did not show up previously, probably because
_get_next_ready_thread did not use the regsiters that had to be saved,
but an upcoming optimization to that function stomps on them.
Change-Id: I27dcededace846e623c3870d907f0d4c464173bf
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Not used anymore as the support for dynamic IRQs was removed by
commit 844e212.
Change-Id: I624bbd777b2dbcbf905cedc61e63cef21e8a0bce
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Move SRAM_BASE_ADDRESS and FLASH_BASE_ADDRESS to Kconfig.soc since
it will most likely be the same values for all STM32 socs.
Change-Id: I682dc441e34155a19a4f90757707008ef299e9d4
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Add _arch_irq_is_enabled external interrupt API to find out
if an IRQ is enabled.
Change-id: I8ccbaa6d4640c1ab8369d2d35c01a2cfbb02f6cd
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Do not clear pending IRQ when enabling an IRQ on ARM
architectures. Peripherals and S/W ISRs may be required to
be deferred until they are enabled later and the pended
IRQ should be retained for the ISR to be vectored to when
enabled.
Change-id: I808183018d8a2cc58390a1de3b4797b2bb7c6ec9
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
The '_timeout' structure is needed by dummy threads so that they can
handle timeouts.
Change-Id: Iefabd6ad93c8e176e95ce4262f5f3544dc90b7d5
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Quoting the product specification this device contains an "ARM
Cortex-M4 processor with floating-point unit" or, as this would
more normally be expressed an ARM Cortex-M4F.
Update Kconfig accordingly.
Change-Id: I5bd6f17724d0d4aa9aaab9961f12d4e8502c38a5
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Provide a random driver wrapped around the KSDK RNGA driver.
Origin: Original
Change-Id: I43feeb37d8d5173c7b95af8e80434fb7dc77a83e
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The ARM architecture port is fitted with support for the unified kernel,
namely:
- the interrupt/exception exit code now pends PendSV if the current
thread is not a coop thread and if the scheduler is not locked
- fiber_abort is replaced by k_thread_abort(), which takes a thread ID
as a parameter (i.e. does not only operate on the current thread)
- the _nanokernel.flags cache of _current.flags is not used anymore
(could be a source of bugs) and is not needed in the scheduling algo
- there is no 'task' field in the _nanokernel anymore: PendSV not calls
_get_next_ready_thread instead
- the _nanokernel.fiber field is replaced by a more sophisticated
ready_q, based on the microkernel's priority-bitmap-based one
- thread initialization initializes new fields in the tcs, and does not
initialize obsolete ones
- nano_private includes nano_internal.h from the unified directory
- The FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
priority drives the behaviour
- the tcs uses a dlist for queuing in both ready and wait queues instead
of a custom singly-linked list
- other new fields in the tcs include a schedule-lock count, a
back-pointer to init data (when the task is static) and a pointer to
swap data, needed when a thread pending on _Swap() must be passed more
then just one value (e.g. k_stack_pop() needs an error code and data)
- the 'fiber' and 'task' fields of _nanokernel are replaced with an O(1)
ready queue (taken from the microkernel)
- fiberRtnValueSet() is aliased to _set_thread_return_value since it
also operates on preempt threads now
- _set_thread_return_value_with_data() sets the swap_data field in
addition to a return value from _Swap()
- convenience aliases are created for shorter names:
- _current is defined as _nanokernel.current
- _ready_q is defined as _nanokernel.ready_q
- _Swap() sets the threads's return code to -EAGAIN before swapping out
to prevent timeouts to have to set it (solves hard issues in some
kernel objects).
Change-Id: I36c03c362bc2908dae064ec67e6b8469fc573983
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
They use data that is unavailable to the unified kernel, and are not
used anymore really. For now, only compile them when CONFIG_GDB_INFO=y,
and never enable CONFIG_GDB_INFO when building the unified kernel.
These files should go away when the unified kernel is made the only
kernel type.
Change-Id: I0a2a917dd453ecaae729125008756e0f676df16d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Watchdog timer is enabled after the board reset. It is not used by Zephyr OS,
and having it enabled causes system resets during CPU-intensive operations.
Change-Id: If5583dbd2d2fb2206274467c523d6b5d147f1fbe
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Define symbolic constants for watchdog timer registers.
Provides the necessary interface to configure or disable
the watchdog timer.
Change-Id: I80002a843361569fdd78b725fc3f68e65195d02e
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
There is a total of 39 IRQs defined at nrf52/soc_irq.h.
Change-Id: Id478fb15a07cfdecaa6cc136730d20017b8752c5
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Zephyr uses the last priority level for the PendSV exception, but
sharing prio can still be useful on systems with a reduced set of
priorities, like Cortex-M0/M0+.
Change-Id: I767527419dcd8f67c2b406756b9208afd3b96de0
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Add a shim layer around the ksdk I2C driver to adapt it to the Zephyr
I2C interface. Currently only supports master mode.
Jira: ZEP-717
Change-Id: I704b8c38e22e456bb9fa4325682b2a354a27a7ba
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Since nrf.h abstracts the differences between the nRF51 and nRF52
architectures and chooses the right headers to include, it is
safer to use that instead of directly including the soc-specific
headers.
Jira: ZEP-702
Change-Id: I0e1758ede48f3422a41d226b0eab008e4ba2c77c
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The ksdk provides a clock driver, fsl_clock.c, for the K64F and an
example usage of that driver, clock_config.c, for the Freedom board.
See ext/hal/ksdk/devices/MK64F12/
Leverage parts of clock_config.c to configure the clocks (specifically,
the sequence in BOARD_BootClockRUN()), but use the new Kconfig options
to set up the configuration structure. This will allow support for new
boards that may have a different external oscillator frequency or type.
Jira: ZEP-715
Change-Id: I3f0c75e6236f57600cd8b7f06f4482b13026fc10
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Many Kinetis SoCs contain an Oscillator (OSC) module and a Multipurpose
Clock Generator (MCG) module to configure clocks. Adding options to
configure these modules for PLL operation with different external
oscillator frequencies, which can vary across boards. More options may
be added later to support other clocking modes such as FLL.
Jira: ZEP-715
Change-Id: Ia121cc5b464d7e681883507bd756d331a8abd6ef
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.
We aren't. Zephyr is an ELF platform. None of our toolchains do
this. Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard. Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.
(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)
Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Add a Kconfig option to select between the Hard and Soft Float ABIs. We
also default to the Hard Float ABI as this is what older SDK versions
supported.
JIRA: ZEP-555
Change-Id: I2180c98cd7556ab49f5ca9b46b31add2c11bd07b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The K64F SoC initialization previously used macros and structs
custom-defined in Zephyr in order to access peripheral registers.
Refactored it to use CMSIS-style register accesses from the ksdk
instead.
Change-Id: I80975c62de07ec95cf830e99cd5b0abb9623acd0
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Utilize the gcc -print-libgcc-file-name to determine the path to
libgcc.a. Using this also resolve issues if we are building with
floating point and the various ABIs to pickup the right lib.
We can also simply a few Makefiles and remove the need to export
_CROSS_COMPILE_arm_isa.
Change-Id: I293394c921c18fa4984173ba51825d6f9a333697
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.
At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.
Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The comments for INT_ACTIVE and EXC_ACTIVE now refer to
"executing context ..." for all architectures.
Change-Id: Ib868958639a3b30e1814fcaa4d1f0651d3b2561e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds Kconfig options CPU_HAS_FPU, FLOAT and FP_SHARING for the arm
architecture.
NOTE: All SOCs in the MK64F12 family have an FPU so that makes it a
convenient location to enable the hidden CPU_HAS_FPU option.
Change-Id: I71771d24f20f52079314bb8db9bf8a0aa827ab41
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Apply the correct compiler options when building for a Cortex-M4
processor that has floating point enabled. Using 'softfp' allows
floating point to be used with existing libraries supplied by the
Zephyr SDK. The 'hard' option would require new libraries to be
shipped with the SDK.
Change-Id: I141c20f54c2241134510888688637930c7b560a2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Enable floating point in the Cortex-M4 processor.
Change-Id: Ibadae12b9197d6486fd5c6a3d4e177fa9e1c71bc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Saves and loads the non-volatile FP registers (s16-s31) when switching
between threads.
Change-Id: Ib3190452d9a70d722032ac83176eb4fbb92aca3d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds the preemptive floating point registers to the ARM's thread
control structure.
Change-Id: I65fbee6303091ce0658bbc442c4707d306b68e92
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Updates the exception stack frame structure to include floating point
registers.
Change-Id: I0fef784cf4d91dda245180abd75bfd9221825fba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
at91sam3 supposed to go to Sleep mode and stop the CPU clock
(HCLK). It leads to JTAG problems. In order to be able to use
JTAG, we need to keep CPU clock on. This is achieved by
switching to Wait mode and keeping external main clock.
Since Wait mode switches off automatically Fast RC Oscillator,
but keeps external clock untouched.
Change-Id: Ife37a7691c3cbdf434e560725a71d419adafe054
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Add hidden configuration HAS_KSDK for SoCs to select if they have
support in the ksdk.
Change-Id: Ia4cd11901bc26d21a3bdfad6236d66656bb292cb
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
There was a reference to SOC_FAMILY_NRF5 which was not use by anyone
else and it seemes like it was a typo, where the right reference was
to symbol SOC_NRF5. However, the right fix is to move both sites to
use SOC_FAMILY_NRF5 *and* fix the SOC_SERIES to be only nrf52,
otherwise it causes path duplication and the build fails.
This was also causing documentation warnings that are thus killed.
Change-Id: I92e74a6158f02df43e6e857df8f1e67bcfdd9551
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
The ReST parser dislikes enumerations with no empty lines in
between. Whatever.
Change-Id: I480c08fe5b69f0d0f3ebfacdc64fc9e3ec94da21
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
The KSDK device header files require a preprocessor macro that defines
the part number string (e.g., MK64FN1M0VMD12). Create a hidden Kconfig
option to hold the part number string, and hidden Kconfig options that
the board Kconfig will use to select the specific part number.
Change-Id: I612e785026261e425b47b5b7fae0c65b4f94b30b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
