We already determine whether the target is PMSAv8 or (PMSAv6/PMSAv7)
using the selected architecture profile (ARMv6-M/ARMv7-M or ARMv8-M
Baseline/Mainline) and define a symbol accordingly. Make use of that
symbol everywhere instead of repeating CPU checks all over arch code.
While at it, drop the allowlist which generated a build error when the
MPU was enabled on an "unknown" CPU. The header is only included from
SoC-specific code which knows whether an MPU exists or not, or generic
code gated behind CONFIG_ARM_MPU, which guarantees that the MPU exists
as CONFIG_ARM_MPU depends on CONFIG_CPU_HAS_ARM_MPU.
Note: this tangentially fixes a bug that misclassified ARMv8-R targets
as using the PMSAv6/PMSAv7 MPU. This bug did not seem to have any
adverse effect though...
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The loop loaded s[counter] before checking counter == maxsize, so it
read s[maxsize] when the first maxsize bytes were all non-NUL and
dereferenced s[0] when maxsize == 0, violating the strnlen()
semantics required by arch_user_string_nlen(). The over-read byte
cannot change the returned length, but if it is not accessible the
exception fixup reports a spurious error and callers reject valid
input with EFAULT.
Check the limit before the load instead.
Fixeszephyrproject-rtos/zephyr#113722
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
This reverts commit c18885e95f:
the issue that this commit worked around was fixed in the
previous commit by preserving the original stack alignment.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
Preserve the alignment indication and rebuild the hardware frame with its
padding word to ensure the stack is always 8-byte aligned when returning
from exception: this is required on Armv8-M.
When an exception is taken with a stack pointer that is not 8-byte
aligned, Armv8-M, and Armv7-M when configured, adds a 4-byte padding word
to align the exception frame. Bit 9 of xPSR records the presence of this
padding.
However, arm_m_switch_to_cpu() does not restore the padding word when
rebuilding the hardware frame. The existing workaround clears the xPSR
alignment bit, which is sufficient on Armv7-M but is invalid on Armv8-M.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
Declare dummy as a read-write output operand, to reflect how it
is used in the assembly block.
The inline assembly overwrites dummy before reading it, but declares the
operand as input-only. The compiler may therefore assume that the backing
register is unchanged and reuse it for another live value, even though the
assembly clobbers it.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
Add a Cortex-M perf backend that samples interrupted context from the
SysTick exception frame.
Install a SysTick wrapper when stack-sampling perf is enabled and
capture the interrupted stack pointer, EXC_RETURN, and r7 on exception
entry. Validate the complete hardware-stacked frame, including optional
alignment padding and extended FP state, against the Thread-mode or
Handler-mode stack before unwinding with arch_stack_walk().
The Arm stack walker uses EHABI unwind tables, so the backend does not
require CONFIG_FRAME_POINTER. Preserve r7 because EHABI unwind recipes
may use it to recover VSP even when frame pointers are not enabled
globally.
Return -EAGAIN when the interrupted context is invalid or unavailable
so the perf core discards that sample without reporting buffer
exhaustion.
Limit the backend to uniprocessor configurations because its captured
sample state is global and remote SMP sampling does not enter the
SysTick wrapper.
Disable the backend for Non-secure Trusted Execution images. A
Non-secure SysTick can be taken while the core executes Secure code,
but Non-secure firmware cannot access the Secure exception frame.
The stack pointer read by the wrapper instead refers to the suspended
Non-secure context, so it cannot be unwound as the interrupted frame.
Sampling across Security states is unsupported.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Cortex-M exception frames can be stacked on MSP when execution is
interrupted in handler mode. The Arm EHABI stack walker currently seeds
VSP from the saved PSP unconditionally, which only works for frames
stacked on PSP.
Select the exception frame stack pointer from EXC_RETURN.SPSEL so
MSP-backed frames seed the unwinder from extra_info.msp, while preserving
the existing PSP path. This also allows perf sampling backends to unwind
handler-mode call chains captured on MSP.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Otherwise, "warning: implicit declaration of function 'dump_fault'" is
generated, which may be promoted to an error when also using
CONFIG_COMPILER_WARNINGS_AS_ERRORS=y.
Some variables may be unused when the dump_fault isn't called, so mark them
as unused to avoid warnings.
Signed-off-by: Phil Hindman <phindman@xes-inc.com>
Commit 2222fa1426 removed all callers of
the function arm_core_mpu_mem_partition_config_update()... but not the
function itself, which became dead code lingering in tree since then...
Get rid of this function - it has served no purpose for long enough.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Rename pm_s2ram.S to pm_s2ram_asm.S and update the
Cortex-M source list to reference the new filename.
This avoids generating colliding object paths for the
C and assembly suspend-to-RAM sources when both are
built together.
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Evan Chen <bugena123@gmail.com>
Code using this header is only built when CONFIG_ARM_MPU=y so it isn't
necessary to gate the header's declarations behind that option.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
`arm_core_mpu_dev.h` is the header describing the API that must be
implemented by drivers compatible with the core. Some functions were
were however accessed using an extern declaration inside the ARM MPU
Core module instead of a declaration in the API header.
Move the offending functions to the API header, making the extern
declaration unnecessary. While at it, also make `z_arm_mpu_init()`
part of the header because it is required, even if not consumed by
the ARM MPU Core module itself.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
XN on device-type regions only protects mapped regions; unmapped holes
in the MPU map remain reachable through the PRIVDEFENA background map,
both by Cortex-M7 speculative instruction fetches (Cortex-M7 TRM) and
by PLD linefills to faulting addresses (erratum 1013783, SDEN-1068427,
all M7 revisions).
Add opt-in CONFIG_ARM_MPU_CM7_UNMAPPED_REGION to program region 0 as a
4GB Strongly-ordered, no-access, Execute-Never catch-all, as
recommended by the erratum workaround; static regions start from
region 1 and take precedence. Opt-in because the catch-all defeats the
PRIVDEFENA background map: the static MPU region table must explicitly
cover all memory the firmware uses.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" arch/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add support for stacktrace of threads. The shell command
"kernel unwind <thread_ptr>" now works.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Co-authored-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Mapping large memory regions at the soc level will consume too
many l2 entries, adding l1 section mapping functionality to
reduce excessive use of l2 entries.
Signed-off-by: CHEN Xing <xing.chen@microchip.com>
arm_cpu_boot_params stack pointer fields used pointer arithmetic on
two-dimensional K_KERNEL_STACK_ARRAY_DECLARE arrays before casting to
char *, producing invalid initialized pointer values.
Use K_KERNEL_STACK_BUFFER() on the CPU 0 stack elements instead,
matching the runtime initialization in arch_cpu_start().
Fixes#113125
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
z_main_thread is only needed if multithreading is enabled, so move its
definition inside a multithreading check.
Signed-off-by: Josh DeWitt <josh.dewitt@garmin.com>
Commit f5a1585426 removed the extra
pointers for the IAR toolchain tls pointer setup. Update the size
returned from arch_tls_stack_setup to keep in sync with the tls pointer.
Signed-off-by: Josh DeWitt <josh.dewitt@garmin.com>
The architecture idle paths call sys_trace_idle() and
sys_trace_idle_exit() to notify subscribers when the CPU enters and
leaves the idle state. These calls were guarded by CONFIG_TRACING,
which tied idle-time accounting to the tracing subsystem even though
no tracing backend is required to service the hooks.
Introduce a hidden Kconfig symbol, SYS_IDLE_HOOKS, that any subsystem
needing these notifications can select, and have TRACING select it.
Switch the idle-path guards in every architecture and SoC that emits
the hooks from CONFIG_TRACING to CONFIG_SYS_IDLE_HOOKS. Because
TRACING selects the new symbol, existing tracing behaviour is
unchanged; the change only lets non-tracing consumers receive the
hooks.
This is a prerequisite for building the CPU load module without the
tracing subsystem.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Cortex-M arch cache backend exposed sys_cache_data_invd_all()
through CMSIS SCB_InvalidateDCache(). That routine invalidates the whole
D-cache by set/way, which unconditionally discards every dirty line,
including cache lines holding the current call stack and other runtime
state. Doing this while Zephyr is running can therefore drop the
caller's own return address and stack frame, corrupting execution and
hanging the cache API test on i.MX RT Cortex-M7 platforms. A prior
sys_cache_data_flush_all() does not help, because the stack is dirtied
again after the flush and during the invalidate itself.
Report the operation as unsupported instead. The cache API permits
-ENOTSUP for unsupported operations, and the whole-cache clean and
clean-invalidate paths remain available for callers that need safe
maintenance.
Reproduced on mimxrt1064_evk/mimxrt1064 with tests/arch/common/cache
(J-Link, COM42): with the original implementation the test flushed
successfully and then hung inside sys_cache_data_invd_all() at
"START - test_data_cache_api"; with this change the operation returns
-ENOTSUP and the suite reports PROJECT EXECUTION SUCCESSFUL. Also built
the same test for mimxrt1170_evk/mimxrt1176/cm7.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The Cortex-A/R interrupt wrapper enables IRQs to support nested interrupt
handling while running the registered ISR.
Move cpsie i after the spurious IRQ check so only valid ISR calls run
with IRQs enabled, and add cpsid i after the ISR returns. This prevents
EOI and z_arm_int_exit() from running with IRQs enabled.
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
When Secure firmware handles a fault with a recovered Non-Secure
exception frame, keep that context through fault classification.
Use it when reporting SecureFaults so the dump makes clear that the
fault originated in Non-Secure state and escalated into Secure state.
Also include guidance for the missing or disabled Non-Secure fault
handler case, where this escalation is commonly seen.
Handle the unexpected case where an exception frame cannot be recovered
without relying on __ASSERT(). Report the failure through the fault log
and terminate through z_arm_fatal_error(), so the path remains fatal
even when assertions are disabled.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The fault assembly wrapper saves r4-r11 after exception entry. When
EXC_RETURN says callee stacking was skipped, the processor has already
saved the interrupted Secure r4-r11 in the Secure additional context
block, so the wrapper's live r4-r11 are not the interrupted values.
Keep a pointer to the skipped Secure additional context and use it to
populate extra_info.callee when available, so fault dumps and other ESF
consumers report the interrupted Secure context.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Secure exception entry can place an integrity signature and additional
Secure context at the top of the stack before the basic exception frame.
Detect that signature when resolving the ESF and skip the additional
context before casting the stack pointer to struct arch_esf.
When EXC_RETURN says callee stacking was skipped, treat a missing
integrity signature as an invalid frame instead of silently using the
original stack pointer as the ESF. This avoids reporting misleading
fault state when the Secure stack shape is inconsistent or corrupt.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Fix a compilation error when CONFIG_EXTRA_EXCEPTION_INFO is enabled
on platforms that do not define EXC_RETURN_STACK_FRAME_TYPE_Msk
(which is only defined for Cortex-M).
For Cortex-A/R devices we just default to the same code path as before
bce6f0de63
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Check the exc_return flags to determine if the FPU registers were actually
pushed onto the stack by the exception handler and only dump them if they
are used. Otherwise the stack locations for the FPU registers are invalid
and we're just dumping garbage.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Add CONFIG_ARM_MPU_SKIP_ARCH_INIT for platforms where early boot code
(for example a TCM-resident stub) enables the MPU before z_arm_mpu_init()
runs. On Versal RPU split TCM/OCM images the kernel is linked in OCM while
reset code runs from TCM; z_arm_mpu_init() must not disable and reprogram
the MPU while the CPU is executing from an OCM-only region map.
When SCTLR.M is already set, z_arm_mpu_init() records the SoC static MPU
region count in static_regions_num and returns without touching the live
region table. That preserves the boot-time map (TCM, peripherals, OCM)
and keeps vector fetches at 0x0 executable after relocation.
SoCs that need this behavior select CONFIG_ARM_MPU_SKIP_ARCH_INIT from
their Kconfig; no Versal-specific logic is added under arch/.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Implement CONFIG_INIT_STACKS for the main stack when
CONFIG_MULTITHREADING is disabled. This keeps the config behavior
consistent between the main stack and the interrupt stack which is
memset in reset.S.
Signed-off-by: Josh DeWitt <josh.dewitt@garmin.com>
The ARM zImage header (header.S) ends with three words that follow
the Linux self-decompressor convention:
.long 0x016f2818 // Magic number
.long __rom_region_start // start address of zImage
.long __end // end address of zImage
A standard ARM zImage consumer (e.g. U-Boot bootz, or the Xen arm32
kernel loader) reads the third word and computes the on-disk file
size of the zImage as (__end - __rom_region_start). Linux establishes
the same invariant in arch/arm/boot/compressed/head.S, where the
analogous field is encoded as "_edata - start", i.e. the LMA of the
last byte of the image relative to its load address.
The current zimage_header.ld emits __end with:
KEEP(*(.image_header))
KEEP(*(.".image_header.*"))
__end = .;
zimage_header.ld is plugged into the linker script via the ROM_START
hook (see arch/arm/core/CMakeLists.txt) and runs immediately after
the 48-byte .image_header section is placed. At that point '.' is
still just past the header, so __end ends up only 0x30 bytes past
__rom_region_start regardless of how large the actual image is.
Every zImage built with CONFIG_ARM_ZIMAGE_HEADER=y therefore
advertises a size of 48 bytes in its header.
For Zephyr standalone this is invisible: the FVP / debugger loads
the whole file unconditionally and never consults the header. It
breaks any consumer that honours the header, though. On a Cortex-R52
FVP under Xen dom0less, the guest fails to boot:
(XEN) Loading zImage from 11000000 to 30000000-30000030
(XEN) CPU0: Unexpected Trap: Undefined Instruction
Xen copied only the 48 header bytes into the DomU and the guest
branched into uninitialised memory.
Fix it by computing __end the way Linux's head.S computes _edata:
take the LMA of the very last output section. Zephyr already exposes
that anchor as .last_section, and uses
LOADADDR(.last_section) + SIZEOF(.last_section)
elsewhere for the same purpose (e.g. _flash_used in
include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld and the
equivalent cortex_m / arm64 / riscv linker scripts). The expression
is resolved lazily by the linker at final link time, so referring
to it from a ROM_START fragment that runs before .last_section is
emitted is safe.
After this change, a build of samples/hello_world for
fvp_baser_aemv8r/fvp_aemv8r_aarch32 with -DCONFIG_ARM_ZIMAGE_HEADER=y
produces a 27268-byte zephyr.bin whose header reads:
magic = 0x016f2818
start = 0x30000000
end = 0x30006a84 (end - start == file size)
`file(1)` now identifies it as "Linux kernel ARM boot executable
zImage", U-Boot bootz accepts it without complaint, and the same
binary boots cleanly as a Xen R52 dom0less DomU using Xen's standard
zImage loader path (no special payload-only handling required).
Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Signed-off-by: Satya Sri <satyasri.katru@amd.com>
Fix the MCR instruction in switch.S to use the 'p15' coprocessor prefix
required by ARMv7-A toolchains.
Signed-off-by: Chidvilas Yerramsetti <cyerrams@qti.qualcomm.com>
Use <> operator to include a Zephyr header file instead of "" that
is intended to local header files, not header files relative to
specifically defined search paths.
This change was made running the sed shell command below:
$ sed -i -E 's/#include "zephyr\/([^"]+)\.h"/#include <zephyr\/\1.h>/g' \
`grep -rsl "#include \"zephyr/" arch/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The arm_core_mpu_enable() and arm_core_mpu_disable() functions were
defined in the ARM MPU driver but never declared in a header.
As a result, callers had to provide their own local `extern`
declarations to use them.
Add documented prototypes for both functions to
include/zephyr/arch/arm/mpu/arm_mpu.h and drop the redundant `extern`
declarations in arm_core_mpu.c and the userspace memory protection
test.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
CONFIG_LINKER_USE_PINNED_SECTION is the second half of the selective
kernel-pinning model removed in issue #108773. With the kernel image
now always resident at boot (previous commit), the __pinned_*
attribute family is a no-op: every page they would have segregated is
already pinned by z_mem_manage_init()'s whole-image loop, so the
tagging contract neither adds safety nor remains maintainable.
Drop it.
Mechanical removals:
* All ~219 in-tree uses of __pinned_text, __pinned_rodata,
__pinned_data, __pinned_bss, __pinned_noinit, and __pinned_func
across arch/x86, drivers/interrupt_controller, drivers/timer,
arch/common, kernel, lib/libc, subsys/portability/posix, tests, and
the syscall code generator (scripts/build/gen_syscalls.py).
* The assembly aliases PINNED_TEXT/RODATA/DATA/BSS/NOINIT used in
arch/x86/core/ia32/*.S and drivers/interrupt_controller/
intc_loapic_spurious.S become plain TEXT/RODATA/DATA/BSS/NOINIT.
* K_KERNEL_PINNED_STACK_DEFINE, K_KERNEL_PINNED_STACK_ARRAY_DEFINE,
K_KERNEL_PINNED_STACK_ARRAY_DECLARE, K_THREAD_PINNED_STACK_DEFINE,
and K_THREAD_PINNED_STACK_ARRAY_DEFINE are removed. The few
in-tree callers (kernel/init.c, arch/arm/core/cortex_a_r/smp.c,
arch/arm64/core/fatal.c, arch/rx/core/prep_c.c,
arch/x86/core/prep_c.c, kernel/include/kernel_internal.h,
tests/bluetooth/hci_uart_async) move to the corresponding
non-pinned macros.
Machinery removals:
* Kconfig.zephyr drops CONFIG_LINKER_USE_PINNED_SECTION.
qemu_x86_tiny and qemu_x86_atom_virt drop their =y overrides.
* include/zephyr/linker/section_tags.h drops the __pinned_* macro
definitions (both arms). __isr collapses to an empty macro since
its only purpose was to alias __pinned_func.
* include/zephyr/linker/sections.h drops PINNED_TEXT_SECTION_NAME,
PINNED_BSS_SECTION_NAME, etc. and the bare PINNED_TEXT/RODATA/etc.
forwarders, plus the _APP_SMEM_PINNED_SECTION_NAME constant.
* include/zephyr/linker/linker-defs.h drops the lnkr_pinned_*
externs, the _app_smem_pinned_* externs, and the lnkr_is_pinned()
/ lnkr_is_region_pinned() inline helpers.
* include/zephyr/linker/utils.h drops the lnkr_pinned_rodata branch
in linker_is_in_rodata().
* include/zephyr/linker/app_smem_pinned{,_aligned,_unaligned}.ld
are deleted; cmake/linker/ld/target_configure.cmake stops
configuring them.
* boards/qemu/x86/qemu_x86_tiny.ld and
include/zephyr/arch/x86/ia32/linker.ld drop their pinned-section
blocks and the now-redundant #ifndef CONFIG_LINKER_USE_PINNED_SECTION
conditionals throughout the body. The
LIB_KERNEL_IN_SECT / LIB_ARCH_X86_IN_SECT / LIB_ZEPHYR_IN_SECT /
LIB_C_IN_SECT / LIB_DRIVERS_IN_SECT / LIB_SUBSYS_LOGGING_IN_SECT /
LIB_ZEPHYR_OBJECT_FILE_IN_SECT / ZEPHYR_KERNEL_FUNCS_IN_SECT macros
in qemu_x86_tiny.ld are deleted; they existed only to feed the
pinned text/rodata/data/bss/noinit sections.
* kernel/mmu.c drops the mark_linker_section_pinned(lnkr_pinned_start,
...) call. The mark_linker_section_pinned() helper survives but is
now gated only on CONFIG_LINKER_USE_BOOT_SECTION.
* arch/common/init.c and include/zephyr/arch/common/init.h drop
arch_bss_zero_pinned(); arch/x86/core/ia32/crt0.S drops the call
to it.
* arch/x86/core/userspace.c drops the eager k_mem_page_in() of the
thread's privileged stack on user-mode entry. With the kernel
image fully resident the stack is already mapped.
* arch/x86/gen_mmu.py drops map_region("lnkr_pinned") and the
set_region_perms() calls for lnkr_pinned_text / lnkr_pinned_rodata.
* CMakeLists.txt drops the LINKER_USE_PINNED_SECTION block that
generated APP_SMEM_PINNED_* variables and the
pinned_partitions target property feeding gen_app_partitions.py.
cmake/modules/extensions.cmake removes the PINNED_RODATA /
PINNED_RAM_SECTIONS / PINNED_DATA_SECTIONS zephyr_linker_sources()
location keywords and their snippet files.
scripts/build/gen_app_partitions.py drops --pinoutput /
--pinpartitions arguments and the pinned-output branch.
subsys/testsuite/coverage/CMakeLists.txt drops its
CONFIG_DEMAND_PAGING-conditional fork.
* scripts/build/gen_kobject_list.py drops the
app_smem_pinned_start / _end fallback for kobject placement
validation.
* tests/arch/x86/pagetables and tests/kernel/mem_protect/userspace
drop their lnkr_pinned_text / lnkr_pinned_rodata branches.
* include/zephyr/arch/x86/ia32/arch.h folds IRQSTUBS_TEXT_SECTION
to the unconditional ".text.irqstubs" form.
* tests/subsys/llext/src/syscalls_ext.c drops a stale comment about
syscalls landing in .pinned_text.
Targeted retentions:
* arch/x86/core/bootargs.c keeps multiboot_cmdline and efi_bootargs
in .noinit (was __pinned_noinit, which decayed to __noinit when
LINKER_USE_PINNED_SECTION was unset). The multiboot and zefi loader
paths write these buffers before Zephyr's BSS-zero step, so
zeroing them at boot loses the cmdline.
* arch/x86/core/ia32/fatal.c keeps _df_esf and _df_stack in .noinit.
They are scratch space written by the double-fault handler and have
no zero-init requirement; keeping them in .noinit also preserves
the historical post-noinit alignment that gen_mmu.py relies on
(z_mapped_size is computed before CMake-injected iterable sections
are appended to the linker script, so the post-noinit page padding
is what keeps those sections within the mapped region).
* include/zephyr/arch/x86/ia32/syscall.h and
include/zephyr/arch/x86/arch.h wrap the per-arch
arch_syscall_invoke* / arch_is_user_context / arch_k_cycle_get_*
implementations in @cond INTERNAL_HIDDEN. The public Doxygen
contract lives on the prototypes in
include/zephyr/arch/arch_interface.h; the per-arch implementations
are internal. Without this, removing the __pinned_func attribute
exposes the implementations to the doxygen-coverage delta check
as 10 newly-undocumented APIs.
Documentation updates are deferred to a separate commit.
Issue: #108773
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
TLS area must be defined also when multithreading is disabled. Not doing
so whould cause access to libc variables like 'errno' to fail with a
crash.
This commit adds the TLS area for the single thread case by reserving
some space at the top of the main stack area.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Replace the opt-in locked marker with a legacy unlocked marker. With
this, SoC PM hooks use the locked IRQ contract by default, and only
legacy SoCs that still unmask interrupts from PM hooks select
PM_STATE_SET_IRQ_UNLOCKED.
Drop the old locked marker selections from already migrated NXP SoCs and
update the PM test expectation accordingly.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
arm_m_switch_stack_buffer is only defined when CONFIG_USE_SWITCH is
enabled. With link-time optimization or certain no-optimization builds
using Clang, the symbol is referenced unconditionally and the linker
fails with:
ld.lld: error: undefined symbol: arm_m_switch_stack_buffer
Move the reference inside a preprocessor guard so that the symbol is
only accessed when the kernel is built with CONFIG_USE_SWITCH.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for generating llext veneers for Arm baseline cores.
The veneer is AAPCS-compliant: r0-r3, r5-r11 and LR are preserved,
r4 is saved and restored, and only r12 (ip) is clobbered as
permitted by AAPCS.
Tested on RP2040 (Cortex-M0+) loading an extension that calls
__gnu_thumb1_case_uqi.
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
Enabling the FPU forces the choice between CONFIG_FP_HARDABI
and CONFIG_FP_SOFTABI. Both of these options allow the compiler
to generate FP instructions. As a result, all threads must have
the K_FP_REGS options bit set because we can not predict where
the compiler will generate those instructions.
The forced enablement is keyed off those ABI Kconfig options
and not FPU sharing nor the FPU enablement. This leaves the
option open for a future (as yet not implemented) case where
someone might want FPU support but not have the compiler generate
any FPU instructions at all.
Fixes#108793
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Add support for the Cortex-A32 processor. The Cortex-A32 processor
is built on the ARMv8-A architecture and supports only the AArch32
execution state.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add CONFIG_AARCH32_ARMV8_A_MONITOR_INIT to perform early Monitor mode
(EL3 AArch32) initialization at reset, modelled after z_arm64_el3_init()
in the arm64 port.
On ARMv8-A AArch32 platforms booting bare-metal without Trusted
Firmware-A, the core resets into Secure SVC mode. Certain system
registers (such as ICC_MSRE for GICv3) are only accessible from Monitor
mode. This option briefly switches to Monitor mode at reset to configure
such registers before returning to Secure SVC mode.
Currently used to configure ICC_MSRE, which enables GICv3 CPU
interface system register access at lower privilege levels (equivalent
to ICC_SRE_EL3 in the arm64 port).
ICC_MSRE_INIT reuses the existing ICC_SRE_ELx_* bit definitions from
cpu.h as the AArch32 ICC_MSRE shares the same bitfield layout as its
AArch64 counterpart ICC_SRE_EL3.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add a new AARCH32_ARMV8_A Kconfig symbol for ARMv8-A processors
running in AArch32 execution state, modelled after the existing
ARMv8-R AArch32 support. ARMv8-A AArch32 execution state is used
by processors such as the Cortex-A32 that implement only the AArch32
state as well as by other ARMv8-A processors that support AArch32
at specific exception levels.
A dedicated Kconfig symbol is needed (compared to simply reusing
ARMV7_A)because ARMv8-A AArch32 shares some code paths with ARMv7-A
and others with ARMv8-R AArch32. This also means that rather than
introducing a new standalone architecture port, the implementation
selectively extends the code paths used by either of these
architectures based on the architectural requirements as detailed
below.
MMU/fault handling: The implementation uses the existing short
descriptor translation table format used by ARMv7-A, sharing
the MMU programming and FSR encodings.
exception modes stack initialization: ARMv8-A AArch32 implements the
same exception modes as ARMv7-A and so reuses the ARMv7-A exception
mode stack initialization framework directly.
VBAR programming: Unlike ARMv7-A, ARMv8-A AArch32 mandates the use of
VBAR to store the vector table base address. So extend the vector
table relocation support already used by ARMv8-R AArch32. Also map
the vectors region from arch-level code rather than requiring each
SoC to provide this.
Arm generic timer support: The Generic Timer is mandatory in ARMv8-A
AArch32 and is accessed via the system register interface rather than
the memory-mapped I/O interface used by some ARMv7-A implementations.
The system-register-based timer path is therefore shared with ARMv8-R
AArch32.
interrupt masking: Reuse the CPSR based interrupt masking used by
ARMv7-A and ARMv8-R AArch32.
SVC based fatal error path: Reuse the SVC based fatal error path
shared by ARMv7-A and ARMv8-R AArch32.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
kernel.h implies kernel_structs.h via kernel_includes.h, making
explicit inclusion of kernel_structs.h unnecessary whenever kernel.h
is already included in the same translation unit.
Remove the redundant includes across arch, boards, drivers, kernel,
lib, samples, subsys, and tests trees.
in include/zephyr/kernel_structs.h:
* 2. kernel.h shall imply kernel_structs.h, such that it shall not be
* necessary to include kernel_structs.h explicitly when kernel.h is
* included.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
