michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arm: soc: Add support for ARM Beetle SoC

Browse source 
Add SoC support for ARM Beetle platform.

Beetle is an ARM Cortex-M3 based SoC used on ARM V2M Beetle Boards.

https://www.arm.com/products/tools/development-boards/versatile-express/beetle_iot_evaluation_platform.php

This patch contains:
* The base SoC platform.
* The clock_init functionality.
* The system wide pin definitions.
* The configuarion for the drivers at SoC level (IRQs, PINs and
  Base Addr).

Jira: ZEP-1245
Change-Id: If15675935890711983e5ce37d49732b0462c3ec7
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Vincenzo Frascino 2016-08-16 11:35:23 +01:00 • committed by Kumar Gala
commit df33a1e185
15 changed files with 688 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

18
arch/arm/soc/arm/Kbuild Normal file
View file

@ -0,0 +1,18 @@
# Kconfig - ARM LTD SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
obj-y += $(SOC_SERIES)/

29
arch/arm/soc/arm/Kconfig Normal file
View file

@ -0,0 +1,29 @@
# Kconfig - ARM LTD SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
config SOC_FAMILY_ARM
bool
# omit prompt to signify a "hidden" option
default n
if SOC_FAMILY_ARM
config SOC_FAMILY
string
default arm
endif
source "arch/arm/soc/arm/*/Kconfig.soc"

18
arch/arm/soc/arm/Kconfig.defconfig Normal file
View file

@ -0,0 +1,18 @@
# Kconfig - ARM LTD SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
source "arch/arm/soc/arm/*/Kconfig.defconfig.series"

18
arch/arm/soc/arm/Kconfig.soc Normal file
View file

@ -0,0 +1,18 @@
# Kconfig - ARM LTD SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
source "arch/arm/soc/arm/*/Kconfig.series"

37
arch/arm/soc/arm/beetle/Kconfig.defconfig.beetle_r0 Normal file
View file

@ -0,0 +1,37 @@
# Kconfig - ARM LTD Beetle SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_BEETLE_R0
config SOC
default beetle_r0
#
# Beetle R0 has one SRAM bank:
# 128K @ 0x20000000
#
config SRAM_SIZE
default 128
#
# Beetle R0 has 256K@0x0 of flash.
#
config FLASH_SIZE
default 256
endif # SOC_BEETLE_R0

44
arch/arm/soc/arm/beetle/Kconfig.defconfig.series Normal file
View file

@ -0,0 +1,44 @@
# Kconfig - ARM LTD Beetle SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_SERIES_BEETLE
source "arch/arm/soc/arm/beetle/Kconfig.defconfig.beetle*"
config SOC_SERIES
default beetle
config NUM_IRQ_PRIO_BITS
int
default 3
config NUM_IRQS
int
default 45
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 24000000
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x00000000
endif # SOC_SERIES_BEETLE

26
arch/arm/soc/arm/beetle/Kconfig.series Normal file
View file

@ -0,0 +1,26 @@
# Kconfig - ARM LTD Beetle SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
config SOC_SERIES_BEETLE
bool "ARM Beetle MCU Series"
depends on ARM
select CPU_CORTEX_M
select CPU_CORTEX_M3
select SOC_FAMILY_ARM
help
Enable support for Beetle MCU Series

26
arch/arm/soc/arm/beetle/Kconfig.soc Normal file
View file

@ -0,0 +1,26 @@
# Kconfig - ARM LTD Beetle SoC configuration options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
choice
prompt "ARM Beetle SoC"
depends on SOC_SERIES_BEETLE
config SOC_BEETLE_R0
bool "ARM BEETLE R0"
endchoice

19
arch/arm/soc/arm/beetle/Makefile Normal file
View file

@ -0,0 +1,19 @@
# Makefile - ARM LTD Beetle SoC build options
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
obj-y += soc.o

19
arch/arm/soc/arm/beetle/linker.ld Normal file
View file

@ -0,0 +1,19 @@
/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <arch/arm/cortex_m/scripts/linker.ld>

96
arch/arm/soc/arm/beetle/soc.c Normal file
View file

@ -0,0 +1,96 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief System/hardware module for the ARM LTD Beetle SoC
*
* This module provides routines to initialize and support board-level hardware
* for the ARM LTD Beetle SoC.
*/
#include <nanokernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <arch/cpu.h>
/**
* @brief Setup various clock on SoC.
*
* Setup the SoC clocks.
*
* Assumption:
* MAINCLK = 24Mhz
*/
static ALWAYS_INLINE void clock_init(void)
{
/* Enable AHB and APB clocks */
/* GPIO */
__BEETLE_SYSCON->ahbclkcfg0set = _BEETLE_GPIO0
| _BEETLE_GPIO1
| _BEETLE_GPIO2
| _BEETLE_GPIO3;
/*
* Activate clock for: I2C1, SPI1, SPIO, QUADSPI, WDOG,
* I2C0, UART0, UART1, TIMER0, TIMER1, DUAL TIMER, TRNG
*/
__BEETLE_SYSCON->apbclkcfg0set = _BEETLE_TIMER0
| _BEETLE_TIMER1
| _BEETLE_DUALTIMER0
| _BEETLE_UART0
| _BEETLE_UART1
| _BEETLE_I2C0
| _BEETLE_WDOG
| _BEETLE_QSPI
| _BEETLE_SPI0
| _BEETLE_SPI1
| _BEETLE_I2C1
| _BEETLE_TRNG;
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int arm_beetle_init(struct device *arg)
{
uint32_t key;
ARG_UNUSED(arg);
key = irq_lock();
/* Setup master clock */
clock_init();
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
return 0;
}
SYS_INIT(arm_beetle_init, PRE_KERNEL_1, 0);

98
arch/arm/soc/arm/beetle/soc.h Normal file
View file

@ -0,0 +1,98 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SoC configuration macros for the ARM LTD Beetle SoC.
*
*/
#ifndef _ARM_BEETLE_SOC_H_
#define _ARM_BEETLE_SOC_H_
#include "soc_irq.h"
/*
* The bit definitions below are used to enable/disable the following
* peripheral configurations:
* - Clocks in active state
* - Clocks in sleep state
* - Clocks in deep sleep state
* - Wake up sources
*/
/* Beetle SoC AHB Devices */
#define _BEETLE_GPIO0 (1 << 0)
#define _BEETLE_GPIO1 (1 << 1)
#define _BEETLE_GPIO2 (1 << 2)
#define _BEETLE_GPIO3 (1 << 3)
/* Beetle SoC APB Devices */
#define _BEETLE_TIMER0 (1 << 0)
#define _BEETLE_TIMER1 (1 << 1)
#define _BEETLE_DUALTIMER0 (1 << 2)
#define _BEETLE_UART0 (1 << 4)
#define _BEETLE_UART1 (1 << 5)
#define _BEETLE_I2C0 (1 << 7)
#define _BEETLE_WDOG (1 << 8)
#define _BEETLE_QSPI (1 << 11)
#define _BEETLE_SPI0 (1 << 12)
#define _BEETLE_SPI1 (1 << 13)
#define _BEETLE_I2C1 (1 << 14)
#define _BEETLE_TRNG (1 << 15)
/*
* Address space definitions
*/
/* Beetle SoC Address space definition */
#define _BEETLE_APB_BASE 0x40000000
#define _BEETLE_AHB_BASE 0x40010000
/* Beetle SoC AHB peripherals */
#define _BEETLE_GPIO0_BASE (_BEETLE_AHB_BASE + 0x0000)
#define _BEETLE_GPIO1_BASE (_BEETLE_AHB_BASE + 0x1000)
#define _BEETLE_GPIO2_BASE (_BEETLE_AHB_BASE + 0x2000)
#define _BEETLE_GPIO3_BASE (_BEETLE_AHB_BASE + 0x3000)
#define _BEETLE_SYSCON_BASE (_BEETLE_AHB_BASE + 0xF000)
/* Beetle SoC APB peripherals */
#define _BEETLE_UART0_BASE (_BEETLE_APB_BASE + 0x4000)
#define _BEETLE_UART1_BASE (_BEETLE_APB_BASE + 0x5000)
#ifndef _ASMLANGUAGE
#include <device.h>
#include <misc/util.h>
#include "soc_pins.h"
#include "soc_registers.h"
/* System Control Register (SYSCON) */
#define __BEETLE_SYSCON ((volatile struct syscon *)_BEETLE_SYSCON_BASE)
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define CMSDK_AHB_GPIO0 _BEETLE_GPIO0_BASE
#define CMSDK_AHB_GPIO1 _BEETLE_GPIO1_BASE
#define CMSDK_AHB_GPIO2 _BEETLE_GPIO2_BASE
#define CMSDK_AHB_GPIO3 _BEETLE_GPIO3_BASE
/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
#define CMSDK_APB_UART0 _BEETLE_UART0_BASE
#define CMSDK_APB_UART1 _BEETLE_UART1_BASE
#endif /* !_ASMLANGUAGE */
#endif /* _ARM_BEETLE_SOC_H_ */

74
arch/arm/soc/arm/beetle/soc_irq.h Normal file
View file

@ -0,0 +1,74 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Interrupt numbers for the ARM LTD Beetle SoC.
*/
#ifndef _ARM_BEETLE_SOC_IRQ_H_
#define _ARM_BEETLE_SOC_IRQ_H_
/* IRQ Numbers */
#define IRQ_UART0 0 /* UART 0 RX and TX Combined Interrupt */
#define IRQ_SPARE 1 /* Undefined */
#define IRQ_UART1 2 /* UART 1 RX and TX Combined Interrupt */
#define IRQ_I2C0 3 /* I2C 0 Interrupt */
#define IRQ_I2C1 4 /* I2C 1 Interrupt */
#define IRQ_RTC 5 /* RTC Interrupt */
#define IRQ_PORT0_ALL 6 /* GPIO Port 0 combined Interrupt */
#define IRQ_PORT1_ALL 7 /* GPIO Port 1 combined Interrupt */
#define IRQ_TIMER0 8 /* TIMER 0 Interrupt */
#define IRQ_TIMER1 9 /* TIMER 1 Interrupt */
#define IRQ_DUALTIMER 10 /* Dual Timer Interrupt */
#define IRQ_SPI0 11 /* SPI 0 Interrupt */
#define IRQ_UARTOVF 12 /* Common UART Overflow Interrupt */
#define IRQ_SPI1 13 /* SPI 1 Interrupt */
#define IRQ_QSPI 14 /* QUAD SPI Interrupt */
#define IRQ_DMA 15 /* Reserved for DMA Interrupt */
#define IRQ_PORT0_0 16 /* All P0 I/O pins used as irq source */
#define IRQ_PORT0_1 17 /* There are 16 pins in total */
#define IRQ_PORT0_2 18
#define IRQ_PORT0_3 19
#define IRQ_PORT0_4 20
#define IRQ_PORT0_5 21
#define IRQ_PORT0_6 22
#define IRQ_PORT0_7 23
#define IRQ_PORT0_8 24
#define IRQ_PORT0_9 25
#define IRQ_PORT0_10 26
#define IRQ_PORT0_11 27
#define IRQ_PORT0_12 28
#define IRQ_PORT0_13 29
#define IRQ_PORT0_14 30
#define IRQ_PORT0_15 31
#define IRQ_SYSERROR 32 /* System Error Interrupt */
#define IRQ_EFLASH 33 /* Embedded Flash Interrupt */
#define IRQ_LLCC_TXCMD_EMPTY 34 /* Cordio */
#define IRQ_LLCC_TXEVT_EMPTY 35 /* Cordio */
#define IRQ_LLCC_TXDMAH_DONE 36 /* Cordio */
#define IRQ_LLCC_TXDMAL_DONE 37 /* Cordio */
#define IRQ_LLCC_RXCMD_VALID 38 /* Cordio */
#define IRQ_LLCC_RXEVT_VALID 39 /* Cordio */
#define IRQ_LLCC_RXDMAH_DONE 40 /* Cordio */
#define IRQ_LLCC_RXDMAL_DONE 41 /* Cordio */
#define IRQ_PORT2_ALL 42 /* GPIO Port 2 combined Interrupt */
#define IRQ_PORT3_ALL 43 /* GPIO Port 3 combined Interrupt */
#define IRQ_TRNG 44 /* Random number generator Interrupt */
/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
#define CMSDK_APB_UART_0_IRQ IRQ_UART0
#define CMSDK_APB_UART_1_IRQ IRQ_UART1
#endif /* _ARM_BEETLE_SOC_IRQ_H_ */

43
arch/arm/soc/arm/beetle/soc_pins.h Normal file
View file

@ -0,0 +1,43 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SoC Pin Out definition for the ARM LTD Beetle SoC.
*
*/
#define PIN_UART_0_RX 0
#define PIN_UART_0_TX 1
#define PIN_SPI_0_CS 10
#define PIN_SPI_0_MOSI 11
#define PIN_SPI_0_MISO 12
#define PIN_SPI_0_SCLK 13
#define PIN_I2C_0_SCL 14
#define PIN_I2C_0_SDA 15
#define PIN_UART_1_RX 16
#define PIN_UART_1_TX 17
#define PIN_SPI_1_CS 18
#define PIN_SPI_1_MOSI 19
#define PIN_SPI_1_MISO 20
#define PIN_SPI_1_SCK 21
#define PIN_I2C_1_SDA 22
#define PIN_I2C_1_SCL 23
/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
#define CMSDK_APB_UART_FUN_SEL 1
#define CMSDK_APB_UART_0_RX PIN_UART_0_RX
#define CMSDK_APB_UART_0_TX PIN_UART_0_TX
#define CMSDK_APB_UART_1_RX PIN_UART_1_RX
#define CMSDK_APB_UART_1_TX PIN_UART_1_TX

123
arch/arm/soc/arm/beetle/soc_registers.h Normal file
View file

@ -0,0 +1,123 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file SoC configuration macros for the ARM LTD Beetle SoC.
*
*/
#ifndef _ARM_BEETLE_SOC_REGS_H_
#define _ARM_BEETLE_SOC_REGS_H_
/* System Control Register (SYSCON) */
struct syscon {
/* Offset: 0x000 (r/w) remap control register */
volatile uint32_t remap;
/* Offset: 0x004 (r/w) pmu control register */
volatile uint32_t pmuctrl;
/* Offset: 0x008 (r/w) reset option register */
volatile uint32_t resetop;
/* Offset: 0x00c (r/w) emi control register */
volatile uint32_t emictrl;
/* Offset: 0x010 (r/w) reset information register */
volatile uint32_t rstinfo;
volatile uint32_t reserved0[3];
/* Offset: 0x020 (r/w)AHB peripheral access control set */
volatile uint32_t ahbper0set;
/* Offset: 0x024 (r/w)AHB peripheral access control clear */
volatile uint32_t ahbper0clr;
volatile uint32_t reserved1[2];
/* Offset: 0x030 (r/w)APB peripheral access control set */
volatile uint32_t apbper0set;
/* Offset: 0x034 (r/w)APB peripheral access control clear */
volatile uint32_t apbper0clr;
volatile uint32_t reserved2[2];
/* Offset: 0x040 (r/w) main clock control register */
volatile uint32_t mainclk;
/* Offset: 0x044 (r/w) auxiliary / rtc control register */
volatile uint32_t auxclk;
/* Offset: 0x048 (r/w) pll control register */
volatile uint32_t pllctrl;
/* Offset: 0x04c (r/w) pll status register */
volatile uint32_t pllstatus;
/* Offset: 0x050 (r/w) sleep control register */
volatile uint32_t sleepcfg;
/* Offset: 0x054 (r/w) flash auxiliary settings control register */
volatile uint32_t flashauxcfg;
volatile uint32_t reserved3[10];
/* Offset: 0x080 (r/w) AHB peripheral clock set in active state */
volatile uint32_t ahbclkcfg0set;
/* Offset: 0x084 (r/w) AHB peripheral clock clear in active state */
volatile uint32_t ahbclkcfg0clr;
/* Offset: 0x088 (r/w) AHB peripheral clock set in sleep state */
volatile uint32_t ahbclkcfg1set;
/* Offset: 0x08c (r/w) AHB peripheral clock clear in sleep state */
volatile uint32_t ahbclkcfg1clr;
/* Offset: 0x090 (r/w) AHB peripheral clock set in deep sleep state */
volatile uint32_t ahbclkcfg2set;
/* Offset: 0x094 (r/w) AHB peripheral clock clear in deep sleep state */
volatile uint32_t ahbclkcfg2clr;
volatile uint32_t reserved4[2];
/* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */
volatile uint32_t apbclkcfg0set;
/* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */
volatile uint32_t apbclkcfg0clr;
/* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */
volatile uint32_t apbclkcfg1set;
/* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */
volatile uint32_t apbclkcfg1clr;
/* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
volatile uint32_t apbclkcfg2set;
/* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
volatile uint32_t apbclkcfg2clr;
volatile uint32_t reserved5[2];
/* Offset: 0x0c0 (r/w) AHB peripheral reset select set */
volatile uint32_t ahbprst0set;
/* Offset: 0x0c4 (r/w) AHB peripheral reset select clear */
volatile uint32_t ahbprst0clr;
/* Offset: 0x0c8 (r/w) APB peripheral reset select set */
volatile uint32_t apbprst0set;
/* Offset: 0x0cc (r/w) APB peripheral reset select clear */
volatile uint32_t apbprst0clr;
/* Offset: 0x0d0 (r/w) AHB power down sleep wakeup source set */
volatile uint32_t pwrdncfg0set;
/* Offset: 0x0d4 (r/w) AHB power down sleep wakeup source clear */
volatile uint32_t pwrdncfg0clr;
/* Offset: 0x0d8 (r/w) APB power down sleep wakeup source set */
volatile uint32_t pwrdncfg1set;
/* Offset: 0x0dc (r/w) APB power down sleep wakeup source clear */
volatile uint32_t pwrdncfg1clr;
/* Offset: 0x0e0 ( /w) rtc reset */
volatile uint32_t rtcreset;
/* Offset: 0x0e4 (r/w) event interface control register */
volatile uint32_t eventcfg;
volatile uint32_t reserved6[2];
/* Offset: 0x0f0 (r/w) sram power control overide */
volatile uint32_t pwrovride0;
/* Offset: 0x0f4 (r/w) embedded flash power control overide */
volatile uint32_t pwrovride1;
/* Offset: 0x0f8 (r/ ) memory status register */
volatile uint32_t memorystatus;
volatile uint32_t reserved7[1];
/* Offset: 0x100 (r/w) io pad settings */
volatile uint32_t gpiopadcfg0;
/* Offset: 0x104 (r/w) io pad settings */
volatile uint32_t gpiopadcfg1;
/* Offset: 0x108 (r/w) testmode boot bypass */
volatile uint32_t testmodecfg;
};
#endif /* _ARM_BEETLE_SOC_REGS_H_ */