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stm32f4: Enable STM32Cube SDK support on stm32f4 family

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Enable HAS_CUBE config flag on stm32f4 family soc.h is updated to
include minimum include files from ext/hal/stm23cube

Change-Id: I35a8c33aab777167ee7029edc1b7a4f6d21fccd8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Erwan Gouriou 2016-11-02 13:54:19 +01:00 • committed by Kumar Gala
commit f595df3755
2 changed files with 9 additions and 38 deletions
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1
arch/arm/soc/st_stm32/stm32f4/Kconfig.series
View file

@ -21,5 +21,6 @@ config SOC_SERIES_STM32F4X
select CPU_CORTEX_M4
select SOC_FAMILY_STM32
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
select HAS_STM32CUBE
help
Enable support for STM32F4 MCU series

46
arch/arm/soc/st_stm32/stm32f4/soc.h
View file

@ -28,48 +28,16 @@
#ifndef _STM32F4_SOC_H_
#define _STM32F4_SOC_H_
/* peripherals start address */
#define PERIPH_BASE 0x40000000
/* use naming consistent with STMF4 Peripherals Library */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
/* UART */
#define USART1_ADDR (APB2PERIPH_BASE + 0x1000)
#define USART2_ADDR (APB1PERIPH_BASE + 0x4400)
#define USART6_ADDR (APB2PERIPH_BASE + 0x1400)
/* Reset and Clock Control */
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
#define GPIO_REG_SIZE 0x400
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
/* base address for where GPIO registers start */
#define GPIO_PORTS_BASE (GPIOA_BASE)
/* EXTI */
#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
/* IWDG */
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
/* FLASH */
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
/* SYSCFG */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
/* FIXME: keep these defines until we enable STM32CUBE on this family */
/* Then they will bre replaced by "USARTX_BASE" defines */
/* UART */
#define USART1_ADDR (APB2PERIPH_BASE + 0x1000)
#define USART2_ADDR (APB1PERIPH_BASE + 0x4400)
#define USART6_ADDR (APB1PERIPH_BASE + 0x1400)
#ifndef _ASMLANGUAGE
@ -77,6 +45,8 @@
#include <misc/util.h>
#include <drivers/rand32.h>
#include <stm32f4xx.h>
/* IO pin functions */
enum stm32f4x_pin_config_mode {
STM32F4X_PIN_CONFIG_DRIVE_PUSH_PULL,