Commit graph

2358 commits

Author SHA1 Message Date
Ioannis Glaropoulos
4a41f42e73 arch: arm: set interrupt stack protection with MSPLIM
This commit implements the build-in interrupt stack protection
via the native MSPLIM register in ARMv8-M MCUs that support the
Main Extension. Main stack pointer overflows will cause Stack
Overflow UsageFaults. In addition, the commit introduces a new
config option, BUILTIN_STACK_GUARD, allowing the user to enable
and use the built-in stack protection in ARMv8-M firmware.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Yannis Damigos
2fd277fccf arch/arm/soc/st_stm32/stm32f1: Add I2C1 to dts.fixup
This patch adds the missing defines for I2C1.

Fixes #7248.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-02 01:11:36 -04:00
Rajavardhan Gundi
08172cdf83 xtensa: provide XCC compiler support for Xtensa
This patchset provides Xtensa's xcc compiler support for Xtensa
projects in Cmake. This requires the below environment variables
to be defined aptly. The appropriate xcc license information also
need to be supplied.

ZEPHYR_GCC_VARIANT=xcc
TOOLCHAIN_VER=RF-2015.3-linux
XTENSA_CORE=cavs21_LX6HiFi3_RF3_WB16
XTENSA_SYSTEM=/opt/xtensa/XtDevTools/install/tools/
		RF-2015.3-linux/XtensaTools/config/
XTENSA_BUILD_PATHS=/opt/xtensa/XtDevTools/install/builds/

Change-Id: Ib3c10e8095439b0e32276ff37c00eca8420773ec
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Yannis Damigos
d9cdf7bf30 arch/arm/soc/st_stm32: Fix typos in soc.h
Fix typos in soc.h for stm32f1 and stm32l4 families.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-04-28 20:46:08 +05:30
Manivannan Sadhasivam
42a7c5732f arm: soc: Elaborate Kconfig strings for MPU selection
Some of the SoCs specify "Enable MPU" in Kconfig for enabling MPU
support. This will create ambiguity while selecting options via
menuconfig. Hence, append SoC family name to the selection strings
to looks more elaborative.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-04-28 20:38:12 +05:30
Manivannan Sadhasivam
c36e5ac129 arm: Fix title for SoC configuration in Kconfig
The title for selecting the configuration options for SoC's should be
"SoC Configuration" not "Board Configuration".

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-04-28 20:38:12 +05:30
Ioannis Glaropoulos
c7d808f965 arch: arm: improve help text for PROGRAMMABLE_FAULT_PRIOS option
Improve the help text of ARM k-config option
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-04-27 17:41:24 +05:30
Kumar Gala
ae5e11bebc arm: soc: NXP: Enable SEGGER RTT on all NXP SoCs
It seems like SEGGER is supported across all the NXP SoC families so
lets enable it across all of them.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-04-26 14:49:57 -05:00
Maureen Helm
adf5b36a78 lpc54114: Remove unused include in soc.c
The lpc54114 soc.c file included clock_config.h unnecessarily.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-24 07:55:48 -05:00
Maureen Helm
57e80e5345 ext: mcux: Reorganize imported drivers into soc family subfolders
We have been combining imported mcux drivers into a flattened directory
structure to maximize driver reuse, but the introduction of additional
nxp soc families (lpc and imx) to zephyr has introduced driver naming
conflicts. This caused us to rename and modify imported files, such as
fsl_gpio.c/h, to make them unique across all three nxp soc families.
This makes updating the the mcux drivers complicated, especially for the
lpc family.

Reoganize the mcux drivers into soc family subfolders, so we can just
copy all the drivers from an mcux distribution (which is done on an
soc-basis) into the appropriate soc family folder. Undo all of the
naming changes that occurred when lpc and imx drivers were originally
imported. Undo the accidental squashing of the kinetis watchdog and dcdc
drivers that occurred when the imx drivers were introduced.

The drawback to this approach is that we have duplicate files when the
same hw ip modules exist in multiple soc families, however there are
only few cases where this occurs, such as fsl_lpuart and fsl_trng.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-24 07:55:48 -05:00
Andy Ross
15cb5d7293 kernel: Further unify _reschedule APIs
Now that other work has eliminated the two cases where we had to do a
reschedule "but yield even if we are cooperative", we can squash both
down to a single _reschedule() function which does almost exactly what
legacy _Swap() did, but wrapped as a proper scheduler API.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-04-24 03:57:20 +05:30
Andy Ross
8606fabf74 kernel: Scheduler refactoring: use _reschedule_*() always
There was a somewhat promiscuous pattern in the kernel where IPC
mechanisms would do something that might effect the current thread
choice, then check _must_switch_threads() (or occasionally
__must_switch_threads -- don't ask, the distinction is being replaced
by real English words), sometimes _is_in_isr() (but not always, even
in contexts where that looks like it would be a mistake), and then
call _Swap() if everything is OK, otherwise releasing the irq_lock().
Sometimes this was done directly, sometimes via the inverted test,
sometimes (poll, heh) by doing the test when the thread state was
modified and then needlessly passing the result up the call stack to
the point of the _Swap().

And some places were just calling _reschedule_threads(), which did all
this already.

Unify all this madness.  The old _reschedule_threads() function has
split into two variants: _reschedule_yield() and
_reschedule_noyield().  The latter is the "normal" one that respects
the cooperative priority of the current thread (i.e. it won't switch
out even if there is a higher priority thread ready -- the current
thread has to pend itself first), the former is used in the handful of
places where code was doing a swap unconditionally, just to preserve
precise behavior across the refactor.  I'm not at all convinced it
should exist...

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-04-24 03:57:20 +05:30
Ioannis Glaropoulos
0b7c964f5f arch: arm: clear BFSR sticky bits in ARMv8-M Mainline MCUs
Contrary to ARMv7-M, in ARMv8-M MCUs with the Main Extension,
BusFault Status Register bits are sticky and must be cleared.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-04-23 08:40:15 -05:00
Maureen Helm
50b69fbb55 arm: nxp_kinetis: Remove unused defines from soc.h
Now that we get gpio irq numbers from dts, we can remove the defines
from soc.h

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-20 08:54:11 -05:00
Ding Tao
b4696bd7ec arch: arm: Fix coding style in file irq_relay.S
Make the code more human readable by Remove some TABs.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-04-19 14:54:28 -05:00
Andy Gross
09a8810b33 arm: userspace: Rework system call arguments
This patch changes the ARM system calls to use registers for passing
or arguments.  This removes the possibility of stack issues when
callers do not adhere to the AAPCS.

Fixes #6802

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-04-16 10:13:20 -07:00
Adithya Baglody
95126d1af6 boards: sam_e70_xplained: Enable userspace
Enabled userspace support for Atmel SAMe70.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-04-16 09:01:49 -07:00
Leandro Pereira
4d5fbbc517 arch: arm: Flush pipeline after switching privilege levels
During the transition of privilege levels while performing syscalls,
the ARM documentation recommends flushing the pipeline to avoid
pre-fetched instructions from being executed with the previous
privilege level.

The manual says:
   4.16 CONTROL register
   (...) after programming the CONTROL register, an ISB instruction
   should be used.
   (...) This is not implemented in the Cortex M0 processor.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-04-13 15:35:45 -05:00
Andrzej Głąbek
397e52f099 arch: nrf52: Correct the number of IRQs in nRF52840
The old value does not cover the IRQ assigned to the SPIM3 peripheral.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-04-12 14:19:53 -04:00
David Leach
c563e33102 drivers: entropy: Change KW41Z to use XOROSHIRO for RNG source
The TRNG IP block in the KW41Z is really an entropy source and not
intended to be used as a general purpose random number generator
source. The block has 15 slots to read from and when the last slot
is read it has to regenerate the 15 numbers. This process takes
3-5 seconds and is blocking. The change here is to use the TRNG as
an entropy source to the XOROSHIRO pseudo random number function
and then have the KW41Z use XOROSHIRO for random number generation.

Signed-off-by: David Leach <david.leach@nxp.com>
2018-04-11 16:57:12 +03:00
David Leach
00885bbf28 OpenThread: Normalize IEEE802.15.4 driver name for use by L2 layers
- Removed OT_PLAT_RADIO_DEVICE_NAME
- Changed OpenThread binding to use NET_AP_IEEE802154_DEV_NAME
- Modified Kconfig chain to ensure NET_AP_IEEE802154_DEV_NAME
  is enabled for both native 802.15.4 and OpenThread configurations
- Changed default setting of NET_L2_IEEE802154 in defconfig for mkw41z4.
- Fixed OpenThread api support code to use the state of mIsCcaEnabled
  in the transmit frame to conditionally invoke radio_api->cc() on
  transmits.

Signed-off-by: David Leach <david.leach@nxp.com>
2018-04-11 16:57:12 +03:00
Diego Sueiro
816330239e arch: Add imx7d m4 soc support
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.

Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.

The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README

The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.

The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:

+---------------+-----------------+---------------------------+
| Memory Name   | Start Address   | Size                      |
+===============+=================+===========================+
| TCML          | 0x007F8000      | 32KB                      |
+---------------+-----------------+---------------------------+
| TCMU          | 0x20000000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM_S       | 0x20180000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM         | 0x00900000      | 128KB                     |
+---------------+-----------------+---------------------------+
| DDR           | 0x10000000      | 256MB                     |
+---------------+-----------------+---------------------------+

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-04-11 08:27:05 +02:00
Erwan Gouriou
6c2047fcd0 arch/arm: stm32: All SoCs have dts for I2C and SPI
All boards based on STM32 should use dts for I2C and SPI.
Move CONFIG flags selection from boards to arch and select them
for all STM32 SoCs.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-04-10 08:27:50 -05:00
Andrew Boie
548421828e arm_mpu: fix _get_region_attr()
srd bits start at bit 8, not bit 5.
To date we are not using sub-regions so this problem was
undetected.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-04-09 17:15:15 -05:00
Ilya Tagunov
77bbc42eaf arch: arm: soc: stm32l0: fix port H EXTI
Ports F and G are not present on some STM32L0 parts, so
for these parts port H external interrupt should be enabled
by writing value 0x5 instead of 0x7 to SYSCFG_EXTICRn registers
(see e.g. RM0367, 10.2.4).

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-04-05 10:31:43 -05:00
Paolo Teti
700e4bd2e8 ARM: -march compile option is not set
Removing ${} variable evaluation fixes the issue.

For sam4s_xplained:

Before:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
/repos/zephyr/samples/hello_world/build$

After:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
...
-mthumb -mcpu=cortex-m4 -march=armv7e-m
...

Signed-off-by: Paolo Teti <paolo.teti@gmail.com>
2018-04-05 08:36:04 -04:00
Tomasz Bursztyka
324265420b api/spi: Disable legacy API by default
Let's start deprecation work of the SPI legacy API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Anas Nashif
993c350b92 cleanup: replace old jira numbers with GH issues
Replace all references to old JIRA issues (ZEP) with the corrosponding
Github issue ID.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-26 13:13:04 -04:00
Tomasz Bursztyka
d95fa65270 drivers/i2c: Cleanup Kconfig
Move driver specific to dedicated file when relevant (i.e.: more than
1-2 options), use if/endif also.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Carles Cufi
6656969598 arch: arm: nordic_nrf: Restore copyright years
A previous commit had mistakenly overwritten the copyright years instead
of extending the range. Fix this mistake so that the proper range is
recorded.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 13:25:44 +01:00
Carles Cufi
b2016da563 arch: arm: nrf: Rename common header to apply to all nRFx ICs
The existing nrf5_common.h now applies to other Nordic ICs that are not
part of the "5" family. Instead rename this to nrf_common.h to cover the
upcoming ICs that belong to other families.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 11:57:14 +01:00
Carles Cufi
f49150cab6 arch: arm: nrf: Rename nrf5 SoC Family to nrf
Upcoming Nordic ICs that share many of the peripherals and architecture
with the currently supported nRF5x ones are no longer part of the nRF5
family. In order to accomodate that, rename the SoC family from nrf5 to
nrf, so that it can contain all of the members of the wider Nordic
family.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 11:57:14 +01:00
Anas Nashif
e5f1b51f01 debug: fix RTT console Kconfig
Use HAS_ Kconfig option as intended, those are invisible option that
signify support of a certain feature that can be selected by a hardware
or platform.

For RTT and system view this was not dont in an inconsistent way.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-19 15:37:26 -04:00
Ilya Tagunov
48a5fbcaa9 drivers: flash: stm32f0: remove CONFIG_FLASH_PAGE_SIZE
STM32F0 flash driver already uses FLASH_PAGE_SIZE from HAL
in flash layout part, so CONFIG_FLASH_PAGE_SIZE is redundant
and confusing.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-18 17:02:53 -04:00
qianfan Zhao
494bf56811 arch: arm: soc: stm32f0: add STM32F070XB SOC
Add initial support for STM32F070XB SOC

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-03-16 09:18:08 -05:00
Ilya Tagunov
00c0520247 arch: arm: soc: stm32l0: add I2C support
Add SPI support for STM32L0 series.
L0 SPI peripheral requires SCK pin speed workaround
to function properly.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-15 10:53:26 -05:00
Sundar Subramaniyan
037dddbe8f dts: arm: nrf52840_pca10056: Use DT to configure USB
Configure USB using DT for nrf52840_pca10056

Signed-off-by: Sundar Subramaniyan <sundar.subramaniyan@gmail.com>
2018-03-15 12:39:53 +01:00
Ilya Tagunov
9ae3fdc2ef arch: arm: soc: stm32l0: add I2C support
Add I2C support for STM32L0 series. LL-based driver
was already in place, so I've just enable it.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-14 09:02:25 -05:00
Kumar Gala
c9b0208552 arm: mps2_an385: Move dts.fixup to board dir
Move the dts.fixup back to board dir in prep for support mps2_an521.
The memory maps between the two mps2_an385 and mps2_an521 differ greatly
so its easier to just keep the fixup files with the board.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-13 15:29:21 -05:00
Carles Cufi
9afb0cfab0 kconfig: Remove UTF-8 character from author's name
Kconfiglib does not support UTF-8 properly yet, so avoid issues by
removing the UTF-8 character from the name until this is fixed.

See https://github.com/ulfalizer/Kconfiglib/pull/41

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-13 20:30:15 +01:00
Ioannis Glaropoulos
5475de105b arch: arm: define the ARM_SECURE_FIRMWARE option
This commit introduces the ARM_SECURE_FIRMWARE k-option,
which indicates that we are building an ARM Secure application.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-13 10:23:40 -05:00
Ioannis Glaropoulos
a01e7903b2 arch: arm: SecureFault Handling for Cortex-M33
This commit contributes the implementation of the SecureFault
handling for ARMv8-M-based Cortex-M33. The implementation is
compiled conditionally with compile-time directive
CONFIG_ARM_SECURE_FIRMWARE, which is to signify the intention to
build a Secure image on ARMv8-M with Security Extensions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-13 10:23:40 -05:00
Ilya Tagunov
b6da79cb82 arch: arm: soc: stm32l0: add STM32L073xZ SOC
Add initial support for STM32L073xZ SOC which is not very different
from already supported STM32L072xZ.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-13 10:23:23 -05:00
Ilya Tagunov
6a1cb6540f arch: arm: soc: stm32l0: fix indentation and comments in Kconfigs
Fix indentation and small comment typos in Kconfigs.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-13 10:23:23 -05:00
Aapo Vienamo
422bc240b4 soc: nrf5: Use i2c configure options generated from dts
SoC dts fixups are added and the i2c_nrf5 driver is modified to use
the values generated from the device tree.

The I2C_*_DEFAULT_CFG and I2C_*_IRQ_PRI options are removed from board
defconfigs. Bitrate and IRQ priority are configured using using the
device tree instead.

HAS_DTS_I2C is selected on all nrf5 boards to prevent generation of
conflicting defines from Kconfig.

Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi>
2018-03-13 14:14:13 +01:00
Ioannis Glaropoulos
c028f88b37 arch: arm: remove redundant asm inline headers
This commit removes the unnecessary asm inline header for ARM.
It also adapts the stack.h and exc.h to use the ARM CMSIS inline
functions to access the IPSR and MSP registers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-12 10:14:12 -05:00
Ioannis Glaropoulos
10b40ecaba arch: arm: conditionally select FP extension in cortex-m MCUs
This commit conditionally selects the ARMV7_M_ARMV8_M_FP option
in ARMv7-M/ARMv8-M Mainline processors, when the Floating Point
Extension is implemented (CPU_HAS_FPU is selected).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-11 21:53:50 -05:00
Ioannis Glaropoulos
b75b01050d arch: arm: Stack Overflow Usage Fault log for ARMv8-M Mainline
This commit contributes the Stack Overflow UsageFault dumping
for ARMv8-M implementations that support the Main Extension.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Ioannis Glaropoulos
cfab6e0806 arch: arm: define ARMv8-M Mainline K-option
This commit introduces the ARMV8_M_MAINLINE K-config option. The
option signifies the use of an ARMv8-M CPU supporting the Main
Extension. ARMv8-M Main Extension includes additional features
that are  not present in the ARMv7-M architecture.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Ioannis Glaropoulos
d2e0d975f6 arch: arm: ARMv7-M/ARMv8-M Mainline dependency for programmable prios
This commit forces CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS to
depend on ARMV7_M_ARMV8_M_MAINLINE. This allows the user to get
a build warning if he manually selects
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS for a CPU that does
not implement either ARMv7-M or ARMv8-M Mainline.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00