Commit graph

2358 commits

Author SHA1 Message Date
Ioannis Glaropoulos
0967f11f6d arch: arm: enhance internal function documentation
This commit enhaces the documentation of internal functions
in arm_mpu.c by explicitly stating that the caller needs to
ensure the validity of the supplied MPU region index. The
warning is required as these functions modify the ARM MPU_RNR
register, without checking themselves the validity of the
provided region number.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
7b77a25f14 arch: arm: coding and comment style fixes
This commit fixes some minor issues with coding style
and comment syntax in arm_mpu.c

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Joakim Andersson
45b75dd7ff arch: arm: Fix zero interrupt latency priority level
Change the zero latency interrupt priority level from 2 to 1.
This is the priority level that the kernel has reserved for the
zero latency IRQ feature by the _IRQ_PRIO_OFFSET constant.
The zero latency IRQ will now not be masked by the irq_lock function.

Update comments to reflect the priority levels reserved by the kernel.

Fixes: #8073

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2018-05-31 14:58:43 -04:00
Ioannis Glaropoulos
6399cb6b27 arch: arm: force MpuFaultHandler to inspect multiple error conditions
Upon MemManage Exception, multiple status bits of MMFSR may be
set. This commit modifies the MPU Fault Handler, so that it can
inspect and display information from all error conditions,
instead of just the first error condition that is true.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 14:05:58 -04:00
Ioannis Glaropoulos
56c9760834 arch: arm: use stored value for MMFAR
Make MPU stack guard checks use the previously stored value
of the MemManage Fault Address Register, to ensure that the
address-under-check is valid.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 14:05:58 -04:00
Gil Pitney
ec7d483b5b arch: arm: soc: cc2650: Remove dead code.
Remove the dead code that was guarded by previously removed
Kconfig symbols for the sensortag board.

With b028a51542,
this fixes #7873

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-30 22:20:37 -04:00
Johann Fischer
5fae373107 dts: nxp: fix typo in usbd bindings
Fix typo in usbd bindings.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-30 11:23:39 -05:00
Erwan Gouriou
f315afd0a7 arch: stm32: Fix inclusion of SPI headers
In some STM32 series, SPI LL headers where included under
CONFIG_CLOCK_CONTROL_STM32_CUBE flag definition.
Fix this and use CONFIG_SPI_STM32 instead.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-29 07:44:00 -07:00
Adithya Baglody
c2d632d69d arch: arm/arc: Remove usage of zephyr_library_ifdef.
Phasing out the usage of this cmake macro from the arch folder.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Adithya Baglody
a9ea155425 arch: arm: add_subdirectory shouldn't depend on a hidden kconfig.
Previously the directory core/cortex/mpu/ was getting included
on a hidden kconfig. Now this has been replaced with the Kconfig
CONFIG_ARM_CORE_MPU.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Carles Cufi
93a464321d arch: arm: nordic: nrf52: Enable instruction cache
Enable the instruction cache by default in order to achieve a speedup of
up to 20% in code execution.
Cache can be disabled by setting the new NRF_ENABLE_ICACHE Kconfig
option.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-05-28 17:59:38 +02:00
Aurelien Jarno
cbac8fcadb arch: arm: select CPU_HAS_FPU on STM32L4 family
All the STM32L4 SoCs have a Cortex-M4F CPU, and thus have a FPU. Update
stm32l4/Kconfig.series to select CPU_HAS_FPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-28 09:32:23 -05:00
Ulf Magnusson
cc4473831f soc: soc_family: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Ulf Magnusson
d946ed7328 soc: defconfig.series: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Ulf Magnusson
3ac3216d89 soc: defconfig: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Aurelien Jarno
a9fe133d07 arch: arm: fix a typos in Kconfig file
Architectue => Architecture

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-26 19:07:55 -04:00
Ioannis Glaropoulos
0825d0cd19 arch: arm: fix undefined variable bug
This commit fixes a compilation bug for an undefined variable
(mmfar), which is only conditionally defined. Instead of mmfar
we use the ARM register value directly.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-26 15:50:56 -04:00
Anthony Kreft
94a22daf36 arch: arm: STM32L053X8 support
Add support for the STM32L053X8 on the NUCLEO-L053R8 board.

Signed-off-by: Anthony Kreft <anthony.kreft@gmail.com>
2018-05-25 13:06:18 -05:00
Gil Pitney
9d2f370ddb boards: cc3220sf_launchxl: Make cc3220sf XIP by default
Previously, there was no easy command-line solution for loading
a Zephyr program to (internal) flash.
So, the default development method was to load via gdb/openocd
to SRAM and debug from there, thus making the cc3220sf platform
non-XIP (CONFIG_XIP=n) by default.

With new openocd v 1.10 updates from TI (git.ti.com/sdo-emu),
the image can now be flashed and debugged via gdb/openocd,
so the default will be changed to XIP (CONFIG_XIP=y).

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-25 11:59:00 -05:00
Jun Li
8cc002e657 soc: stm32f1: add port uart4
Enable supporting UART4 on STM32F107 and STM32F103Xe SoCs.
Modified stm32f1/dts.fixup for replacing USART with UART.

Signed-off-by: Jun Li <jun.r.li@intel.com>
2018-05-25 11:58:20 -05:00
Ilya Tagunov
1e6d827a53 drivers: serial: stm32: add LPUART support for L0/L4 series
LPUART (Low-power UART) peripheral is just like ordinary U(S)ART
which lives in a separate clock/power domain.
Therefore already existing code could be reused as is
almost entirely.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-05-25 11:54:42 -05:00
Ilya Tagunov
fd26514a4d drivers: serial: stm32: rework macros and fixups
STM32Lx LPUART peripherals do not fit well into existing U(S)ART
port numbering scheme, so there will be two separate namespaces
in Kconfig: one for U(S)ARTs and one for LPUARTs.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-05-25 11:54:42 -05:00
Andy Ross
3a0cb2d35d kernel: Remove legacy preemption checking
The metairq feature exposed the fact that all of our arch code (and a
few mistaken spots in the scheduler too) was trying to interpret
"preemptible" threads independently.

As of the scheduler rewrite, that logic is entirely within sched.c and
doing it externally is redundant.  And now that "cooperative" threads
can be preempted, it's wrong and produces test failures when used with
metairq threads.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-25 09:40:55 -07:00
Ioannis Glaropoulos
49f0dabfcc arch: arm: refactor default _FaultDump to provide fatal error code
Refactor the _FaultDump of the default debug-level (2) to
provide the error code that indicates the fatal error reason.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Ioannis Glaropoulos
d54dc42af9 arch: arm: refactor FAULT_DUMP to retrieve the fatal error reason
Refactor FAULT_DUMP macro to obtain and store the fatal error
reason. Make non-default version of FAULT_DUMP (i.e. with
CONFIG_FAULT_DUMP level 1) to retrieve the default reason
for fatal errors (_NANO_ERR_HW_EXCEPTION).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Ioannis Glaropoulos
d2c8a20560 arch: arm: document non-returning fatal handlers
Document that execution does not return from
_NanoFatalErrorHandler and _SysFatalErrorHandler.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Andrew Boie
6f6acb4667 arm_mpu: reduce boot MPU regions for various soc
The PPB, Peripheral, and any other I/O regions have been
removed, the Shareable options are only important with
unlocked dual cores. Just use the background mapping,
which is RWX for supervisor and no access for user mode.

The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.

Fixes #6896

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-24 19:19:07 -04:00
Andrew Boie
d9a227c19c arm: st_stm32: reduce boot MPU regions
The PPB and Peripheral regions have been removed,
the Shareable options are only important with unlocked
dual cores. Just use the background mapping.

The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.

Related to #6896 and #7877

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-24 15:31:00 -07:00
Ioannis Glaropoulos
46a3e8bdf0 arch: arm: fix fault status register bitfield masks
This commit fixes the bitfield masks for the Cortex-M
fault status registers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-24 11:31:54 -05:00
Aurelien Jarno
509e6964cc arch: stm32l432: add support for USB controller
The STM32L432 SoC has a standard non-OTG USB controller. Add an entry
for it in stm32l432.dtsi and add the corresponding DTS fixup entries.
The controller is kept disabled and should be enabled at the board
level.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-24 09:42:30 -05:00
Aurelien Jarno
dc01b99068 arch: stm32l4: only enable USB OTG on SoCs supporting it
USB OTG is currently enable for the whole STM32L4 family, while only a
few of them actually support it:

- STM32L475, STM32L476 and STM32L496 have an OTG controller
- STM32L432, STM32L433 and STM32L452 have an USB controller
- STM32L431, STM32L451 and STM32L471 do not have any USB controller

Fix that by moving the DT entry from stm32l4.dtsi to stm32l475.dtsi
and by adding a #ifdef #endif around the corresponding DTS fixup
entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-24 09:42:30 -05:00
Kumar Gala
8321b6b64f arch: arm: nxp: Fixup HAS_MCUX_RTC
When the RTC support get added we had a select on HAS_RTC, however this
Kconfig symbol didn't exist.  Clean this up to match the pattern of
HAS_MCUX_RTC.  The driver now depends on that and the SoC selects it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-24 08:21:24 -05:00
Erwan Gouriou
9559277094 arch: stm32: Remove unsupported MPU options
Some code was developped around MPU support in ealy stage
of feature introduction. This code was gated under MPU_ENABLE
flag which does not exist and hence code has never been
enabled nor tested.
Since there has been futher MPU development since then, it seems
safer to simply remove that code and associated Kconfig symbols
to avoid that someone starts using it while it was not part of
MPU development track.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-24 08:04:00 -04:00
Kumar Gala
6ef2f76b2f arch: arm: thread.c: Fix typo in comment
Changed CONFIG_BUIILTIN_STACK_GUARD to CONFIG_BUILTIN_STACK_GUARD.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
Kumar Gala
7faac6a761 arch: arm: atmel_sam: Add quotes to strings in Kconfig
While not technically required, its cleaner to ensure that strings
defaults are quoted.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
David B. Kinder
44383a394b doc: fix misspellings in Kconfig files
Found some misspellings missed during normal reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-05-23 16:57:20 -04:00
Carles Cufi
5b37cd7346 arch: arm: swap: Remove old context switch code
Remove unused context switch code from the helper assembly file that
manages the SuperVisor Call invocations (SVCs). This is no longer in use
in the code, since all calls to __swap() now go through PendSV directly.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-05-23 09:34:12 -07:00
Andrew Boie
99f36de0a1 arm: userspace: fix initial user sp location
The initial user stack pointer gets rounded to STACK_ALIGN_SIZE,
which can be much finer granularity than MPU regions. With
certain stack size values passed to k_thread_create(), the stack
pointer can be set past the defined region for the user thread's
stack, causing an immediate MPU fault.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-22 15:59:07 -07:00
Andrew Boie
9731a0cce9 arm: syscalls: fix some register issues
Upon return from a syscall handlers, the r1, r2, and r3 registers
could contain random kernel data that should not be leaked to user
mode. Zero these out before returning from _arm_do_syscall().
Fixes #7753.

The invocation macros need a clobber if r1, r2, or r3 are not used
to carry syscall arguments. This is a partial fix for #7754 but
there appear to be other issues.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-22 15:59:07 -07:00
Kumar Gala
edf7c4fd08 arch: arm: kw41z: Set DTS fixup for CONFIG_RTC_0_NAME
Recent change to RTC core now gets CONFIG_RTC_0_NAME from device tree.
So we need a fixup for KW41Z for that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-21 14:06:57 -05:00
Maureen Helm
b5db62ca94 frdm_kl25z: Remove incorrect references to spi
The kl25z does not have the same spi hardware as the k64f and therefore
cannot use the same spi driver. Remove all references to spi for the
kl25z soc and frdm_kl25z board until we have a valid spi driver.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-21 13:26:10 -05:00
Alexander Wachter
e73637af24 boards: stm: Add CAN support for stm32f072b micro controller
This commit adds the can device to the stm32f072b device tree and pinmux

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2018-05-19 20:19:30 +02:00
Stanislav Poboril
5477ee4531 mcux: Add MCUX IPM driver for lpc and kinetis socs
Add driver for MCUX mailbox which can be used for lpcxpresso54114
and other lpc and kinetis socs.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-05-17 15:07:48 -05:00
Kumar Gala
7514a92cbe arch: arm: nxp_lpc: Added support for init of slave core
Added ability to load and bootup the slave (Cortex-M0+) core on the
LPC54xxx SoC.  Currently we expect a binary image to be specified via
Kconfig for the code that will run on the slave core.  We also specify
via Kconfig the boot/load address for the slave core.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-17 15:07:48 -05:00
Kumar Gala
b7312d1bbc arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc
Add soc configuration support and dts files for nxp_lpc54xxx_m0.

Adjusted nxp_lpc54xxx soc, configuration and dts files for the
presence of slave core.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-17 15:07:48 -05:00
Maureen Helm
02253c231d nxp_kinetis: Fix rtc base address in kw41z dts.fixup
Since commit 081c9c3bec,
extract_dts_includes no longer appends _0 to peripheral base addresses.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-17 15:03:50 -05:00
Maureen Helm
e9ca0a7dae nxp_kinetis: Enable mcux watchdog driver on k64, kw2xd socs
Enables the mcux kinetis watchdog driver on k64 and kw2xd socs. Adds
relevant soc-level dts fixups.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-17 15:00:55 -05:00
Andy Gross
7b92d3fb1c rtc: nxp: Add RTC driver for NXP Kinetis
This patch adds the configuration, driver, and HAL changes required
to implement a MCUX based RTC driver for the NXP Kinetis KW41Z.

Signed-off-by: Andy Gross <agross@kernel.org>
2018-05-17 13:45:08 -05:00
Andy Gross
1fe586f678 dts: nxp: kw41z: Fixup NXP Kinetis RTCs on KW41Z
This patch adds some DTS information to flesh out the NXP Kinetis
based RTC blocks.  DTS fixups were added as well to match up the driver
usage to the DTS output.

Signed-off-by: Andy Gross <agross@kernel.org>
2018-05-17 13:45:08 -05:00
Florian Vaussard
ae71554be3 dts: stm32l4: add node and fixup for i2c4
Add the device tree node for I2C4 and the corresponding fixup.

Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
2018-05-17 13:08:36 -05:00