Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:
1. Rename Kconfig name
CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
a. arch/riscv/custom/thead/Kconfig: for T-Head extension
b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
(e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Update OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom
CSR common code. Move these stuff to 'arch/riscv/custom/openisa':
1. Rename 'soc_ri5cy.h' to 'ri5cy_csr.h' for CSR definitions.
2. Rename 'soc_zero_riscy.h' to 'zero_riscy_csr.h' for CSR definitions.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move compiler option '-march=rv32imcxpulpv2' to common code.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h',
allowing other SoCs using the CVA6 core to reuse the same CSR definitions.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to
'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Rework Andes-specific CSR to use RISC-V custom CSR common code.
Move these stuff to 'arch/riscv/custom/andes':
1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions.
2. Replace '_start' with '__reset' hook for low-level CSR initialization.
3. Move CSR context to common macro '__custom_csr_save/restore_context'.
4. Move 'EXECIT' CSR support to common code.
5. Move PMA CSR driver to common code.
6. Use RISC-V common linker.ld instead of SoC-specific linker.ld.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
RISC-V allows custom CSR implementation. Some SoCs from different vendors
may share the same core or the same custom CSR definitions and drivers.
This patch introduces 'arch/riscv/custom', which centralizes support
for custom CSRs, allowing code reuse across SoCs that come from different
vendors. Currently supported thess custom CSR:
1. Andes
2. Nuclei
3. OpenHWGroup CVA6
4. OpenISA RI5CY
5. OpenISA Zero-riscy
6. T-Head Xuantie
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The PMP initialization and thread seeding logic in arch/riscv/core/pmp.c
did not correctly handle scenarios where the global PMP entries span
across multiple `pmpcfg` hardware registers.
The `global_pmp_cfg` array, intended to store the hardware register
values, was hardcoded to size 1. This is only sufficient if all global
PMP entries fall within the range covered by the first `pmpcfg` register
(e.g., pmpcfg0). When more global entries are used, their configurations
reside in subsequent `pmpcfg` registers (pmpcfg1, pmpcfg2, etc.).
The code was only saving/restoring and checking `global_pmp_cfg[0]`,
leading to loss of configuration for entries mapped to higher `pmpcfg`
registers.
This patch fixes this by:
1. Resizing the `global_pmp_cfg` array to
`CONFIG_PMP_SLOTS / PMPCFG_STRIDE` to correctly accommodate values
from all potentially used `pmpcfg` CSRs.
2. In `z_riscv_pmp_init`, using `memcpy` to save the entire contents of
the local `pmp_cfg` array (derived from initial setup) into the
`global_pmp_cfg` array.
3. In `z_riscv_pmp_thread_init`, using `memcpy` to restore the entire
saved global configuration from `global_pmp_cfg` into a thread's
`pmp_cfg` array.
4. Updating the SMP consistency assertion in `z_riscv_pmp_init` to
compare the contents of the array element @ `index / PMPCFG_STRIDE`
of the `pmp_cfg` arrays.
These changes ensure that the configurations from all relevant `pmpcfg`
registers are preserved and correctly propagated to thread contexts.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Factor out the logic for reading PMP configuration registers (pmpcfgX)
from dump_pmp_regs into a new static inline helper function,
z_riscv_pmp_read_config.
This new function encapsulates the architecture-specific (RV32/RV64)
and slot-count-specific reads of the pmpcfg CSRs, improving code
organization and potential reusability.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Specifying undefined symbol on linker invocation requests the linker to
search and include the symbol.
This ensures the symbol will be present in final output.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Use the privileged stack when starting K_USER threads in arch_new_thread().
Threads entering user mode with k_thread_user_mode_enter() keep their
existing flow. To support both cases, z_arm_userspace_enter() now takes an
internal ABI flag (sp_is_priv) indicating whether PSP already points to
the privileged stack.
Also fix calculation of the privileged stack top: use priv_stack_end
directly instead of priv_stack_start + CONFIG_PRIVILEGED_STACK_SIZE, which
failed to account for guard/FPU offsets applied to priv_stack_start.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The arrays used for M-mode Physical Memory Protection (PMP),
specifically for the stack guard feature (CONFIG_PMP_STACK_GUARD),
were previously sized using the hardcoded PMP_M_MODE_SLOTS macro,
defined as 8. This affected arrays in both the _thread_arch
struct (m_mode_pmpaddr_regs, m_mode_pmpcfg_regs) and local
variables within the z_riscv_pmp_stackguard_disable function.
This commit changes the array sizing to use the Kconfig option
CONFIG_PMP_SLOTS. This option reflects the total number of PMP
slots available and configured for the target hardware.
Using CONFIG_PMP_SLOTS ensures these arrays are dimensioned
according to the system's actual capabilities, providing better
flexibility and correctness over a fixed size.
The PMP_M_MODE_SLOTS macro definition has been removed from
thread.h as it is no longer used.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Introduce hook for customize reset.S code even before stack is
initialized or RAM is accessed. Hook can be enabled using
CONFIG_SOC_EARLY_RESET_HOOK=y.
Hook implementation is by soc_early_reset_hook() function which should
be provided by custom code.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Currently, CORTEX_M_DWT option does not refresh its value when
TIMING_FUNCTIONS, on which it depends, is selected via menuconfig.
This occurs because during the early west build steps the
aarch32-specific Kconfig file is parsed with TIMING_FUNCTIONS=n,
resulting in CORTEX_M_DWT being set to 'n' (not set) in .config.
Later, when the user runs west with -t menuconfig and sets
TIMING_FUNCTIONS=y using the menus or any other option that selects
TIMING_FUNCTIONS=y indirectly, CORTEX_M_DWT is already set to 'n' and
remains set as such. That is inconvenient, and, moreoever, since
CORTEX_M_DWT gets set if TIMING_FUNCTIONS is set in prj.conf, the
current behavior is not consistent, i.e. via the menuconfig setting
TIMING_FUNCTIONS=y doesn't imply selecting CORTEX_M_DWT automatically.
This commit addresses this issue by selecting CORTEX_M_DWT=y if
TIMING_FUNCTIONS becomes set to 'y', otherwise allowing it to be set via
the prompt. This is possible by making the CORTEX_M_DWT prompt
conditional. Hence, in menuconfig, if TIMING_FUNCTIONS gets set
CORTEX_M_DWT is set automatically. If TIMING_FUNCTIONS is not set, a
prompt is presented to allow selecting CORTEX_M_DWT manually.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
- add NXP_BOARD_SPECIFIC_MPU_SETTINGS kconfig to provide a switch
for developer if they want to use private mpu settings
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==1 | NXP default setting
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==0 | User specific
- Use DT function to get memory base address and region size for cm7
- CM33 use dts to set mpu settings
- Add REGION_CUSTOMED_MEMORY_SIZE macro provide a common mapping ways
to map actual memory_size_kb to "region_size"
- The settings of the unified memory on cm33/cm7 cores:
ocram1/flexspi2 -> REGION_RAM_NOCACHE_ATTR
ocram2/dtcm -> REGION_RAM_NOCACHE_ATTR
flexspi/itcm -> REGION_FLASH_ATTR
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The config PM_S2RAM_CUSTOM_MARKING is not an optional config for a
user to select, it is required by some soc implementations of S2RAM,
in which case it must be selected by the soc.
Refactor the configuration to be HAS_PM_S2RAM_CUSTOM_MARKING, and
make the currently only soc which needs it select it. Then update
samples which previously had to select this option for this soc.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Several static functions in ptables.c always return 0, make them void
to improve readability.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Combine the load and noload cache regions for a single MPU aligned block.
This is required to have an MPU region with a size that is a power of 2.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
A warning was promoted to error in twister runs due to implicit
declaration of the function `z_arm64_safe_exception_stack_init()`.
Include `kernel_arch_func.h` in `prep_c.c` to mitigate the warning.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
- Add calls to sys_trace_idle_exit before leaving idle state
to track CPU load
- Extend CPU_LOAD to CPU_CORTEX_A in Kconfig
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Initialize the privilege stack and switch PSP to it early in the SVC
handler to ensure `z_arm_do_syscall` does not start on a user-accessible
stack frame.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Improve FPU trap debugging by showing the program counter (PC) of
instructions that trigger FPU access traps instead of potentially
stale saved FPU context data.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
CONFIG_FLASH_SIZE and CONFIG_FLASH_BASE_ADDRESS symbols were not defined in
native_sim even though it has a flash controller and flash defined.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
Select ARCH_SUPPORTS_COREDUMP_STACK_PTR on xtensa, and provide an
implementation for the arch_coredump_stack_ptr_get function.
Signed-off-by: Mark Holden <mholden@meta.com>
Do not directly include and use APIs from ksched.h outside of the
kernel. For now do this using more suitable (ipi.h and
kernel_internal.h) internal APIs until more cleanup is done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
To support unprivileged mode (CONFIG_USERSPACE):
- Set unprivileged PAC key registers when system is in unprivileged
mode.
- Add `bti` after each svc call, to make sure that the indirect jumps on
`lr` while returning from an `svc` don't result in a usage fault.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Add a config option to set unique PAC keys per thread and
make sure to retain them during context switch.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
As part of enabling PACBTI support:
- Add config options to enforce PAC and BTI features
- Enable these config options based on the branch protection choice
selected for `ARM_PACBTI`
- Enforce PACBTI, based on the new config options, by enabling
corresponding PACBTI bits in CONTROL register and in FVP.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Rename and move PACBTI config options to common Kconfig so that
they could be re-used for arm64 in the future.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
z_prep_c does not return, mark it as such consistently across
architectures. We had some arches do that, others not. This resolves a
few coding guideline violations in arch code.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup init.c code and move early boot code into arch/ and make it
accessible outside of the boot process/kernel.
All of this code is not related to the 'kernel' and is mostly used
within the architecture boot / setup process.
The way it was done, some soc code was including kernel_internal.h
directly, which shouldn't be done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move under arch, as this is not a kernel feature really. arch also
matches the test idcentifier in place.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Not really a kernel feature, more for architecture, which is reflected
in how XIP is enabled and tested. Move it to architecture code to keep
which much of the 'implementation' and usage is.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce a new Kconfig option CPU_CORTEX_A78 to enable support for the
Arm Cortex-A78 CPU architecture within Zephyr. This configuration can be
selected by boards or SoCs that utilize the Cortex-A78 core, enabling
architecture-specific features and optimizations as needed.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
- No more need for special IRQ shadow stacks - just reuse the one
created for z_interrupt_stacks;
- Add the linker sections for the pairs of stack/shadow stack;
- Support shadow stack arrays.
Last item was a bit challenging: shadow stacks need to be initialised
before use, and this is done statically for normal shadow stacks. To
initialise the shadow stacks in the array, one needs how many entries it
has. While a simple approach would use `LISTIFY` to them do the
initialization on all entries, that is not possible as many stack arrays
are created using expressions instead of literals, such as
`CONFIG_MP_MAX_NUM_CPUS - 1`, which won't work with `LISTIFY`.
Instead, this patch uses a script, `gen_static_shstk_array.py` that
gathers all needed information and patches the ELF to initialize the
stack arrays. Note that this needs to be done before any other operation
on the ELF file that creates new representations, such as the .bin
output.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
It seems that, at least on tests, it's common to call k_thread_create()
on a thread multiple times. This trips a check for the CET shadow stack
- namely, set a shadow stack on a thread which already has a shadow
stack.
This patch adds a Kconfig option to allow that, iff the base address and
size of the new shadow stack are the same as before. This will trigger a
reset of the shadow stack, so it can be reused.
It may be the case that this behaviour (reusing threads) is more common
than only for tests, in which case it could make sense to change the
default - in this patch, is only true if ZTEST.
Even if being enabled by default becomes the reality, it would still
make sense to keep this option - more conscious apps could avoid the
need for the shadow stack reset code altogether.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
