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zephyr/soc/arm/nxp_imx/rt/soc.c

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arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/*
mimxrt1050: remove app specific code from soc file - Remove clock gating code to be compatible with A1 silicon - Remove PLL deinitialization code out of soc file Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-15 03:06:14 -08:00
* Copyright (c) 2017,2018, NXP
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <linker/sections.h>
#include <fsl_clock.h>
#include <arch/cpu.h>
headers: Refactor kernel and arch headers. This commit refactors kernel and arch headers to establish a boundary between private and public interface headers. The refactoring strategy used in this commit is detailed in the issue This commit introduces the following major changes: 1. Establish a clear boundary between private and public headers by removing "kernel/include" and "arch/*/include" from the global include paths. Ideally, only kernel/ and arch/*/ source files should reference the headers in these directories. If these headers must be used by a component, these include paths shall be manually added to the CMakeLists.txt file of the component. This is intended to discourage applications from including private kernel and arch headers either knowingly and unknowingly. - kernel/include/ (PRIVATE) This directory contains the private headers that provide private kernel definitions which should not be visible outside the kernel and arch source code. All public kernel definitions must be added to an appropriate header located under include/. - arch/*/include/ (PRIVATE) This directory contains the private headers that provide private architecture-specific definitions which should not be visible outside the arch and kernel source code. All public architecture- specific definitions must be added to an appropriate header located under include/arch/*/. - include/ AND include/sys/ (PUBLIC) This directory contains the public headers that provide public kernel definitions which can be referenced by both kernel and application code. - include/arch/*/ (PUBLIC) This directory contains the public headers that provide public architecture-specific definitions which can be referenced by both kernel and application code. 2. Split arch_interface.h into "kernel-to-arch interface" and "public arch interface" divisions. - kernel/include/kernel_arch_interface.h * provides private "kernel-to-arch interface" definition. * includes arch/*/include/kernel_arch_func.h to ensure that the interface function implementations are always available. * includes sys/arch_interface.h so that public arch interface definitions are automatically included when including this file. - arch/*/include/kernel_arch_func.h * provides architecture-specific "kernel-to-arch interface" implementation. * only the functions that will be used in kernel and arch source files are defined here. - include/sys/arch_interface.h * provides "public arch interface" definition. * includes include/arch/arch_inlines.h to ensure that the architecture-specific public inline interface function implementations are always available. - include/arch/arch_inlines.h * includes architecture-specific arch_inlines.h in include/arch/*/arch_inline.h. - include/arch/*/arch_inline.h * provides architecture-specific "public arch interface" inline function implementation. * supersedes include/sys/arch_inline.h. 3. Refactor kernel and the existing architecture implementations. - Remove circular dependency of kernel and arch headers. The following general rules should be observed: * Never include any private headers from public headers * Never include kernel_internal.h in kernel_arch_data.h * Always include kernel_arch_data.h from kernel_arch_func.h * Never include kernel.h from kernel_struct.h either directly or indirectly. Only add the kernel structures that must be referenced from public arch headers in this file. - Relocate syscall_handler.h to include/ so it can be used in the public code. This is necessary because many user-mode public codes reference the functions defined in this header. - Relocate kernel_arch_thread.h to include/arch/*/thread.h. This is necessary to provide architecture-specific thread definition for 'struct k_thread' in kernel.h. - Remove any private header dependencies from public headers using the following methods: * If dependency is not required, simply omit * If dependency is required, - Relocate a portion of the required dependencies from the private header to an appropriate public header OR - Relocate the required private header to make it public. This commit supersedes #20047, addresses #19666, and fixes #3056. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-25 00:08:21 +09:00
#include <arch/arm/cortex_m/cmsis.h>
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
#include <fsl_flexspi_nor_boot.h>
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#if CONFIG_USB_DC_NXP_EHCI
#include "usb_phy.h"
#include "usb_dc_mcux.h"
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#ifdef CONFIG_INIT_ARM_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* ARM PLL configuration for RUN mode */
const clock_arm_pll_config_t armPllConfig = {
.loopDivider = 100U
};
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#ifdef CONFIG_INIT_SYS_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* SYS PLL configuration for RUN mode */
const clock_sys_pll_config_t sysPllConfig = {
.loopDivider = 1U
};
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#ifdef CONFIG_INIT_USB1_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* USB1 PLL configuration for RUN mode */
const clock_usb_pll_config_t usb1PllConfig = {
.loopDivider = 0U
};
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#if CONFIG_USB_DC_NXP_EHCI
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#endif
soc: nxp_imx: rt: fix enet pll initialization config macro name - Update config macro name for enet pll - Update impacted defconfig of RT1052 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 14:01:41 +08:00
#ifdef CONFIG_INIT_ENET_PLL
/* ENET PLL configuration for RUN mode */
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
const clock_enet_pll_config_t ethPllConfig = {
arch: arm: nxp: imxrt1015: add device support - Add SoC information for RT1015 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-03-04 22:59:15 +08:00
#if defined(CONFIG_SOC_MIMXRT1021) || defined(CONFIG_SOC_MIMXRT1015)
arch: arm: nxp: imxrt1021: add device support - Add Soc information for RT1020 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-08 08:27:52 +08:00
.enableClkOutput500M = true,
soc: nxp_imx: Fix enabling ENET PLL outputs The ENET PLL should be enabled if the SoC is the MIMXRT1021 (it used by the ARM core) or if the ENET device is enabled. The 500MHz clock should be enabled if the SoC is the MIMXRT1021. The ENET clock should be enabled if the ENET device is enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-20 21:14:08 +01:00
#endif
#ifdef CONFIG_ETH_MCUX
soc: nxp_imx: Fix ethernet build error Fixes an ethernet build error introduced with MCUXpresso SDK 2.5.0, caused by a slight change in the ethernet pll configuration structure. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-04 09:15:37 -06:00
.enableClkOutput = true,
arch: arm: nxp: imxrt1021: add device support - Add Soc information for RT1020 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-08 08:27:52 +08:00
#endif
soc: nxp_imx: Fix ethernet build error Fixes an ethernet build error introduced with MCUXpresso SDK 2.5.0, caused by a slight change in the ethernet pll configuration structure. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-04 09:15:37 -06:00
.enableClkOutput25M = false,
.loopDivider = 1,
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
};
#endif
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#if CONFIG_USB_DC_NXP_EHCI
usb_phy_config_struct_t usbPhyConfig = {
BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
};
#endif
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
#ifdef CONFIG_INIT_VIDEO_PLL
const clock_video_pll_config_t videoPllConfig = {
.loopDivider = 31,
.postDivider = 8,
.numerator = 0,
.denominator = 0,
};
#endif
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
const __imx_boot_data_section BOOT_DATA_T boot_data = {
.start = CONFIG_FLASH_BASE_ADDRESS,
.size = CONFIG_FLASH_SIZE,
.plugin = PLUGIN_FLAG,
.placeholder = 0xFFFFFFFF,
};
const __imx_boot_ivt_section ivt image_vector_table = {
.hdr = IVT_HEADER,
.entry = CONFIG_FLASH_BASE_ADDRESS + CONFIG_TEXT_SECTION_OFFSET,
.reserved1 = IVT_RSVD,
soc: nxp_imx: Add support for device configuration data (DCD) Adds support for the device configuration data (DCD), which provides a sequence of commands to the imx rt boot ROM to initialize components such as an SDRAM. It is now possible to use the external SDRAM instead of the internal DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note, however, that the default board configurations still link data into internal DTCM, therefore you must use a device tree overlay to override "zephyr,sram = &sdram0" Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-28 08:43:48 -06:00
#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
.dcd = (uint32_t) dcd_data,
#else
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
.dcd = (uint32_t) NULL,
soc: nxp_imx: Add support for device configuration data (DCD) Adds support for the device configuration data (DCD), which provides a sequence of commands to the imx rt boot ROM to initialize components such as an SDRAM. It is now possible to use the external SDRAM instead of the internal DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note, however, that the default board configurations still link data into internal DTCM, therefore you must use a device tree overlay to override "zephyr,sram = &sdram0" Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-28 08:43:48 -06:00
#endif
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
.boot_data = (uint32_t) &boot_data,
.self = (uint32_t) &image_vector_table,
.csf = (uint32_t)CSF_ADDRESS,
.reserved2 = IVT_RSVD,
};
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/**
*
* @brief Initialize the system clock
*
* @return N/A
*
*/
arm: arch code naming cleanup This patch re-namespaces global variables and functions that are used only within the arch/arm/ code to be prefixed with z_arm_. Some instances of CamelCase have been corrected. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-30 12:31:07 -07:00
static ALWAYS_INLINE void clock_init(void)
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
{
/* Boot ROM did initialize the XTAL, here we only sets external XTAL
* OSC freq
*/
CLOCK_SetXtalFreq(24000000U);
CLOCK_SetRtcXtalFreq(32768U);
/* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1);
/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
CLOCK_SetMux(kCLOCK_PeriphMux, 0x1);
/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz
*/
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
mimxrt1050: fix dcdc value change process - to check status bit to make sure DCDC output is stable Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:59 +08:00
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK !=
(DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
;
}
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#ifdef CONFIG_INIT_ARM_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
#ifdef CONFIG_INIT_SYS_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
#ifdef CONFIG_INIT_USB1_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
soc: nxp_imx: rt: fix enet pll initialization config macro name - Update config macro name for enet pll - Update impacted defconfig of RT1052 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 14:01:41 +08:00
#ifdef CONFIG_INIT_ENET_PLL
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
CLOCK_InitEnetPll(&ethPllConfig);
#endif
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
#ifdef CONFIG_INIT_VIDEO_PLL
CLOCK_InitVideoPll(&videoPllConfig);
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
CLOCK_SetDiv(kCLOCK_ArmDiv, CONFIG_ARM_DIV); /* Set ARM PODF */
CLOCK_SetDiv(kCLOCK_AhbDiv, CONFIG_AHB_DIV); /* Set AHB PODF */
CLOCK_SetDiv(kCLOCK_IpgDiv, CONFIG_IPG_DIV); /* Set IPG PODF */
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* Set PRE_PERIPH_CLK to PLL1, 1200M */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3);
/* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
CLOCK_SetMux(kCLOCK_PeriphMux, 0x0);
#ifdef CONFIG_UART_MCUX_LPUART
/* Configure UART divider to default */
CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
#endif
mimxrt1050: remove app specific code from soc file - Remove clock gating code to be compatible with A1 silicon - Remove PLL deinitialization code out of soc file Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-15 03:06:14 -08:00
soc: nxp_imx: Enable mcux lpi2c driver and clocks Enables the mcux lpi2c shim driver and clocks on all imx rt socs when the i2c driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 15:22:22 -06:00
#ifdef CONFIG_I2C_MCUX_LPI2C
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set I2C divider to 6 */
#endif
soc: arm: Enable the lpspi driver and clock for the imxrt soc Enables the mcux lpspi shim driver and subsystem clock for the imxrt soc. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:18:41 -05:00
#ifdef CONFIG_SPI_MCUX_LPSPI
CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */
#endif
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
#ifdef CONFIG_DISPLAY_MCUX_ELCDIF
CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4);
CLOCK_SetDiv(kCLOCK_LcdifDiv, 1);
#endif
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#if CONFIG_USB_DC_NXP_EHCI
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
nxp_imx: Fix dts build error The SoC clock init code for USB was using a deprecated DTS define. Switch to using the non-deprecated form. Fixes: #17772 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-07-25 07:56:51 -05:00
DT_INST_0_NXP_KINETIS_USBD_CLOCKS_CLOCK_FREQUENCY);
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
nxp_imx: Fix dts build error The SoC clock init code for USB was using a deprecated DTS define. Switch to using the non-deprecated form. Fixes: #17772 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-07-25 07:56:51 -05:00
DT_INST_0_NXP_KINETIS_USBD_CLOCKS_CLOCK_FREQUENCY);
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
clock/usdhc: Enable clock of USDHC of i.MXRT Enable clock of USDHC of i.MXRT. Add clock interface for USDHC in ccm. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:28:35 -07:00
#if defined(CONFIG_DISK_ACCESS_USDHC1) || \
defined(CONFIG_DISK_ACCESS_USDHC2)
CLOCK_InitSysPfd(kCLOCK_Pfd0, 0x12U);
/* Configure USDHC clock source and divider */
#ifdef CONFIG_DISK_ACCESS_USDHC1
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U);
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc1);
#endif
#ifdef CONFIG_DISK_ACCESS_USDHC2
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 0U);
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc2);
#endif
#endif
soc: nxp: rt: Add CSI video support Add CSI node to generic nxp rt dtsi. Add corresponding dts binding. Add CSI capability for rt MCUs. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-07-01 14:47:14 +02:00
#ifdef CONFIG_VIDEO_MCUX_CSI
CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */
CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */
CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Set CSI source to OSC 24M */
#endif
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
imxrt1050: Disable low-power modes The imxrt1050 is configured to use SYSTICK for the kernel timer, but SYSTICK cannot wake up the soc from low-power modes. Disable low-power modes on this soc until we have support for an alternative timer. This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An earlier version of the board (EVK, not EVKB), had A0 silicon which by default did not enter low-power mode on a wfi. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-22 08:14:32 -05:00
/* Keep the system clock running so SYSTICK can wake up the system from
* wfi.
*/
CLOCK_SetMode(kCLOCK_ModeRun);
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
}
usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:23:35 -07:00
#if defined(CONFIG_DISK_ACCESS_USDHC1) || \
defined(CONFIG_DISK_ACCESS_USDHC2)
/* Usdhc driver needs to re-configure pinmux
* Pinmux depends on board design.
* From the perspective of Usdhc driver,
* it can't access board specific function.
* So SoC provides this for board to register
* its usdhc pinmux and for usdhc to access
* pinmux.
*/
static usdhc_pin_cfg_cb g_usdhc_pin_cfg_cb;
void imxrt_usdhc_pinmux_cb_register(usdhc_pin_cfg_cb cb)
{
g_usdhc_pin_cfg_cb = cb;
}
void imxrt_usdhc_pinmux(u16_t nusdhc, bool init,
u32_t speed, u32_t strength)
{
if (g_usdhc_pin_cfg_cb)
g_usdhc_pin_cfg_cb(nusdhc, init,
speed, strength);
}
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int imxrt_init(struct device *arg)
{
ARG_UNUSED(arg);
irq: Fix irq_lock api usage irq_lock returns an unsigned int, though, several places was using signed int. This commit fix this behaviour. In order to avoid this error happens again, a coccinelle script was added and can be used to check violations. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-08-14 17:57:08 -07:00
unsigned int oldLevel; /* old interrupt lock level */
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* disable interrupts */
oldLevel = irq_lock();
/* Watchdog disable */
soc: arm: Make statements evaluate boolean expressions MISRA-C requires that the if statement has essentially Boolean type. MISRA-C rule 14.4 Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-17 16:15:20 -08:00
if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0) {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
}
soc: arm: Make statements evaluate boolean expressions MISRA-C requires that the if statement has essentially Boolean type. MISRA-C rule 14.4 Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-17 16:15:20 -08:00
if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0) {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
}
RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
RTWDOG->TOVAL = 0xFFFF;
RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK)
| RTWDOG_CS_UPDATE_MASK;
/* Disable Systick which might be enabled by bootrom */
soc: arm: Make statements evaluate boolean expressions MISRA-C requires that the if statement has essentially Boolean type. MISRA-C rule 14.4 Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-17 16:15:20 -08:00
if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0) {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
SCB_EnableICache();
soc: arm: Make statements evaluate boolean expressions MISRA-C requires that the if statement has essentially Boolean type. MISRA-C rule 14.4 Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-17 16:15:20 -08:00
if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
mimxrt1050: check if D-cache is enabled before enabling it. An issue has been confirmed in CMSIS core header file in SCB_EnableDCache when stack is in cacheable memory. Issue report: https://github.com/ARM-software/CMSIS_5/issues/331 To workaround this issue by checking if Dcache's been enabled before trying to enable it. Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:54:53 +08:00
SCB_EnableDCache();
}
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
mimxrt1050: remove app specific code from soc file - Remove clock gating code to be compatible with A1 silicon - Remove PLL deinitialization code out of soc file Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-15 03:06:14 -08:00
/* Initialize system clock */
arm: arch code naming cleanup This patch re-namespaces global variables and functions that are used only within the arch/arm/ code to be prefixed with z_arm_. Some instances of CamelCase have been corrected. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-30 12:31:07 -07:00
clock_init();
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);
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