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kconfig: Clean up header comments and make them consistent Use this short header style in all Kconfig files: # <description> # <copyright> # <license> ... Also change all <description>s from # Kconfig[.extension] - Foo-related options to just # Foo-related options It's clear enough that it's about Kconfig. The <description> cleanup was done with this command, along with some manual cleanup (big letter at the start, etc.) git ls-files '*Kconfig*' | \ xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /' Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-01 13:45:29 +01:00
# i.MX RT series
soc: arm: nxp_imx: add rt117x support 1. Added RT10xx and RT11xx configs 2. Added a new soc file for rt117x. There are clock differences between the RT10xx and RT11xx series, hence the soc files have been separated. Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2020-11-24 10:45:02 +08:00
# Copyright (c) 2017-2021, NXP
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX_RT
config SOC_SERIES
soc: defconfig.series: Consistently quote string defaults In preparation for introducing a warning. Unquoted string defaults work through a quirk of Kconfig (undefined symbols get their name as their string value), but look confusing. It's done inconsistently now too. Suggested by Kumar Gala. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-25 21:09:37 +02:00
default "rt"
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between the beginning of the ROM area and the address of the first ROM section. This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because the first ROM section is not always the `.text` section. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-02-10 16:37:24 +09:00
config ROM_START_OFFSET
soc: nxp_imx: Disable IVT/DCD when building for mcuboot The bootloader application itself should contain the IVT/DCD in the header, but the chainable application doesn't. The ROM_START_OFFSET defaults to 0x400 otherwise the linker alignment isn't taken into account. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-03-25 09:33:56 +01:00
default 0x400 if BOOTLOADER_MCUBOOT
soc: boards: Reserve space for the imx boot header at the soc level Moves the default TEXT_SECTION_OFFSET from the board level to the soc level for the imx rt series. This offset is used to reserve space for the imx boot header for external xip flash images. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:54:42 -06:00
default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
drivers: pinctrl: refactor pin control support for imx rt Refactor iMX RT pin control support to use more generic names, as the IOMUXC peripheral is present on non RT iMX application cores. Additionally, make selection of the pin control driver occur at the SOC level. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-25 16:30:58 -05:00
config PINCTRL_IMX
default y if HAS_MCUX_IOMUXC
depends on PINCTRL
soc: add adc driver to the nxp rt series soc add adc support to the soc dts, add MCUX_12B1MSPS_SAR to the soc Kconfigs Signed-off-by: Andrei Auchynnikau <ovchinnikov@strim-tech.com>
2021-10-08 21:09:41 +03:00
config ADC_MCUX_12B1MSPS_SAR
default y if HAS_MCUX_12B1MSPS_SAR
depends on ADC
soc: nxp_imx: Promote driver defaults to soc series level Streamlines repetitious code enabling default drivers by promoting it to the soc series level. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-28 14:32:15 -06:00
soc: nxp_imx: rt: enable SWO output for iMX RT 10xx series enable swo output for iMX RT 10xx series. SWO pinmux settings are currently only present for the RT1060 and RT1064 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-25 11:30:36 -05:00
config LOG_BACKEND_SWO_FREQ_HZ
default 7500000
depends on LOG_BACKEND_SWO
drivers: mcux_flexspi: Default logging to disabled when XIP is used Program flow will behave incorrectly (memory and instruction fetches return invalid data) if Flexspi is accessed by the Flexspi driver while being used as XIP memory by the Cortex M7. Set logging to disabled by when XIP mode is used in the memc and flexspi drivers, and warn the user if they attempt to enable it. Fixes #40133 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-18 09:52:56 -06:00
if FLASH_MCUX_FLEXSPI_XIP
# Avoid RWW hazards by defaulting logging to disabled
choice FLASH_LOG_LEVEL_CHOICE
default FLASH_LOG_LEVEL_OFF
endchoice
choice MEMC_LOG_LEVEL_CHOICE
default MEMC_LOG_LEVEL_OFF
endchoice
endif
drivers: mcux_gpt_timer: Added GPT timer for HW clock Added a driver to enable the GPT timer on RT1xxx parts to be used instead of systick as a clock source. The timer is set to run in reset mode, and uses the low frequency 32kHz oscillator for power savings Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-10-13 17:28:05 -05:00
# set the tick per sec as a divider of the GPT clock source
config SYS_CLOCK_TICKS_PER_SEC
default 4096 if MCUX_GPT_TIMER
ARM: nxp_imx: rt10xx: get systick freq from 'sysclk' DT nodelabel So far systick frequency was duplicated in 'sysclk' DT nodelabel's 'clock-frequency' property and in per SoC SYS_CLOCK_HW_CYCLES_PER_SEC default value. Set the latter based on DT configuration. Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-08-31 23:05:34 +02:00
DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk)
drivers: mcux_gpt_timer: Added GPT timer for HW clock Added a driver to enable the GPT timer on RT1xxx parts to be used instead of systick as a clock source. The timer is set to run in reset mode, and uses the low frequency 32kHz oscillator for power savings Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-10-13 17:28:05 -05:00
config SYS_CLOCK_HW_CYCLES_PER_SEC
ARM: nxp_imx: rt10xx: get systick freq from 'sysclk' DT nodelabel So far systick frequency was duplicated in 'sysclk' DT nodelabel's 'clock-frequency' property and in per SoC SYS_CLOCK_HW_CYCLES_PER_SEC default value. Set the latter based on DT configuration. Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-08-31 23:05:34 +02:00
default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMX_RT10XX && CORTEX_M_SYSTICK
drivers: mcux_gpt_timer: Added GPT timer for HW clock Added a driver to enable the GPT timer on RT1xxx parts to be used instead of systick as a clock source. The timer is set to run in reset mode, and uses the low frequency 32kHz oscillator for power savings Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-10-13 17:28:05 -05:00
default 32768 if MCUX_GPT_TIMER
soc: arm: nxp: switch imxrt boards to use systick timer unless CONFIG_PM=y Switch all imxrt boards to use the systick timer by default, and only enable the GPT timer when using low power modes. This is desirable because the systick has a higher resolution, but the GPT can run while the core clock is gated, making it useful for low power modes. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-12-13 14:53:11 -06:00
# Disable systick if using MCUX_GPT_TIMER, as they will conflict
config CORTEX_M_SYSTICK
default n if MCUX_GPT_TIMER
soc: imx_rt: Enable IMX.RT General Power Controller Driver GPC driver is used for power management operations on RT series SoCs. Enable inclusion of the driver into the build. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-14 10:26:06 -06:00
config PM_MCUX_GPC
default y if HAS_MCUX_GPC
depends on SOC_SERIES_IMX_RT11XX && PM
soc: nxp_imx: Enable inclusion of power management HAL drivers Add KConfig symbols to select power management HAL drivers required for low power modes. Set ZTEST_NO_YEILD if PM is enabled, since RT series SOCs do not connect to a debugger in WAIT mode. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-27 10:50:56 -06:00
# Don't allow SOC to sleep after tests complete when PM is enabled
config ZTEST_NO_YIELD
default y if (ZTEST && PM)
if SOC_SERIES_IMX_RT10XX && PM
soc: rt10xx: Add power management support Add power management code for the RT10xx SOC. By default, the code will simply gate the core clock and transition the SOC to WAIT mode when sleeping, but if clocking hooks are register to reduce clock frequencies these will be called as well, and the SOC core voltage will be lowered for additional power savings. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-09 12:52:58 -06:00
config CODE_DATA_RELOCATION
default y
soc: nxp_imx: Enable inclusion of power management HAL drivers Add KConfig symbols to select power management HAL drivers required for low power modes. Set ZTEST_NO_YEILD if PM is enabled, since RT series SOCs do not connect to a debugger in WAIT mode. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-27 10:50:56 -06:00
config PM_MCUX_GPC
default y if HAS_MCUX_GPC
config PM_MCUX_DCDC
default y if HAS_MCUX_DCDC
config PM_MCUX_PMU
default y if HAS_MCUX_PMU
endif # SOC_SERIES_IMX_RT10XX && PM
soc: nxp: rt10xx: Increase workqueue size for enet Increase the size of the system workqueue stack if using nxp ethernet driver Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-09-08 15:31:05 -05:00
if ETH_NXP_ENET
config SYSTEM_WORKQUEUE_STACK_SIZE
default 1560
endif # ETH_NXP_ENET
soc: rt: Add flash chosen node functionality Add functionality for changing the code location based on the flash chosen node for RT devices. Remove obsolete Kconfigs that used to be used to set the code location for RT devices. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-02-23 10:50:50 -06:00
DT_CHOSEN_Z_FLASH := zephyr,flash
DT_COMPAT_FLEXSPI := nxp,imx-flexspi
kconfig: add CODE_SEMC for CODE_LOCATION Add CODE_SEMC to support nxp-rt series code run in external sdram. Signed-off-by: Frank Li <lgl88911@163.com>
2020-02-16 20:57:57 +08:00
soc: rt: Add flash chosen node functionality Add functionality for changing the code location based on the flash chosen node for RT devices. Remove obsolete Kconfigs that used to be used to set the code location for RT devices. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-02-23 10:50:50 -06:00
DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
kconfig: add CODE_SEMC for CODE_LOCATION Add CODE_SEMC to support nxp-rt series code run in external sdram. Signed-off-by: Frank Li <lgl88911@163.com>
2020-02-16 20:57:57 +08:00
soc: rt: Add flash chosen node functionality Add functionality for changing the code location based on the flash chosen node for RT devices. Remove obsolete Kconfigs that used to be used to set the code location for RT devices. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-02-23 10:50:50 -06:00
DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
soc: nxp_imx: Move code/data location configs to soc level The imx rt family of socs has several options for linking code and data into internal or external memories, and up until now we have handled these options at the board level. This has resulted in several Kconfig symbols being defined in multiple places and triggering warnings in documentation builds: warning: the default selection CODE_ITCM (defined at boards/arm/mimxrt1050_evk/Kconfig:13, boards/arm/mimxrt1060_evk/Kconfig:13) of <choice> (defined at boards/arm/mimxrt1050_evk/Kconfig:9) is not contained in the choice warning: the choice symbol CODE_ITCM (defined at boards/arm/mimxrt1050_evk/Kconfig:13, boards/arm/mimxrt1060_evk/Kconfig:13) is defined with a prompt outside the choice warning: the choice symbol CODE_HYPERFLASH (defined at boards/arm/mimxrt1050_evk/Kconfig:16, boards/arm/mimxrt1060_evk/Kconfig:16) is defined with a prompt outside the choice warning: the choice symbol CODE_QSPI (defined at boards/arm/mimxrt1050_evk/Kconfig:19, boards/arm/mimxrt1060_evk/Kconfig:19) is defined with a prompt outside the choice warning: the choice symbol CODE_ITCM (defined at boards/arm/mimxrt1050_evk/Kconfig:13, boards/arm/mimxrt1060_evk/Kconfig:13) is defined with a prompt outside the choice warning: the choice symbol CODE_HYPERFLASH (defined at boards/arm/mimxrt1050_evk/Kconfig:16, boards/arm/mimxrt1060_evk/Kconfig:16) is defined with a prompt outside the choice warning: the choice symbol CODE_QSPI (defined at boards/arm/mimxrt1050_evk/Kconfig:19, boards/arm/mimxrt1060_evk/Kconfig:19) is defined with a prompt outside the choice The number of warnings increased as we added more imx rt boards. Fix the warnings by moving code and data location configs from the board level to the soc level. The default memories for all imx rt boards are unchanged. The mimxrt10{20,50,60}_evk boards still default to hyperflash/qspi for code and sdram for data. The mimxrt1064_evk board still defaults to ITCM for code and DTCM for data because jlink does not yet support programming internal flash. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-02-12 15:46:31 -06:00
config FLASH_BASE_ADDRESS
soc: rt: Add flash chosen node functionality Add functionality for changing the code location based on the flash chosen node for RT devices. Remove obsolete Kconfigs that used to be used to set the code location for RT devices. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-02-23 10:50:50 -06:00
default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
if $(DT_FLASH_PARENT_IS_FLEXSPI)
soc: arm: nxp_imx: add rt117x support 1. Added RT10xx and RT11xx configs 2. Added a new soc file for rt117x. There are clock differences between the RT10xx and RT11xx series, hence the soc files have been separated. Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2020-11-24 10:45:02 +08:00
config FLASH_SIZE
soc: rt: Add flash chosen node functionality Add functionality for changing the code location based on the flash chosen node for RT devices. Remove obsolete Kconfigs that used to be used to set the code location for RT devices. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-02-23 10:50:50 -06:00
default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
if $(DT_FLASH_HAS_SIZE_PROP)
soc: nxp_imx: Add on-chip flash code location support iMXRT1064 has 4MB on-chip Flash memory (flexspi2) mapped to 0x70000000. Add it as configurable code location for MIMXRT1064-EVK board. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-02-21 13:18:06 +01:00
soc: nxp: rt1xxx: Enable NXP FlexRAM Enable NXP FlexRAM in DTS and SOC code. Do not configure flexram at runtime if the code is in the RAM. Fix RT1060 DT to be more accurate. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-09-14 19:40:17 -05:00
config MEMC
default y
soc: rt: Update USB config and device tree node names The USB config name has changed to USB_MCUX and the device tree node name has changed from nxp_kinetis_usbd to nxp_mcux_usbd Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-08-18 15:56:18 -05:00
choice USB_MCUX_CONTROLLER_TYPE
default USB_DC_NXP_EHCI
endchoice
soc: arm: nxp_imx: Link Segger RTT/SystemView sections in DTCM if chosen Configures Segger RTT and SystemView data linker sections to DTCM by default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in devicetree. This fixes a build warning in samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm chosen node. Note that there are runtime issues with Segger RTT and SystemView on this board that need further debug, but submitting this patch now to address nightly CI failures. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-07-02 15:32:18 -05:00
DT_CHOSEN_Z_DTCM := zephyr,dtcm
soc: arm: Use DTCM section for RTT and SystemView data on i.MX RT SoCs Configures i.MX RT SoCs that support cacheable external SDRAM to use the DTCM linker section for Segger RTT and SystemView data. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-11-02 16:58:42 -06:00
choice SEGGER_RTT_SECTION
soc: arm: nxp_imx: Link Segger RTT/SystemView sections in DTCM if chosen Configures Segger RTT and SystemView data linker sections to DTCM by default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in devicetree. This fixes a build warning in samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm chosen node. Note that there are runtime issues with Segger RTT and SystemView on this board that need further debug, but submitting this patch now to address nightly CI failures. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-07-02 15:32:18 -05:00
default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
soc: arm: Use DTCM section for RTT and SystemView data on i.MX RT SoCs Configures i.MX RT SoCs that support cacheable external SDRAM to use the DTCM linker section for Segger RTT and SystemView data. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-11-02 16:58:42 -06:00
depends on USE_SEGGER_RTT
endchoice
choice SEGGER_SYSVIEW_SECTION
soc: arm: nxp_imx: Link Segger RTT/SystemView sections in DTCM if chosen Configures Segger RTT and SystemView data linker sections to DTCM by default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in devicetree. This fixes a build warning in samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm chosen node. Note that there are runtime issues with Segger RTT and SystemView on this board that need further debug, but submitting this patch now to address nightly CI failures. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-07-02 15:32:18 -05:00
default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
soc: arm: Use DTCM section for RTT and SystemView data on i.MX RT SoCs Configures i.MX RT SoCs that support cacheable external SDRAM to use the DTCM linker section for Segger RTT and SystemView data. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-11-02 16:58:42 -06:00
depends on SEGGER_SYSTEMVIEW
endchoice
soc: arm: nxp_imx: rt: Configure settings for TRNG IP RT platforms that support TRNG IP (rt10xx and rt6xx) need to set RNG and CSRNG to Xoroshiro and CTR_DRBG respectively instead of using TRNG as random source. Fixes: #37307 Signed-off-by: David Leach <david.leach@nxp.com>
2021-08-02 17:21:16 -05:00
#
# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
#
config MBEDTLS
#config TINYCRYPT
random: Fix kconfig symbol name s/CSPRING_ENABLED/CSPRNG_ENABLED/g Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-09-22 14:04:03 -07:00
default y if CSPRNG_ENABLED
soc: arm: nxp_imx: rt: Configure settings for TRNG IP RT platforms that support TRNG IP (rt10xx and rt6xx) need to set RNG and CSRNG to Xoroshiro and CTR_DRBG respectively instead of using TRNG as random source. Fixes: #37307 Signed-off-by: David Leach <david.leach@nxp.com>
2021-08-02 17:21:16 -05:00
depends on ENTROPY_GENERATOR
if MBEDTLS
#
# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than
# what the ztest_thread_stack defaults to.
#
kconfig: Rename the TEST_EXTRA stack size option to align with the rest All stack sizes should end with STACK_SIZE. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2022-02-17 17:09:09 +01:00
config TEST_EXTRA_STACK_SIZE
soc: arm: nxp_imx: rt: Configure settings for TRNG IP RT platforms that support TRNG IP (rt10xx and rt6xx) need to set RNG and CSRNG to Xoroshiro and CTR_DRBG respectively instead of using TRNG as random source. Fixes: #37307 Signed-off-by: David Leach <david.leach@nxp.com>
2021-08-02 17:21:16 -05:00
int
default 1024
endif # MBEDTLS
soc: arm: nxp_imx: enable CONFIG_CACHE_MANAGEMENT for RT1xxx M7 cores Since d992683db5 (soc: arm: replace redundant config option for caches for nxp_imx), RT1xxx series will not have cache enabled at boot unless CONFIG_CACHE_MANAGEMENT=y. Since this will improve performance, enable CONFIG_CACHE_MANAGEMENT by default. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-01-10 14:33:44 +00:00
# Enable cache management features when using M7 core, since these parts
# have L1 instruction and data caches that should be enabled at boot
config CACHE_MANAGEMENT
default y if CPU_CORTEX_M7
arm: soc: move arm SoCs to top-dir Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-03 15:47:02 -05:00
source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*"
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
endif # SOC_SERIES_IMX_RT
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