2015-04-11 01:44:37 +02:00
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/* ns16550.c - NS16550D serial driver */
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2020-03-27 12:03:59 +01:00
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#define DT_DRV_COMPAT ns16550
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2015-04-11 01:44:37 +02:00
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/*
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* Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
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2020-01-04 00:22:47 +01:00
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* Copyright (c) 2020 Intel Corp.
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2015-04-11 01:44:37 +02:00
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 01:44:37 +02:00
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*/
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2015-08-21 00:10:21 +02:00
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/**
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* @brief NS16550 Serial Driver
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*
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* This is the driver for the Intel NS16550 UART Chip used on the PC 386.
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* It uses the SCCs in asynchronous mode only.
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*
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2015-12-01 17:42:19 +01:00
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* Before individual UART port can be used, uart_ns16550_port_init() has to be
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2015-08-21 00:10:21 +02:00
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* called to setup the port.
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*
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2015-09-02 16:04:06 +02:00
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* - the following macro for the number of bytes between register addresses:
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2015-08-21 00:10:21 +02:00
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*
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* UART_REG_ADDR_INTERVAL
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2015-07-01 23:22:39 +02:00
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*/
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2015-04-11 01:44:37 +02:00
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2018-05-22 13:44:40 +02:00
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#include <errno.h>
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2016-12-04 21:59:37 +01:00
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#include <kernel.h>
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2015-05-28 19:56:47 +02:00
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#include <arch/cpu.h>
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Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-19 17:32:08 +02:00
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#include <zephyr/types.h>
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2018-05-22 13:44:40 +02:00
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#include <soc.h>
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2015-04-11 01:44:37 +02:00
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2015-12-01 17:42:19 +01:00
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#include <init.h>
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2015-04-11 01:44:37 +02:00
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#include <toolchain.h>
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2017-06-17 17:30:47 +02:00
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#include <linker/sections.h>
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2019-06-25 21:54:01 +02:00
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#include <drivers/uart.h>
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2019-06-25 18:26:23 +02:00
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#include <sys/sys_io.h>
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2020-03-23 17:31:15 +01:00
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#include <spinlock.h>
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2015-12-01 17:42:19 +01:00
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2019-06-21 19:30:27 +02:00
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#include "uart_ns16550.h"
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2016-01-06 18:17:03 +01:00
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uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
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/*
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* If PCP is set for any of the ports, enable support.
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* Ditto for DLF and PCI(e).
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*/
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2020-03-27 12:03:59 +01:00
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#if DT_INST_NODE_HAS_PROP(0, pcp) || \
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DT_INST_NODE_HAS_PROP(1, pcp) || \
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DT_INST_NODE_HAS_PROP(2, pcp) || \
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DT_INST_NODE_HAS_PROP(3, pcp)
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uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
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#define UART_NS16550_PCP_ENABLED
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#endif
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2020-03-27 12:03:59 +01:00
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#if DT_INST_NODE_HAS_PROP(0, dlf) || \
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DT_INST_NODE_HAS_PROP(1, dlf) || \
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DT_INST_NODE_HAS_PROP(2, dlf) || \
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DT_INST_NODE_HAS_PROP(3, dlf)
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uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
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#define UART_NS16550_DLF_ENABLED
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#endif
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2020-03-27 12:03:59 +01:00
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#if DT_INST_PROP(0, pcie) || \
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DT_INST_PROP(1, pcie) || \
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DT_INST_PROP(2, pcie) || \
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DT_INST_PROP(3, pcie)
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2020-03-12 16:16:00 +01:00
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BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
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#define UART_NS16550_PCIE_ENABLED
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#include <drivers/pcie/pcie.h>
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#endif
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2015-04-11 01:44:37 +02:00
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/* register definitions */
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2019-02-24 00:18:28 +01:00
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#define REG_THR 0x00 /* Transmitter holding reg. */
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#define REG_RDR 0x00 /* Receiver data reg. */
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#define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define REG_IER 0x01 /* Interrupt enable reg. */
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#define REG_IIR 0x02 /* Interrupt ID reg. */
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#define REG_FCR 0x02 /* FIFO control reg. */
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#define REG_LCR 0x03 /* Line control reg. */
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#define REG_MDC 0x04 /* Modem control reg. */
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#define REG_LSR 0x05 /* Line status reg. */
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#define REG_MSR 0x06 /* Modem status reg. */
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#define REG_DLF 0xC0 /* Divisor Latch Fraction */
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#define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
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2015-04-11 01:44:37 +02:00
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/* equates for interrupt enable register */
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#define IER_RXRDY 0x01 /* receiver data ready */
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#define IER_TBE 0x02 /* transmit bit enable */
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#define IER_LSR 0x04 /* line status interrupts */
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#define IER_MSI 0x08 /* modem status interrupts */
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/* equates for interrupt identification register */
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2016-01-18 14:42:11 +01:00
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#define IIR_MSTAT 0x00 /* modem status interrupt */
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#define IIR_NIP 0x01 /* no interrupt pending */
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#define IIR_THRE 0x02 /* transmit holding register empty interrupt */
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#define IIR_RBRF 0x04 /* receiver buffer register full interrupt */
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#define IIR_LS 0x06 /* receiver line status interrupt */
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#define IIR_MASK 0x07 /* interrupt id bits mask */
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#define IIR_ID 0x06 /* interrupt ID mask without NIP */
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2015-04-11 01:44:37 +02:00
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/* equates for FIFO control register */
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#define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */
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#define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
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#define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
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2019-02-24 00:18:28 +01:00
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/* equates for Apollo Lake clock control register (PRV_CLOCK_PARAMS) */
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#define PCP_UPDATE 0x80000000 /* update clock */
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#define PCP_EN 0x00000001 /* enable clock output */
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2015-04-11 01:44:37 +02:00
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/*
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* Per PC16550D (Literature Number: SNLS378B):
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*
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* RXRDY, Mode 0: When in the 16450 Mode (FCR0 = 0) or in
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* the FIFO Mode (FCR0 = 1, FCR3 = 0) and there is at least 1
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* character in the RCVR FIFO or RCVR holding register, the
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* RXRDY pin (29) will be low active. Once it is activated the
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* RXRDY pin will go inactive when there are no more charac-
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* ters in the FIFO or holding register.
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*
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* RXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when the
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* FCR3 = 1 and the trigger level or the timeout has been
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* reached, the RXRDY pin will go low active. Once it is acti-
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* vated it will go inactive when there are no more characters
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* in the FIFO or holding register.
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*
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* TXRDY, Mode 0: In the 16450 Mode (FCR0 = 0) or in the
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* FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
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* ters in the XMIT FIFO or XMIT holding register, the TXRDY
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* pin (24) will be low active. Once it is activated the TXRDY
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* pin will go inactive after the first character is loaded into the
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* XMIT FIFO or holding register.
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*
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* TXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when
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* FCR3 = 1 and there are no characters in the XMIT FIFO, the
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* TXRDY pin will go low active. This pin will become inactive
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* when the XMIT FIFO is completely full.
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*/
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#define FCR_MODE0 0x00 /* set receiver in mode 0 */
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#define FCR_MODE1 0x08 /* set receiver in mode 1 */
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/* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */
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#define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */
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#define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */
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#define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */
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#define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */
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2016-11-15 03:23:45 +01:00
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/*
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* UART NS16750 supports 64 bytes FIFO, which can be enabled
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* via the FCR register
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*/
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#define FCR_FIFO_64 0x20 /* Enable 64 bytes FIFO */
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2015-04-11 01:44:37 +02:00
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/* constants for line control register */
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#define LCR_CS5 0x00 /* 5 bits data size */
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#define LCR_CS6 0x01 /* 6 bits data size */
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#define LCR_CS7 0x02 /* 7 bits data size */
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#define LCR_CS8 0x03 /* 8 bits data size */
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#define LCR_2_STB 0x04 /* 2 stop bits */
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#define LCR_1_STB 0x00 /* 1 stop bit */
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#define LCR_PEN 0x08 /* parity enable */
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#define LCR_PDIS 0x00 /* parity disable */
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#define LCR_EPS 0x10 /* even parity select */
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#define LCR_SP 0x20 /* stick parity select */
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#define LCR_SBRK 0x40 /* break control bit */
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#define LCR_DLAB 0x80 /* divisor latch access enable */
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/* constants for the modem control register */
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#define MCR_DTR 0x01 /* dtr output */
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#define MCR_RTS 0x02 /* rts output */
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#define MCR_OUT1 0x04 /* output #1 */
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#define MCR_OUT2 0x08 /* output #2 */
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#define MCR_LOOP 0x10 /* loop back */
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2015-07-31 12:57:00 +02:00
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#define MCR_AFCE 0x20 /* auto flow control enable */
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2015-04-11 01:44:37 +02:00
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/* constants for line status register */
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#define LSR_RXRDY 0x01 /* receiver data available */
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#define LSR_OE 0x02 /* overrun error */
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#define LSR_PE 0x04 /* parity error */
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#define LSR_FE 0x08 /* framing error */
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#define LSR_BI 0x10 /* break interrupt */
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2016-01-18 14:43:51 +01:00
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#define LSR_EOB_MASK 0x1E /* Error or Break mask */
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2015-04-11 01:44:37 +02:00
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#define LSR_THRE 0x20 /* transmit holding register empty */
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#define LSR_TEMT 0x40 /* transmitter empty */
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/* constants for modem status register */
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#define MSR_DCTS 0x01 /* cts change */
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#define MSR_DDSR 0x02 /* dsr change */
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#define MSR_DRI 0x04 /* ring change */
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#define MSR_DDCD 0x08 /* data carrier change */
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#define MSR_CTS 0x10 /* complement of cts */
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#define MSR_DSR 0x20 /* complement of dsr */
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#define MSR_RI 0x40 /* complement of ring signal */
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#define MSR_DCD 0x80 /* complement of dcd */
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/* convenience defines */
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2015-08-05 21:13:36 +02:00
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#define DEV_CFG(dev) \
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2020-05-19 22:31:19 +02:00
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((const struct uart_ns16550_device_config * const) \
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2020-03-09 12:49:07 +01:00
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(dev)->config_info)
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2015-08-05 21:13:36 +02:00
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#define DEV_DATA(dev) \
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((struct uart_ns16550_dev_data_t *)(dev)->driver_data)
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2020-05-15 02:47:27 +02:00
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#define THR(dev) (get_port(dev) + REG_THR * UART_REG_ADDR_INTERVAL)
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#define RDR(dev) (get_port(dev) + REG_RDR * UART_REG_ADDR_INTERVAL)
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2020-01-04 00:22:47 +01:00
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#define BRDL(dev) \
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2020-05-15 02:47:27 +02:00
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(get_port(dev) + REG_BRDL * UART_REG_ADDR_INTERVAL)
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2020-01-04 00:22:47 +01:00
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#define BRDH(dev) \
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2020-05-15 02:47:27 +02:00
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(get_port(dev) + REG_BRDH * UART_REG_ADDR_INTERVAL)
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|
#define IER(dev) (get_port(dev) + REG_IER * UART_REG_ADDR_INTERVAL)
|
|
|
|
#define IIR(dev) (get_port(dev) + REG_IIR * UART_REG_ADDR_INTERVAL)
|
|
|
|
#define FCR(dev) (get_port(dev) + REG_FCR * UART_REG_ADDR_INTERVAL)
|
|
|
|
#define LCR(dev) (get_port(dev) + REG_LCR * UART_REG_ADDR_INTERVAL)
|
|
|
|
#define MDC(dev) (get_port(dev) + REG_MDC * UART_REG_ADDR_INTERVAL)
|
|
|
|
#define LSR(dev) (get_port(dev) + REG_LSR * UART_REG_ADDR_INTERVAL)
|
|
|
|
#define MSR(dev) (get_port(dev) + REG_MSR * UART_REG_ADDR_INTERVAL)
|
|
|
|
#define DLF(dev) (get_port(dev) + REG_DLF)
|
|
|
|
#define PCP(dev) (get_port(dev) + REG_PCP)
|
2016-10-11 09:44:22 +02:00
|
|
|
|
|
|
|
#define IIRC(dev) (DEV_DATA(dev)->iir_cache)
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-03-27 12:03:59 +01:00
|
|
|
#if DT_INST_NODE_HAS_PROP(0, reg_shift)
|
|
|
|
#define UART_REG_ADDR_INTERVAL (1<<DT_INST_PROP(0, reg_shift))
|
2019-02-06 23:14:14 +01:00
|
|
|
#endif
|
|
|
|
|
2016-03-29 20:01:11 +02:00
|
|
|
#ifdef UART_NS16550_ACCESS_IOPORT
|
2015-09-02 16:04:06 +02:00
|
|
|
#define INBYTE(x) sys_in8(x)
|
2019-02-24 00:18:28 +01:00
|
|
|
#define INWORD(x) sys_in32(x)
|
2015-09-02 16:04:06 +02:00
|
|
|
#define OUTBYTE(x, d) sys_out8(d, x)
|
2019-02-24 00:18:28 +01:00
|
|
|
#define OUTWORD(x, d) sys_out32(d, x)
|
2019-01-29 07:25:56 +01:00
|
|
|
#ifndef UART_REG_ADDR_INTERVAL
|
|
|
|
#define UART_REG_ADDR_INTERVAL 1 /* address diff of adjacent regs. */
|
2019-02-06 23:14:14 +01:00
|
|
|
#endif /* UART_REG_ADDR_INTERVAL */
|
2016-03-29 20:01:11 +02:00
|
|
|
#else
|
2015-09-02 16:04:06 +02:00
|
|
|
#define INBYTE(x) sys_read8(x)
|
2019-02-24 00:18:28 +01:00
|
|
|
#define INWORD(x) sys_read32(x)
|
2015-09-02 16:04:06 +02:00
|
|
|
#define OUTBYTE(x, d) sys_write8(d, x)
|
2019-02-24 00:18:28 +01:00
|
|
|
#define OUTWORD(x, d) sys_write32(d, x)
|
2019-02-06 23:14:14 +01:00
|
|
|
#ifndef UART_REG_ADDR_INTERVAL
|
2015-12-01 17:42:19 +01:00
|
|
|
#define UART_REG_ADDR_INTERVAL 4 /* address diff of adjacent regs. */
|
2019-02-06 23:14:14 +01:00
|
|
|
#endif
|
2016-03-29 20:01:11 +02:00
|
|
|
#endif /* UART_NS16550_ACCESS_IOPORT */
|
2015-12-01 17:42:19 +01:00
|
|
|
|
2019-05-29 08:58:02 +02:00
|
|
|
#ifdef CONFIG_UART_NS16550_ACCESS_WORD_ONLY
|
|
|
|
#undef INBYTE
|
|
|
|
#define INBYTE(x) INWORD(x)
|
|
|
|
#undef OUTBYTE
|
|
|
|
#define OUTBYTE(x, d) OUTWORD(x, d)
|
|
|
|
#endif
|
|
|
|
|
2020-01-04 00:22:47 +01:00
|
|
|
/* device config */
|
2016-10-11 09:44:22 +02:00
|
|
|
struct uart_ns16550_device_config {
|
2020-01-04 00:22:47 +01:00
|
|
|
struct uart_device_config devconf;
|
2020-05-15 02:47:27 +02:00
|
|
|
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
#ifdef UART_NS16550_PCP_ENABLED
|
2019-02-24 00:18:28 +01:00
|
|
|
u32_t pcp;
|
|
|
|
#endif
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
|
|
|
|
#ifdef UART_NS16550_PCIE_ENABLED
|
|
|
|
bool pcie;
|
|
|
|
pcie_bdf_t pcie_bdf;
|
|
|
|
pcie_id_t pcie_id;
|
|
|
|
#endif
|
2016-10-11 09:44:22 +02:00
|
|
|
};
|
|
|
|
|
2015-12-01 17:42:19 +01:00
|
|
|
/** Device data structure */
|
|
|
|
struct uart_ns16550_dev_data_t {
|
2020-05-15 02:47:27 +02:00
|
|
|
#ifdef UART_NS16550_PCIE_ENABLED
|
|
|
|
struct uart_device_config devconf;
|
|
|
|
#endif
|
2020-01-04 00:22:47 +01:00
|
|
|
struct uart_config uart_config;
|
2020-03-23 17:31:15 +01:00
|
|
|
struct k_spinlock lock;
|
2016-01-06 18:17:03 +01:00
|
|
|
|
2016-03-03 19:14:49 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2017-04-21 17:03:20 +02:00
|
|
|
u8_t iir_cache; /**< cache of IIR since it clears when read */
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
uart_irq_callback_user_data_t cb; /**< Callback function pointer */
|
2018-07-16 20:12:26 +02:00
|
|
|
void *cb_data; /**< Callback function arg */
|
2016-03-03 19:14:49 +01:00
|
|
|
#endif
|
|
|
|
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
#ifdef UART_NS16550_DLF_ENABLED
|
2017-04-21 17:03:20 +02:00
|
|
|
u8_t dlf; /**< DLF value */
|
2016-03-03 19:14:49 +01:00
|
|
|
#endif
|
2015-12-01 17:42:19 +01:00
|
|
|
};
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2016-10-24 09:37:56 +02:00
|
|
|
static const struct uart_driver_api uart_ns16550_driver_api;
|
2015-08-13 18:51:10 +02:00
|
|
|
|
2020-05-15 02:47:27 +02:00
|
|
|
static inline u32_t get_port(struct device *dev)
|
|
|
|
{
|
|
|
|
#ifdef UART_NS16550_PCIE_ENABLED
|
|
|
|
if (DEV_CFG(dev)->pcie) {
|
|
|
|
return DEV_DATA(dev)->devconf.port;
|
|
|
|
}
|
|
|
|
#endif /* UART_NS16550_PCIE_ENABLED */
|
|
|
|
|
|
|
|
return DEV_CFG(dev)->devconf.port;
|
|
|
|
}
|
|
|
|
|
2017-04-21 17:03:20 +02:00
|
|
|
static void set_baud_rate(struct device *dev, u32_t baud_rate)
|
2016-01-06 18:17:03 +01:00
|
|
|
{
|
2016-10-11 09:44:22 +02:00
|
|
|
const struct uart_ns16550_device_config * const dev_cfg = DEV_CFG(dev);
|
2016-01-06 18:17:03 +01:00
|
|
|
struct uart_ns16550_dev_data_t * const dev_data = DEV_DATA(dev);
|
2017-04-21 17:03:20 +02:00
|
|
|
u32_t divisor; /* baud rate divisor */
|
|
|
|
u8_t lcr_cache;
|
2016-01-06 18:17:03 +01:00
|
|
|
|
2020-01-04 00:22:47 +01:00
|
|
|
if ((baud_rate != 0U) && (dev_cfg->devconf.sys_clk_freq != 0U)) {
|
2019-01-29 07:25:56 +01:00
|
|
|
/*
|
|
|
|
* calculate baud rate divisor. a variant of
|
|
|
|
* (u32_t)(dev_cfg->sys_clk_freq / (16.0 * baud_rate) + 0.5)
|
|
|
|
*/
|
2020-01-04 00:22:47 +01:00
|
|
|
divisor = ((dev_cfg->devconf.sys_clk_freq + (baud_rate << 3))
|
2019-01-29 07:25:56 +01:00
|
|
|
/ baud_rate) >> 4;
|
2016-01-06 18:17:03 +01:00
|
|
|
|
|
|
|
/* set the DLAB to access the baud rate divisor registers */
|
2016-06-20 11:02:36 +02:00
|
|
|
lcr_cache = INBYTE(LCR(dev));
|
2017-08-17 18:59:40 +02:00
|
|
|
OUTBYTE(LCR(dev), LCR_DLAB | lcr_cache);
|
2016-01-06 18:17:03 +01:00
|
|
|
OUTBYTE(BRDL(dev), (unsigned char)(divisor & 0xff));
|
|
|
|
OUTBYTE(BRDH(dev), (unsigned char)((divisor >> 8) & 0xff));
|
|
|
|
|
2016-06-20 11:02:36 +02:00
|
|
|
/* restore the DLAB to access the baud rate divisor registers */
|
|
|
|
OUTBYTE(LCR(dev), lcr_cache);
|
|
|
|
|
2020-01-04 00:22:47 +01:00
|
|
|
dev_data->uart_config.baudrate = baud_rate;
|
2016-01-06 18:17:03 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-04 00:22:47 +01:00
|
|
|
static int uart_ns16550_configure(struct device *dev,
|
|
|
|
const struct uart_config *cfg)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2015-12-01 17:42:19 +01:00
|
|
|
struct uart_ns16550_dev_data_t * const dev_data = DEV_DATA(dev);
|
2020-05-19 22:31:19 +02:00
|
|
|
const struct uart_ns16550_device_config * const dev_cfg = DEV_CFG(dev);
|
2015-08-05 21:13:36 +02:00
|
|
|
|
2018-11-29 20:12:22 +01:00
|
|
|
u8_t mdc = 0U;
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
/* temp for return value if error occurs in this locked region */
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
|
|
|
|
2020-03-09 15:37:20 +01:00
|
|
|
ARG_UNUSED(dev_data);
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
ARG_UNUSED(dev_cfg);
|
|
|
|
|
|
|
|
#ifdef UART_NS16550_PCIE_ENABLED
|
|
|
|
if (dev_cfg->pcie) {
|
|
|
|
if (!pcie_probe(dev_cfg->pcie_bdf, dev_cfg->pcie_id)) {
|
2020-03-23 17:31:15 +01:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
}
|
|
|
|
|
2020-05-15 02:47:27 +02:00
|
|
|
dev_data->devconf.port = pcie_get_mbar(dev_cfg->pcie_bdf, 0);
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
pcie_set_cmd(dev_cfg->pcie_bdf, PCIE_CONF_CMDSTAT_MEM, true);
|
2015-08-27 10:06:15 +02:00
|
|
|
}
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
#endif
|
2015-05-20 13:35:45 +02:00
|
|
|
|
2016-03-03 19:14:49 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2018-11-29 20:12:22 +01:00
|
|
|
dev_data->iir_cache = 0U;
|
2016-03-03 19:14:49 +01:00
|
|
|
#endif
|
2015-04-11 01:44:37 +02:00
|
|
|
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
#ifdef UART_NS16550_DLF_ENABLED
|
|
|
|
OUTBYTE(DLF(dev), dev_data->dlf);
|
2016-01-06 18:17:02 +01:00
|
|
|
#endif
|
|
|
|
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
#ifdef UART_NS16550_PCP_ENABLED
|
|
|
|
u32_t pcp = dev_cfg->pcp;
|
|
|
|
|
|
|
|
if (pcp) {
|
|
|
|
pcp |= PCP_EN;
|
|
|
|
OUTWORD(PCP(dev), pcp & ~PCP_UPDATE);
|
|
|
|
OUTWORD(PCP(dev), pcp | PCP_UPDATE);
|
|
|
|
}
|
2019-02-24 00:18:28 +01:00
|
|
|
#endif
|
|
|
|
|
2020-01-11 04:12:48 +01:00
|
|
|
set_baud_rate(dev, cfg->baudrate);
|
|
|
|
|
|
|
|
/* Local structure to hold temporary values to pass to OUTBYTE() */
|
|
|
|
struct uart_config uart_cfg;
|
|
|
|
|
|
|
|
switch (cfg->data_bits) {
|
|
|
|
case UART_CFG_DATA_BITS_5:
|
|
|
|
uart_cfg.data_bits = LCR_CS5;
|
|
|
|
break;
|
|
|
|
case UART_CFG_DATA_BITS_6:
|
|
|
|
uart_cfg.data_bits = LCR_CS6;
|
|
|
|
break;
|
|
|
|
case UART_CFG_DATA_BITS_7:
|
|
|
|
uart_cfg.data_bits = LCR_CS7;
|
|
|
|
break;
|
|
|
|
case UART_CFG_DATA_BITS_8:
|
|
|
|
uart_cfg.data_bits = LCR_CS8;
|
|
|
|
break;
|
|
|
|
default:
|
2020-03-23 17:31:15 +01:00
|
|
|
ret = -ENOTSUP;
|
|
|
|
goto out;
|
2020-01-11 04:12:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (cfg->stop_bits) {
|
|
|
|
case UART_CFG_STOP_BITS_1:
|
|
|
|
uart_cfg.stop_bits = LCR_1_STB;
|
|
|
|
break;
|
|
|
|
case UART_CFG_STOP_BITS_2:
|
|
|
|
uart_cfg.stop_bits = LCR_2_STB;
|
|
|
|
break;
|
|
|
|
default:
|
2020-03-23 17:31:15 +01:00
|
|
|
ret = -ENOTSUP;
|
|
|
|
goto out;
|
2020-01-11 04:12:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (cfg->parity) {
|
|
|
|
case UART_CFG_PARITY_NONE:
|
|
|
|
uart_cfg.parity = LCR_PDIS;
|
|
|
|
break;
|
|
|
|
case UART_CFG_PARITY_EVEN:
|
|
|
|
uart_cfg.parity = LCR_EPS;
|
|
|
|
break;
|
|
|
|
default:
|
2020-03-23 17:31:15 +01:00
|
|
|
ret = -ENOTSUP;
|
|
|
|
goto out;
|
2020-01-11 04:12:48 +01:00
|
|
|
}
|
2019-01-29 07:25:56 +01:00
|
|
|
|
2020-03-11 15:13:05 +01:00
|
|
|
dev_data->uart_config = *cfg;
|
|
|
|
|
2020-01-11 04:12:48 +01:00
|
|
|
/* data bits, stop bits, parity, clear DLAB */
|
|
|
|
OUTBYTE(LCR(dev),
|
|
|
|
uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity);
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2015-07-31 12:57:00 +02:00
|
|
|
mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
|
2020-03-03 21:25:52 +01:00
|
|
|
#ifdef CONFIG_UART_NS16750
|
|
|
|
if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
|
2015-07-31 12:57:00 +02:00
|
|
|
mdc |= MCR_AFCE;
|
2019-06-04 16:52:23 +02:00
|
|
|
}
|
2020-03-03 21:25:52 +01:00
|
|
|
#endif
|
2015-07-31 12:57:00 +02:00
|
|
|
|
|
|
|
OUTBYTE(MDC(dev), mdc);
|
2015-04-11 01:44:37 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Program FIFO: enabled, mode 0 (set for compatibility with quark),
|
|
|
|
* generate the interrupt at 8th byte
|
|
|
|
* Clear TX and RX FIFO
|
|
|
|
*/
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(FCR(dev),
|
2016-11-15 03:23:45 +01:00
|
|
|
FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR
|
|
|
|
#ifdef CONFIG_UART_NS16750
|
|
|
|
| FCR_FIFO_64
|
|
|
|
#endif
|
|
|
|
);
|
2015-04-11 01:44:37 +02:00
|
|
|
|
|
|
|
/* clear the port */
|
2015-08-05 21:13:36 +02:00
|
|
|
INBYTE(RDR(dev));
|
2015-04-11 01:44:37 +02:00
|
|
|
|
|
|
|
/* disable interrupts */
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(IER(dev), 0x00);
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
out:
|
|
|
|
k_spin_unlock(&dev_data->lock, key);
|
|
|
|
return ret;
|
2020-01-04 00:22:47 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static int uart_ns16550_config_get(struct device *dev, struct uart_config *cfg)
|
|
|
|
{
|
|
|
|
struct uart_ns16550_dev_data_t *data = DEV_DATA(dev);
|
|
|
|
|
|
|
|
cfg->baudrate = data->uart_config.baudrate;
|
2020-01-11 04:12:48 +01:00
|
|
|
cfg->parity = data->uart_config.parity;
|
|
|
|
cfg->stop_bits = data->uart_config.stop_bits;
|
|
|
|
cfg->data_bits = data->uart_config.data_bits;
|
|
|
|
cfg->flow_ctrl = data->uart_config.flow_ctrl;
|
|
|
|
|
2020-01-04 00:22:47 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Initialize individual UART port
|
|
|
|
*
|
|
|
|
* This routine is called to reset the chip in a quiescent state.
|
|
|
|
*
|
|
|
|
* @param dev UART device struct
|
|
|
|
*
|
|
|
|
* @return 0 if successful, failed otherwise
|
|
|
|
*/
|
|
|
|
static int uart_ns16550_init(struct device *dev)
|
|
|
|
{
|
2020-05-14 02:08:02 +02:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = uart_ns16550_configure(dev, &DEV_DATA(dev)->uart_config);
|
|
|
|
if (ret != 0) {
|
|
|
|
return ret;
|
|
|
|
}
|
2020-01-04 00:22:47 +01:00
|
|
|
|
2016-03-03 19:14:50 +01:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2020-01-04 00:22:47 +01:00
|
|
|
DEV_CFG(dev)->devconf.irq_config_func(dev);
|
2016-03-03 19:14:50 +01:00
|
|
|
#endif
|
|
|
|
|
2016-03-09 18:01:20 +01:00
|
|
|
return 0;
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Poll the device for input.
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-20 23:58:45 +02:00
|
|
|
* @param c Pointer to character
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return 0 if a character arrived, -1 if the input buffer if empty.
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static int uart_ns16550_poll_in(struct device *dev, unsigned char *c)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
int ret = -1;
|
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
|
|
|
|
if ((INBYTE(LSR(dev)) & LSR_RXRDY) != 0) {
|
|
|
|
/* got a character */
|
|
|
|
*c = INBYTE(RDR(dev));
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((INBYTE(LSR(dev)) & LSR_RXRDY) != 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
2019-06-04 16:52:23 +02:00
|
|
|
}
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
return ret;
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Output a character in polled mode.
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
|
|
|
* Checks if the transmitter is empty. If empty, a character is written to
|
|
|
|
* the data register.
|
|
|
|
*
|
|
|
|
* If the hardware flow control is enabled then the handshake signal CTS has to
|
|
|
|
* be asserted in order to send a character.
|
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-20 23:58:45 +02:00
|
|
|
* @param c Character to send
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2018-11-27 01:43:46 +01:00
|
|
|
static void uart_ns16550_poll_out(struct device *dev,
|
2015-08-20 23:58:45 +02:00
|
|
|
unsigned char c)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
/* wait for transmitter to ready to accept a character */
|
|
|
|
if ((INBYTE(LSR(dev)) & LSR_THRE) == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
OUTBYTE(THR(dev), c);
|
|
|
|
|
|
|
|
break;
|
2019-06-04 16:52:23 +02:00
|
|
|
}
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2016-01-18 14:43:51 +01:00
|
|
|
/**
|
|
|
|
* @brief Check if an error was received
|
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2016-01-18 14:43:51 +01:00
|
|
|
*
|
|
|
|
* @return one of UART_ERROR_OVERRUN, UART_ERROR_PARITY, UART_ERROR_FRAMING,
|
2019-11-02 16:19:17 +01:00
|
|
|
* UART_BREAK if an error was detected, 0 otherwise.
|
2016-01-18 14:43:51 +01:00
|
|
|
*/
|
|
|
|
static int uart_ns16550_err_check(struct device *dev)
|
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
int check = (INBYTE(LSR(dev)) & LSR_EOB_MASK);
|
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
|
|
|
return check >> 1;
|
2016-01-18 14:43:51 +01:00
|
|
|
}
|
|
|
|
|
2015-04-21 19:09:15 +02:00
|
|
|
#if CONFIG_UART_INTERRUPT_DRIVEN
|
2015-08-21 00:10:21 +02:00
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Fill FIFO with data
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-20 23:58:45 +02:00
|
|
|
* @param tx_data Data to transmit
|
2015-08-05 21:13:36 +02:00
|
|
|
* @param size Number of bytes to send
|
|
|
|
*
|
2015-08-21 00:10:21 +02:00
|
|
|
* @return Number of bytes sent
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2017-04-21 17:03:20 +02:00
|
|
|
static int uart_ns16550_fifo_fill(struct device *dev, const u8_t *tx_data,
|
2015-08-20 23:58:45 +02:00
|
|
|
int size)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
|
|
|
int i;
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
2015-04-15 00:15:52 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
for (i = 0; (i < size) && (INBYTE(LSR(dev)) & LSR_THRE) != 0; i++) {
|
2015-08-20 23:58:45 +02:00
|
|
|
OUTBYTE(THR(dev), tx_data[i]);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
2015-04-11 01:44:37 +02:00
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Read data from FIFO
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
* @param rxData Data container
|
|
|
|
* @param size Container size
|
|
|
|
*
|
|
|
|
* @return Number of bytes read
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2017-04-21 17:03:20 +02:00
|
|
|
static int uart_ns16550_fifo_read(struct device *dev, u8_t *rx_data,
|
2015-08-20 23:58:45 +02:00
|
|
|
const int size)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
|
|
|
int i;
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
2015-04-15 00:15:52 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
for (i = 0; (i < size) && (INBYTE(LSR(dev)) & LSR_RXRDY) != 0; i++) {
|
2015-08-20 23:58:45 +02:00
|
|
|
rx_data[i] = INBYTE(RDR(dev));
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
2015-04-11 01:44:37 +02:00
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Enable TX interrupt in IER
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return N/A
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static void uart_ns16550_irq_tx_enable(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(IER(dev), INBYTE(IER(dev)) | IER_TBE);
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Disable TX interrupt in IER
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return N/A
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static void uart_ns16550_irq_tx_disable(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(IER(dev), INBYTE(IER(dev)) & (~IER_TBE));
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Check if Tx IRQ has been raised
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-08-13 18:51:10 +02:00
|
|
|
* @return 1 if an IRQ is ready, 0 otherwise
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static int uart_ns16550_irq_tx_ready(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
|
|
|
int ret = ((IIRC(dev) & IIR_ID) == IIR_THRE) ? 1 : 0;
|
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
|
|
|
return ret;
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2016-01-18 14:16:33 +01:00
|
|
|
/**
|
|
|
|
* @brief Check if nothing remains to be transmitted
|
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2016-01-18 14:16:33 +01:00
|
|
|
*
|
|
|
|
* @return 1 if nothing remains to be transmitted, 0 otherwise
|
|
|
|
*/
|
2017-05-11 16:57:29 +02:00
|
|
|
static int uart_ns16550_irq_tx_complete(struct device *dev)
|
2016-01-18 14:16:33 +01:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
|
|
|
int ret = ((INBYTE(LSR(dev)) & (LSR_TEMT | LSR_THRE))
|
|
|
|
== (LSR_TEMT | LSR_THRE)) ? 1 : 0;
|
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
|
|
|
return ret;
|
2016-01-18 14:16:33 +01:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Enable RX interrupt in IER
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return N/A
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static void uart_ns16550_irq_rx_enable(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(IER(dev), INBYTE(IER(dev)) | IER_RXRDY);
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Disable RX interrupt in IER
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return N/A
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static void uart_ns16550_irq_rx_disable(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(IER(dev), INBYTE(IER(dev)) & (~IER_RXRDY));
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Check if Rx IRQ has been raised
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return 1 if an IRQ is ready, 0 otherwise
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static int uart_ns16550_irq_rx_ready(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
|
|
|
int ret = ((IIRC(dev) & IIR_ID) == IIR_RBRF) ? 1 : 0;
|
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
|
|
|
return ret;
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Enable error interrupt in IER
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return N/A
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static void uart_ns16550_irq_err_enable(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(IER(dev), INBYTE(IER(dev)) | IER_LSR);
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Disable error interrupt in IER
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return 1 if an IRQ is ready, 0 otherwise
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static void uart_ns16550_irq_err_disable(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
2015-08-05 21:13:36 +02:00
|
|
|
OUTBYTE(IER(dev), INBYTE(IER(dev)) & (~IER_LSR));
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Check if any IRQ is pending
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-07-01 23:29:04 +02:00
|
|
|
* @return 1 if an IRQ is pending, 0 otherwise
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static int uart_ns16550_irq_is_pending(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
|
|
|
int ret = (!(IIRC(dev) & IIR_NIP)) ? 1 : 0;
|
|
|
|
|
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
|
|
|
return ret;
|
2015-04-11 01:44:37 +02:00
|
|
|
}
|
|
|
|
|
2015-07-01 23:22:39 +02:00
|
|
|
/**
|
2015-07-01 23:51:40 +02:00
|
|
|
* @brief Update cached contents of IIR
|
2015-07-01 23:22:39 +02:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2015-08-05 21:13:36 +02:00
|
|
|
*
|
2015-08-21 00:10:21 +02:00
|
|
|
* @return Always 1
|
2015-07-01 23:22:39 +02:00
|
|
|
*/
|
2015-12-01 17:42:19 +01:00
|
|
|
static int uart_ns16550_irq_update(struct device *dev)
|
2015-04-11 01:44:37 +02:00
|
|
|
{
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&DEV_DATA(dev)->lock);
|
|
|
|
|
2015-08-05 21:13:36 +02:00
|
|
|
IIRC(dev) = INBYTE(IIR(dev));
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
|
|
|
|
2015-04-11 01:44:37 +02:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2016-03-03 19:14:50 +01:00
|
|
|
/**
|
|
|
|
* @brief Set the callback function pointer for IRQ.
|
|
|
|
*
|
|
|
|
* @param dev UART device struct
|
|
|
|
* @param cb Callback function pointer.
|
|
|
|
*
|
|
|
|
* @return N/A
|
|
|
|
*/
|
|
|
|
static void uart_ns16550_irq_callback_set(struct device *dev,
|
2018-07-16 20:12:26 +02:00
|
|
|
uart_irq_callback_user_data_t cb,
|
|
|
|
void *cb_data)
|
2016-03-03 19:14:50 +01:00
|
|
|
{
|
|
|
|
struct uart_ns16550_dev_data_t * const dev_data = DEV_DATA(dev);
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
2016-03-03 19:14:50 +01:00
|
|
|
|
|
|
|
dev_data->cb = cb;
|
2018-07-16 20:12:26 +02:00
|
|
|
dev_data->cb_data = cb_data;
|
2020-03-23 17:31:15 +01:00
|
|
|
|
|
|
|
k_spin_unlock(&dev_data->lock, key);
|
2016-03-03 19:14:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Interrupt service routine.
|
|
|
|
*
|
|
|
|
* This simply calls the callback function, if one exists.
|
|
|
|
*
|
|
|
|
* @param arg Argument to ISR.
|
|
|
|
*
|
|
|
|
* @return N/A
|
|
|
|
*/
|
|
|
|
static void uart_ns16550_isr(void *arg)
|
|
|
|
{
|
|
|
|
struct device *dev = arg;
|
|
|
|
struct uart_ns16550_dev_data_t * const dev_data = DEV_DATA(dev);
|
|
|
|
|
|
|
|
if (dev_data->cb) {
|
2018-07-16 20:12:26 +02:00
|
|
|
dev_data->cb(dev_data->cb_data);
|
2016-03-03 19:14:50 +01:00
|
|
|
}
|
2020-03-23 17:31:15 +01:00
|
|
|
|
2016-03-03 19:14:50 +01:00
|
|
|
}
|
|
|
|
|
2015-04-21 19:09:15 +02:00
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
2015-08-13 18:51:10 +02:00
|
|
|
|
2016-01-06 18:17:03 +01:00
|
|
|
#ifdef CONFIG_UART_NS16550_LINE_CTRL
|
|
|
|
|
|
|
|
/**
|
2016-01-18 14:42:11 +01:00
|
|
|
* @brief Manipulate line control for UART.
|
2016-01-06 18:17:03 +01:00
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2016-01-06 18:17:03 +01:00
|
|
|
* @param ctrl The line control to be manipulated
|
|
|
|
* @param val Value to set the line control
|
|
|
|
*
|
2016-03-09 18:01:20 +01:00
|
|
|
* @return 0 if successful, failed otherwise
|
2016-01-06 18:17:03 +01:00
|
|
|
*/
|
|
|
|
static int uart_ns16550_line_ctrl_set(struct device *dev,
|
2017-04-21 17:03:20 +02:00
|
|
|
u32_t ctrl, u32_t val)
|
2016-01-06 18:17:03 +01:00
|
|
|
{
|
2017-04-21 17:03:20 +02:00
|
|
|
u32_t mdc, chg;
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key;
|
2016-01-06 18:17:03 +01:00
|
|
|
|
|
|
|
switch (ctrl) {
|
2019-11-02 16:19:17 +01:00
|
|
|
case UART_LINE_CTRL_BAUD_RATE:
|
2016-01-06 18:17:03 +01:00
|
|
|
set_baud_rate(dev, val);
|
2016-03-09 18:01:20 +01:00
|
|
|
return 0;
|
2016-01-06 18:17:03 +01:00
|
|
|
|
2019-11-02 16:19:17 +01:00
|
|
|
case UART_LINE_CTRL_RTS:
|
|
|
|
case UART_LINE_CTRL_DTR:
|
2020-03-23 17:31:15 +01:00
|
|
|
key = k_spin_lock(&DEV_DATA(dev)->lock);
|
2016-01-06 18:17:03 +01:00
|
|
|
mdc = INBYTE(MDC(dev));
|
|
|
|
|
2019-11-02 16:19:17 +01:00
|
|
|
if (ctrl == UART_LINE_CTRL_RTS) {
|
2016-01-06 18:17:03 +01:00
|
|
|
chg = MCR_RTS;
|
|
|
|
} else {
|
|
|
|
chg = MCR_DTR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (val) {
|
|
|
|
mdc |= chg;
|
|
|
|
} else {
|
|
|
|
mdc &= ~(chg);
|
|
|
|
}
|
|
|
|
OUTBYTE(MDC(dev), mdc);
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spin_unlock(&DEV_DATA(dev)->lock, key);
|
2016-03-09 18:01:20 +01:00
|
|
|
return 0;
|
2016-01-06 18:17:03 +01:00
|
|
|
}
|
|
|
|
|
2016-03-09 18:54:42 +01:00
|
|
|
return -ENOTSUP;
|
2016-01-06 18:17:03 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_UART_NS16550_LINE_CTRL */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_NS16550_DRV_CMD
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Send extra command to driver
|
|
|
|
*
|
2016-01-26 21:32:06 +01:00
|
|
|
* @param dev UART device struct
|
2016-01-06 18:17:03 +01:00
|
|
|
* @param cmd Command to driver
|
|
|
|
* @param p Parameter to the command
|
|
|
|
*
|
2016-03-09 18:01:20 +01:00
|
|
|
* @return 0 if successful, failed otherwise
|
2016-01-06 18:17:03 +01:00
|
|
|
*/
|
2017-04-21 17:03:20 +02:00
|
|
|
static int uart_ns16550_drv_cmd(struct device *dev, u32_t cmd, u32_t p)
|
2016-01-06 18:17:03 +01:00
|
|
|
{
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
#ifdef UART_NS16550_DLF_ENABLED
|
2020-01-22 23:15:18 +01:00
|
|
|
if (cmd == CMD_SET_DLF) {
|
|
|
|
struct uart_ns16550_dev_data_t * const dev_data = DEV_DATA(dev);
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
|
|
|
|
uart/ns16550, drivers/pcie: add PCI(e) support
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-04-02 19:06:07 +02:00
|
|
|
dev_data->dlf = p;
|
|
|
|
OUTBYTE(DLF(dev), dev_data->dlf);
|
2020-03-23 17:31:15 +01:00
|
|
|
k_spin_unlock(&dev_data->lock, key);
|
2016-03-09 18:01:20 +01:00
|
|
|
return 0;
|
2016-01-06 18:17:03 +01:00
|
|
|
}
|
2020-01-22 23:15:18 +01:00
|
|
|
#endif
|
2016-01-06 18:17:03 +01:00
|
|
|
|
2016-03-09 18:54:42 +01:00
|
|
|
return -ENOTSUP;
|
2016-01-06 18:17:03 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_UART_NS16550_DRV_CMD */
|
|
|
|
|
2015-08-13 18:51:10 +02:00
|
|
|
|
2016-10-24 09:37:56 +02:00
|
|
|
static const struct uart_driver_api uart_ns16550_driver_api = {
|
2015-12-01 17:42:19 +01:00
|
|
|
.poll_in = uart_ns16550_poll_in,
|
|
|
|
.poll_out = uart_ns16550_poll_out,
|
2016-01-18 14:43:51 +01:00
|
|
|
.err_check = uart_ns16550_err_check,
|
2020-01-04 00:22:47 +01:00
|
|
|
.configure = uart_ns16550_configure,
|
|
|
|
.config_get = uart_ns16550_config_get,
|
2015-08-13 18:51:10 +02:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
|
|
|
2015-12-01 17:42:19 +01:00
|
|
|
.fifo_fill = uart_ns16550_fifo_fill,
|
|
|
|
.fifo_read = uart_ns16550_fifo_read,
|
|
|
|
.irq_tx_enable = uart_ns16550_irq_tx_enable,
|
|
|
|
.irq_tx_disable = uart_ns16550_irq_tx_disable,
|
|
|
|
.irq_tx_ready = uart_ns16550_irq_tx_ready,
|
2017-05-11 16:57:29 +02:00
|
|
|
.irq_tx_complete = uart_ns16550_irq_tx_complete,
|
2015-12-01 17:42:19 +01:00
|
|
|
.irq_rx_enable = uart_ns16550_irq_rx_enable,
|
|
|
|
.irq_rx_disable = uart_ns16550_irq_rx_disable,
|
|
|
|
.irq_rx_ready = uart_ns16550_irq_rx_ready,
|
|
|
|
.irq_err_enable = uart_ns16550_irq_err_enable,
|
|
|
|
.irq_err_disable = uart_ns16550_irq_err_disable,
|
|
|
|
.irq_is_pending = uart_ns16550_irq_is_pending,
|
|
|
|
.irq_update = uart_ns16550_irq_update,
|
2016-03-03 19:14:50 +01:00
|
|
|
.irq_callback_set = uart_ns16550_irq_callback_set,
|
2015-12-01 17:42:19 +01:00
|
|
|
|
|
|
|
#endif
|
2016-01-06 18:17:03 +01:00
|
|
|
|
|
|
|
#ifdef CONFIG_UART_NS16550_LINE_CTRL
|
|
|
|
.line_ctrl_set = uart_ns16550_line_ctrl_set,
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_UART_NS16550_DRV_CMD
|
|
|
|
.drv_cmd = uart_ns16550_drv_cmd,
|
|
|
|
#endif
|
2015-12-01 17:42:19 +01:00
|
|
|
};
|
|
|
|
|
2019-05-01 20:44:01 +02:00
|
|
|
#include <uart_ns16550_port_0.h>
|
|
|
|
#include <uart_ns16550_port_1.h>
|
|
|
|
#include <uart_ns16550_port_2.h>
|
|
|
|
#include <uart_ns16550_port_3.h>
|