drivers: uart: ns16550: move from hard-coded to configurable
The NS16550 UART driver is currently hard-coded as 8-n-1 with no flow control. The baud rate is set by what is in DTS. This commit moves away from hard-coded and strictly DTS to configurable using the UART configure API. Requires commit #bcb807. Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
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parent
3a34db8501
commit
68a235932f
1 changed files with 56 additions and 12 deletions
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@ -199,7 +199,7 @@ BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct uart_ns16550_device_config * const) \
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((struct uart_ns16550_device_config * const) \
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(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct uart_ns16550_dev_data_t *)(dev)->driver_data)
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@ -315,7 +315,7 @@ static int uart_ns16550_configure(struct device *dev,
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const struct uart_config *cfg)
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{
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struct uart_ns16550_dev_data_t * const dev_data = DEV_DATA(dev);
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const struct uart_ns16550_device_config * const dev_cfg = DEV_CFG(dev);
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struct uart_ns16550_device_config * const dev_cfg = DEV_CFG(dev);
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unsigned int old_level; /* old interrupt lock level */
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u8_t mdc = 0U;
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@ -328,7 +328,7 @@ static int uart_ns16550_configure(struct device *dev,
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return -EINVAL;
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}
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dev_data->port = pcie_get_mbar(dev_cfg->pcie_bdf, 0);
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dev_cfg->devconf.port = pcie_get_mbar(dev_cfg->pcie_bdf, 0);
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pcie_set_cmd(dev_cfg->pcie_bdf, PCIE_CONF_CMDSTAT_MEM, true);
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}
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#endif
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@ -353,10 +353,53 @@ static int uart_ns16550_configure(struct device *dev,
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}
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#endif
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set_baud_rate(dev, dev_data->uart_config.baudrate);
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set_baud_rate(dev, cfg->baudrate);
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/* 8 data bits, 1 stop bit, no parity, clear DLAB */
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OUTBYTE(LCR(dev), LCR_CS8 | LCR_1_STB | LCR_PDIS);
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/* Local structure to hold temporary values to pass to OUTBYTE() */
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struct uart_config uart_cfg;
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switch (cfg->data_bits) {
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case UART_CFG_DATA_BITS_5:
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uart_cfg.data_bits = LCR_CS5;
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break;
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case UART_CFG_DATA_BITS_6:
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uart_cfg.data_bits = LCR_CS6;
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break;
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case UART_CFG_DATA_BITS_7:
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uart_cfg.data_bits = LCR_CS7;
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break;
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case UART_CFG_DATA_BITS_8:
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uart_cfg.data_bits = LCR_CS8;
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break;
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default:
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return -ENOTSUP;
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}
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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uart_cfg.stop_bits = LCR_1_STB;
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break;
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case UART_CFG_STOP_BITS_2:
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uart_cfg.stop_bits = LCR_2_STB;
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break;
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default:
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return -ENOTSUP;
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}
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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uart_cfg.parity = LCR_PDIS;
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break;
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case UART_CFG_PARITY_EVEN:
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uart_cfg.parity = LCR_EPS;
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break;
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default:
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return -ENOTSUP;
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}
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/* data bits, stop bits, parity, clear DLAB */
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OUTBYTE(LCR(dev),
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uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity);
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mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
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if ((dev_data->options & UART_OPTION_AFCE) == UART_OPTION_AFCE) {
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@ -385,7 +428,7 @@ static int uart_ns16550_configure(struct device *dev,
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irq_unlock(old_level);
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return 0;
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return 0;
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};
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static int uart_ns16550_config_get(struct device *dev, struct uart_config *cfg)
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@ -393,10 +436,11 @@ static int uart_ns16550_config_get(struct device *dev, struct uart_config *cfg)
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struct uart_ns16550_dev_data_t *data = DEV_DATA(dev);
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cfg->baudrate = data->uart_config.baudrate;
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cfg->parity = UART_CFG_PARITY_NONE; /* use uart_config_parity */
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cfg->stop_bits = UART_CFG_STOP_BITS_1; /* use uart_config_stop_bits */
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cfg->data_bits = UART_CFG_DATA_BITS_8; /* use uart_config_data_bits */
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_NONE;/* use uart_config_flow_control */
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cfg->parity = data->uart_config.parity;
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cfg->stop_bits = data->uart_config.stop_bits;
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cfg->data_bits = data->uart_config.data_bits;
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cfg->flow_ctrl = data->uart_config.flow_ctrl;
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return 0;
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}
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@ -411,7 +455,7 @@ static int uart_ns16550_config_get(struct device *dev, struct uart_config *cfg)
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*/
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static int uart_ns16550_init(struct device *dev)
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{
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uart_ns16550_configure(dev, &DEV_DATA(dev)->uart_config);
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uart_ns16550_configure(dev, &DEV_DATA(dev)->uart_config);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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DEV_CFG(dev)->devconf.irq_config_func(dev);
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