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drivers: convert to using newly introduced integer sized types

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Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.

Jira: ZEP-2051

Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-21 10:03:20 -05:00
commit ccad5bf3e3
231 changed files with 3200 additions and 3200 deletions
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74
drivers/adc/adc_dw.c
View file

@ -52,10 +52,10 @@
static void adc_config_irq(void);
#ifdef CONFIG_ADC_DW_CALIBRATION
static void calibration_command(uint8_t command)
static void calibration_command(u8_t command)
{
uint32_t state;
uint32_t reg_value;
u32_t state;
u32_t reg_value;
state = irq_lock();
reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
@ -77,9 +77,9 @@ static void calibration_command(uint8_t command)
static void adc_goto_normal_mode(struct device *dev)
{
struct adc_info *info = dev->driver_data;
uint8_t calibration_value;
uint32_t reg_value;
uint32_t state;
u8_t calibration_value;
u32_t reg_value;
u32_t state;
reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
@ -119,8 +119,8 @@ static void adc_goto_normal_mode(struct device *dev)
#else
static void adc_goto_normal_mode(struct device *dev)
{
uint32_t reg_value;
uint32_t state;
u32_t reg_value;
u32_t state;
ARG_UNUSED(dev);
reg_value = sys_in32(
@ -159,8 +159,8 @@ static void adc_goto_normal_mode(struct device *dev)
static void adc_goto_deep_power_down(void)
{
uint32_t reg_value;
uint32_t state;
u32_t reg_value;
u32_t state;
reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
if ((reg_value & 0xE >> 1) != 0) {
@ -182,10 +182,10 @@ static void adc_goto_deep_power_down(void)
static void adc_dw_enable(struct device *dev)
{
uint32_t reg_value;
u32_t reg_value;
struct adc_info *info = dev->driver_data;
const struct adc_config *config = dev->config->config_info;
uint32_t adc_base = config->reg_base;
u32_t adc_base = config->reg_base;
/*Go to Normal Mode*/
sys_out32(ADC_INT_DSB|ENABLE_ADC, adc_base + ADC_CTRL);
@ -202,10 +202,10 @@ static void adc_dw_enable(struct device *dev)
static void adc_dw_disable(struct device *dev)
{
uint32_t saved;
u32_t saved;
struct adc_info *info = dev->driver_data;
const struct adc_config *config = dev->config->config_info;
uint32_t adc_base = config->reg_base;
u32_t adc_base = config->reg_base;
sys_out32(ADC_INT_DSB|ENABLE_ADC, adc_base + ADC_CTRL);
adc_goto_deep_power_down();
@ -221,15 +221,15 @@ static void adc_dw_disable(struct device *dev)
static int adc_dw_read_request(struct device *dev, struct adc_seq_table *seq_tbl)
{
uint32_t i;
uint32_t ctrl;
uint32_t tmp_val;
uint32_t num_iters;
uint32_t saved;
u32_t i;
u32_t ctrl;
u32_t tmp_val;
u32_t num_iters;
u32_t saved;
struct adc_seq_entry *entry;
struct adc_info *info = dev->driver_data;
const struct adc_config *config = dev->config->config_info;
uint32_t adc_base = config->reg_base;
u32_t adc_base = config->reg_base;
if (info->state != ADC_STATE_IDLE) {
return 1;
@ -312,10 +312,10 @@ static struct adc_driver_api api_funcs = {
int adc_dw_init(struct device *dev)
{
uint32_t tmp_val;
uint32_t val;
u32_t tmp_val;
u32_t val;
const struct adc_config *config = dev->config->config_info;
uint32_t adc_base = config->reg_base;
u32_t adc_base = config->reg_base;
struct adc_info *info = dev->driver_data;
sys_out32(ADC_INT_DSB | ADC_CLK_ENABLE, adc_base + ADC_CTRL);
@ -353,17 +353,17 @@ static void adc_dw_rx_isr(void *arg)
struct device_config *dev_config = dev->config;
const struct adc_config *config = dev_config->config_info;
struct adc_info *info = dev->driver_data;
uint32_t adc_base = config->reg_base;
u32_t adc_base = config->reg_base;
struct adc_seq_entry *entries = info->entries;
uint32_t reg_val;
uint32_t seq_index;
u32_t reg_val;
u32_t seq_index;
for (seq_index = 0; seq_index < info->seq_size; seq_index++) {
uint32_t *adc_buffer;
u32_t *adc_buffer;
reg_val = sys_in32(adc_base + ADC_SET);
sys_out32(reg_val|ADC_POP_SAMPLE, adc_base + ADC_SET);
adc_buffer = (uint32_t *)entries[seq_index].buffer;
adc_buffer = (u32_t *)entries[seq_index].buffer;
*adc_buffer = sys_in32(adc_base + ADC_SAMPLE);
}
@ -386,15 +386,15 @@ static void adc_dw_rx_isr(void *arg)
struct device_config *dev_config = dev->config;
const struct adc_config *config = dev_config->config_info;
struct adc_info *info = dev->driver_data;
uint32_t adc_base = config->reg_base;
u32_t adc_base = config->reg_base;
struct adc_seq_entry *entries = info->entries;
uint32_t reg_val;
uint32_t sequence_index;
uint8_t full_buffer_flag = 0;
u32_t reg_val;
u32_t sequence_index;
u8_t full_buffer_flag = 0;
for (sequence_index = 0; sequence_index < info->seq_size; sequence_index++) {
uint32_t *adc_buffer;
uint32_t repetitive_index;
u32_t *adc_buffer;
u32_t repetitive_index;
repetitive_index = info->index[sequence_index];
/*API array is 8 bits array but ADC reads blocks of 32 bits with every sample.*/
@ -405,7 +405,7 @@ static void adc_dw_rx_isr(void *arg)
reg_val = sys_in32(adc_base + ADC_SET);
sys_out32(reg_val|ADC_POP_SAMPLE, adc_base + ADC_SET);
adc_buffer = (uint32_t *)entries[sequence_index].buffer;
adc_buffer = (u32_t *)entries[sequence_index].buffer;
adc_buffer[repetitive_index] = sys_in32(adc_base + ADC_SAMPLE);
repetitive_index++;
info->index[sequence_index] = repetitive_index;
@ -437,8 +437,8 @@ static void adc_dw_err_isr(void *arg)
struct device *dev = (struct device *) arg;
const struct adc_config *config = dev->config->config_info;
struct adc_info *info = dev->driver_data;
uint32_t adc_base = config->reg_base;
uint32_t reg_val = sys_in32(adc_base + ADC_SET);
u32_t adc_base = config->reg_base;
u32_t reg_val = sys_in32(adc_base + ADC_SET);
sys_out32(RESUME_ADC_CAPTURE, adc_base + ADC_CTRL);

30
drivers/adc/adc_dw.h
View file

@ -160,24 +160,24 @@ typedef void (*adc_dw_config_t)(void);
*/
struct adc_config {
/**Register base address for hardware registers.*/
uint32_t reg_base;
u32_t reg_base;
/**IIO address for the IRQ mask register.*/
uint32_t reg_irq_mask;
u32_t reg_irq_mask;
/**IIO address for the error mask register.*/
uint32_t reg_err_mask;
u32_t reg_err_mask;
/**Output mode*/
uint8_t out_mode;
u8_t out_mode;
/**Capture mode*/
uint8_t capture_mode;
u8_t capture_mode;
/**Sequence mode*/
uint8_t seq_mode;
u8_t seq_mode;
/**Serial delay*/
uint8_t serial_dly;
u8_t serial_dly;
/**Sample width*/
uint8_t sample_width;
uint8_t padding[3];
u8_t sample_width;
u8_t padding[3];
/**Clock ratio*/
uint32_t clock_ratio;
u32_t clock_ratio;
/**Config handler*/
adc_dw_config_t config_func;
};
@ -191,20 +191,20 @@ struct adc_info {
struct k_sem device_sync_sem;
#ifdef CONFIG_ADC_DW_REPETITIVE
/**Current reception buffer index*/
uint8_t index[BUFS_NUM];
u8_t index[BUFS_NUM];
#endif
/**Sequence entries' array*/
struct adc_seq_entry *entries;
/**State of execution of the driver*/
uint8_t state;
u8_t state;
/**Sequence size*/
uint8_t seq_size;
u8_t seq_size;
#ifdef CONFIG_ADC_DW_CALIBRATION
/**Calibration value*/
uint8_t calibration_value;
u8_t calibration_value;
#endif
#ifdef CONFIG_ADC_DW_DUMMY_CONVERSION
uint8_t dummy_conversion;
u8_t dummy_conversion;
#endif
};

20
drivers/adc/adc_qmsi_ss.c
View file

@ -31,7 +31,7 @@ struct adc_info {
struct k_sem device_sync_sem;
struct k_sem sem;
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
qm_ss_adc_context_t adc_ctx;
#endif
};
@ -239,14 +239,14 @@ static const struct adc_driver_api api_funcs = {
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void adc_qmsi_ss_set_power_state(struct device *dev,
uint32_t power_state)
u32_t power_state)
{
struct adc_info *context = dev->driver_data;
context->device_power_state = power_state;
}
static uint32_t adc_qmsi_ss_get_power_state(struct device *dev)
static u32_t adc_qmsi_ss_get_power_state(struct device *dev)
{
struct adc_info *context = dev->driver_data;
@ -275,17 +275,17 @@ static int adc_qmsi_ss_resume_device_from_suspend(struct device *dev)
return 0;
}
static int adc_qmsi_ss_device_ctrl(struct device *dev, uint32_t ctrl_command,
static int adc_qmsi_ss_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return adc_qmsi_ss_suspend_device(dev);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return adc_qmsi_ss_resume_device_from_suspend(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = adc_qmsi_ss_get_power_state(dev);
*((u32_t *)context) = adc_qmsi_ss_get_power_state(dev);
}
return 0;
@ -327,7 +327,7 @@ DEVICE_DEFINE(adc_qmsi_ss, CONFIG_ADC_0_NAME, &adc_qmsi_ss_init,
static void adc_config_irq(void)
{
uint32_t *scss_intmask;
u32_t *scss_intmask;
IRQ_CONNECT(IRQ_ADC_IRQ, CONFIG_ADC_0_IRQ_PRI,
adc_qmsi_ss_rx_isr, DEVICE_GET(adc_qmsi_ss), 0);
@ -338,9 +338,9 @@ static void adc_config_irq(void)
irq_enable(IRQ_ADC_ERR);
scss_intmask =
(uint32_t *)&QM_INTERRUPT_ROUTER->ss_adc_0_error_int_mask;
(u32_t *)&QM_INTERRUPT_ROUTER->ss_adc_0_error_int_mask;
*scss_intmask &= ~BIT(8);
scss_intmask = (uint32_t *)&QM_INTERRUPT_ROUTER->ss_adc_0_int_mask;
scss_intmask = (u32_t *)&QM_INTERRUPT_ROUTER->ss_adc_0_int_mask;
*scss_intmask &= ~BIT(8);
}

18
drivers/adc/adc_ti_adc108s102.c
View file

@ -24,7 +24,7 @@ static inline int _ti_adc108s102_sampling(struct device *dev)
SYS_LOG_DBG("Sampling!\n");
/* SPI deals with uint8_t buffers so multiplying by 2 the length */
/* SPI deals with u8_t buffers so multiplying by 2 the length */
return spi_transceive(adc->spi, adc->cmd_buffer,
adc->cmd_buf_len * 2,
adc->sampling_buffer,
@ -37,7 +37,7 @@ static inline void _ti_adc108s102_handle_result(struct device *dev)
struct adc_seq_table *seq_table = adc->seq_table;
struct ti_adc108s102_chan *chan;
struct adc_seq_entry *entry;
uint32_t s_i, i;
u32_t s_i, i;
SYS_LOG_DBG("_ti_adc108s102_handle_result()");
@ -49,20 +49,20 @@ static inline void _ti_adc108s102_handle_result(struct device *dev)
continue;
}
*((uint16_t *)(entry->buffer+chan->buf_idx)) =
*((u16_t *)(entry->buffer+chan->buf_idx)) =
ADC108S102_RESULT(adc->sampling_buffer[s_i]);
chan->buf_idx += 2;
}
}
static inline int32_t _ti_adc108s102_prepare(struct device *dev)
static inline s32_t _ti_adc108s102_prepare(struct device *dev)
{
struct ti_adc108s102_data *adc = dev->driver_data;
struct adc_seq_table *seq_table = adc->seq_table;
struct ti_adc108s102_chan *chan;
int32_t sampling_delay = 0;
uint32_t i;
s32_t sampling_delay = 0;
u32_t i;
adc->cmd_buf_len = 0;
adc->sampling_buf_len = 1; /* Counting the dummy byte */
@ -120,7 +120,7 @@ static void ti_adc108s102_disable(struct device *dev)
static inline int _verify_entries(struct adc_seq_table *seq_table)
{
struct adc_seq_entry *entry;
uint32_t chans_set = 0;
u32_t chans_set = 0;
int i;
for (i = 0; i < seq_table->num_entries; i++) {
@ -148,7 +148,7 @@ static int ti_adc108s102_read(struct device *dev,
struct ti_adc108s102_data *adc = dev->driver_data;
struct spi_config spi_conf;
int ret = 0;
int32_t delay;
s32_t delay;
spi_conf.config = config->spi_config_flags;
spi_conf.max_sys_freq = config->spi_freq;
@ -178,7 +178,7 @@ static int ti_adc108s102_read(struct device *dev,
}
/* convert to milliseconds */
delay = (int32_t)((MSEC_PER_SEC * (uint64_t)delay) /
delay = (s32_t)((MSEC_PER_SEC * (u64_t)delay) /
sys_clock_ticks_per_sec);
k_sleep(delay);

20
drivers/adc/adc_ti_adc108s102.h
View file

@ -25,7 +25,7 @@ extern "C" {
#define ADC108S102_SAMPLING_BUFFER_SIZE 9
#define ADC108S102_CHANNELS 8
#define ADC108S102_CHANNELS_SIZE \
(ADC108S102_CHANNELS * sizeof(uint32_t))
(ADC108S102_CHANNELS * sizeof(u32_t))
#define ADC108S102_CHANNEL_CMD(_channel_) \
sys_cpu_to_be16((_channel_ << 8) << 3)
#define ADC108S102_RESULT_MASK 0xfff /* 12 bits resolution */
@ -34,25 +34,25 @@ extern "C" {
struct ti_adc108s102_config {
const char *spi_port;
uint32_t spi_config_flags;
uint32_t spi_freq;
uint32_t spi_slave;
u32_t spi_config_flags;
u32_t spi_freq;
u32_t spi_slave;
};
struct ti_adc108s102_chan {
uint32_t buf_idx;
u32_t buf_idx;
};
struct ti_adc108s102_data {
uint16_t cmd_buffer[ADC108S102_CMD_BUFFER_SIZE];
uint16_t sampling_buffer[ADC108S102_SAMPLING_BUFFER_SIZE];
u16_t cmd_buffer[ADC108S102_CMD_BUFFER_SIZE];
u16_t sampling_buffer[ADC108S102_SAMPLING_BUFFER_SIZE];
struct device *spi;
struct ti_adc108s102_chan chans[ADC108S102_CHANNELS];
struct adc_seq_table *seq_table;
uint8_t cmd_buf_len;
uint8_t sampling_buf_len;
uint8_t stride[2];
u8_t cmd_buf_len;
u8_t sampling_buf_len;
u8_t stride[2];
};
#ifdef __cplusplus

14
drivers/aio/aio_comparator_qmsi.c
View file

@ -30,7 +30,7 @@ struct aio_qmsi_cmp_cb {
struct aio_qmsi_cmp_dev_data_t {
/** Number of total comparators */
uint8_t num_cmp;
u8_t num_cmp;
/** Callback for each comparator */
struct aio_qmsi_cmp_cb cb[AIO_QMSI_CMP_COUNT];
};
@ -40,7 +40,7 @@ static qm_ac_config_t config;
static int aio_cmp_config(struct device *dev);
static int aio_qmsi_cmp_disable(struct device *dev, uint8_t index)
static int aio_qmsi_cmp_disable(struct device *dev, u8_t index)
{
if (index >= AIO_QMSI_CMP_COUNT) {
return -EINVAL;
@ -62,7 +62,7 @@ static int aio_qmsi_cmp_disable(struct device *dev, uint8_t index)
return 0;
}
static int aio_qmsi_cmp_configure(struct device *dev, uint8_t index,
static int aio_qmsi_cmp_configure(struct device *dev, u8_t index,
enum aio_cmp_polarity polarity,
enum aio_cmp_ref refsel,
aio_cmp_cb cb, void *param)
@ -106,7 +106,7 @@ static int aio_qmsi_cmp_configure(struct device *dev, uint8_t index,
return 0;
}
static uint32_t aio_cmp_qmsi_get_pending_int(struct device *dev)
static u32_t aio_cmp_qmsi_get_pending_int(struct device *dev)
{
return QM_SCSS_CMP->cmp_stat_clr;
}
@ -119,7 +119,7 @@ static const struct aio_cmp_driver_api aio_cmp_funcs = {
static int aio_qmsi_cmp_init(struct device *dev)
{
uint8_t i;
u8_t i;
struct aio_qmsi_cmp_dev_data_t *dev_data =
(struct aio_qmsi_cmp_dev_data_t *)dev->driver_data;
@ -154,12 +154,12 @@ static int aio_qmsi_cmp_init(struct device *dev)
static void aio_qmsi_cmp_isr(void *data)
{
uint8_t i;
u8_t i;
struct device *dev = data;
struct aio_qmsi_cmp_dev_data_t *dev_data =
(struct aio_qmsi_cmp_dev_data_t *)dev->driver_data;
uint32_t int_status = QM_SCSS_CMP->cmp_stat_clr;
u32_t int_status = QM_SCSS_CMP->cmp_stat_clr;
for (i = 0; i < dev_data->num_cmp; i++) {
if (int_status & (1 << i)) {

46
drivers/clock_control/beetle_clock_control.c
View file

@ -21,15 +21,15 @@
struct beetle_clock_control_cfg_t {
/* Clock Control ID */
uint32_t clock_control_id;
u32_t clock_control_id;
/* Clock control freq */
uint32_t freq;
u32_t freq;
};
static inline void beetle_set_clock(volatile uint32_t *base,
uint8_t bit, enum arm_soc_state_t state)
static inline void beetle_set_clock(volatile u32_t *base,
u8_t bit, enum arm_soc_state_t state)
{
uint32_t key;
u32_t key;
key = irq_lock();
@ -50,31 +50,31 @@ static inline void beetle_set_clock(volatile uint32_t *base,
irq_unlock(key);
}
static inline void beetle_ahb_set_clock_on(uint8_t bit,
static inline void beetle_ahb_set_clock_on(u8_t bit,
enum arm_soc_state_t state)
{
beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->ahbclkcfg0set),
beetle_set_clock((volatile u32_t *)&(__BEETLE_SYSCON->ahbclkcfg0set),
bit, state);
}
static inline void beetle_ahb_set_clock_off(uint8_t bit,
static inline void beetle_ahb_set_clock_off(u8_t bit,
enum arm_soc_state_t state)
{
beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->ahbclkcfg0clr),
beetle_set_clock((volatile u32_t *)&(__BEETLE_SYSCON->ahbclkcfg0clr),
bit, state);
}
static inline void beetle_apb_set_clock_on(uint8_t bit,
static inline void beetle_apb_set_clock_on(u8_t bit,
enum arm_soc_state_t state)
{
beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->apbclkcfg0set),
beetle_set_clock((volatile u32_t *)&(__BEETLE_SYSCON->apbclkcfg0set),
bit, state);
}
static inline void beetle_apb_set_clock_off(uint8_t bit,
static inline void beetle_apb_set_clock_off(u8_t bit,
enum arm_soc_state_t state)
{
beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->apbclkcfg0clr),
beetle_set_clock((volatile u32_t *)&(__BEETLE_SYSCON->apbclkcfg0clr),
bit, state);
}
@ -84,7 +84,7 @@ static inline int beetle_clock_control_on(struct device *dev,
struct arm_clock_control_t *beetle_cc =
(struct arm_clock_control_t *)(sub_system);
uint8_t bit = 0;
u8_t bit = 0;
switch (beetle_cc->bus) {
case CMSDK_AHB:
@ -108,7 +108,7 @@ static inline int beetle_clock_control_off(struct device *dev,
struct arm_clock_control_t *beetle_cc =
(struct arm_clock_control_t *)(sub_system);
uint8_t bit = 0;
u8_t bit = 0;
switch (beetle_cc->bus) {
case CMSDK_AHB:
@ -127,12 +127,12 @@ static inline int beetle_clock_control_off(struct device *dev,
static int beetle_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
u32_t *rate)
{
#ifdef CONFIG_CLOCK_CONTROL_BEETLE_ENABLE_PLL
const struct beetle_clock_control_cfg_t * const cfg =
clock->config->config_info;
uint32_t nc_mainclk = beetle_round_freq(cfg->freq);
u32_t nc_mainclk = beetle_round_freq(cfg->freq);
*rate = nc_mainclk;
#else
@ -152,9 +152,9 @@ static const struct clock_control_driver_api beetle_clock_control_api = {
};
#ifdef CONFIG_CLOCK_CONTROL_BEETLE_ENABLE_PLL
static uint32_t beetle_round_freq(uint32_t mainclk)
static u32_t beetle_round_freq(u32_t mainclk)
{
uint32_t nc_mainclk = 0;
u32_t nc_mainclk = 0;
/*
* Verify that the frequency is in the supported range otherwise
@ -173,9 +173,9 @@ static uint32_t beetle_round_freq(uint32_t mainclk)
return nc_mainclk;
}
static uint32_t beetle_get_prescaler(uint32_t mainclk)
static u32_t beetle_get_prescaler(u32_t mainclk)
{
uint32_t pre_mainclk = 0;
u32_t pre_mainclk = 0;
/*
* Verify that the frequency is in the supported range otherwise
@ -194,10 +194,10 @@ static uint32_t beetle_get_prescaler(uint32_t mainclk)
return pre_mainclk;
}
static int beetle_pll_enable(uint32_t mainclk)
static int beetle_pll_enable(u32_t mainclk)
{
uint32_t pre_mainclk = beetle_get_prescaler(mainclk);
u32_t pre_mainclk = beetle_get_prescaler(mainclk);
/* Set PLLCTRL Register */
__BEETLE_SYSCON->pllctrl = BEETLE_PLL_CONFIGURATION;

16
drivers/clock_control/nrf5_power_clock.c
View file

@ -13,12 +13,12 @@
#include <misc/__assert.h>
#include <arch/arm/cortex_m/cmsis.h>
static uint8_t m16src_ref;
static uint8_t m16src_grd;
static u8_t m16src_ref;
static u8_t m16src_grd;
static int _m16src_start(struct device *dev, clock_control_subsys_t sub_system)
{
uint32_t imask;
u32_t imask;
bool blocking;
/* If the clock is already started then just increment refcount.
@ -48,7 +48,7 @@ static int _m16src_start(struct device *dev, clock_control_subsys_t sub_system)
/* If blocking then spin-wait in CPU sleep until 16MHz clock settles. */
blocking = POINTER_TO_UINT(sub_system);
if (blocking) {
uint32_t intenset;
u32_t intenset;
irq_disable(POWER_CLOCK_IRQn);
@ -98,7 +98,7 @@ hf_already_started:
static int _m16src_stop(struct device *dev, clock_control_subsys_t sub_system)
{
uint32_t imask;
u32_t imask;
ARG_UNUSED(sub_system);
@ -139,8 +139,8 @@ static int _m16src_stop(struct device *dev, clock_control_subsys_t sub_system)
static int _k32src_start(struct device *dev, clock_control_subsys_t sub_system)
{
uint32_t lf_clk_src;
uint32_t intenset;
u32_t lf_clk_src;
u32_t intenset;
/* TODO: implement the ref count and re-entrancy guard, if a use-case
* needs it.
@ -217,7 +217,7 @@ static int _k32src_start(struct device *dev, clock_control_subsys_t sub_system)
static void _power_clock_isr(void *arg)
{
uint8_t pof, hf_intenset, hf_stat, hf, lf, done, ctto;
u8_t pof, hf_intenset, hf_stat, hf, lf, done, ctto;
struct device *dev = arg;
pof = (NRF_POWER->EVENTS_POFWARN != 0);

6
drivers/clock_control/quark_se_clock_control.c
View file

@ -23,14 +23,14 @@
#include <logging/sys_log.h>
struct quark_se_clock_control_config {
uint32_t base_address;
u32_t base_address;
};
static inline int quark_se_clock_control_on(struct device *dev,
clock_control_subsys_t sub_system)
{
const struct quark_se_clock_control_config *info = dev->config->config_info;
uint32_t subsys = POINTER_TO_INT(sub_system);
u32_t subsys = POINTER_TO_INT(sub_system);
if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
SYS_LOG_DBG("Enabling all clock gates on dev %p", dev);
@ -48,7 +48,7 @@ static inline int quark_se_clock_control_off(struct device *dev,
clock_control_subsys_t sub_system)
{
const struct quark_se_clock_control_config *info = dev->config->config_info;
uint32_t subsys = POINTER_TO_INT(sub_system);
u32_t subsys = POINTER_TO_INT(sub_system);
if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
SYS_LOG_DBG("Disabling all clock gates on dev %p", dev);

10
drivers/clock_control/stm32_ll_clock.c
View file

@ -35,7 +35,7 @@ static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
CONFIG_CLOCK_STM32_APB2_PRESCALER);
}
static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
static u32_t get_bus_clock(u32_t clock, u32_t prescaler)
{
return clock / prescaler;
}
@ -108,7 +108,7 @@ static inline int stm32_clock_control_off(struct device *dev,
static int stm32_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
u32_t *rate)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
/*
@ -117,10 +117,10 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
* since it will be updated after clock configuration and hence
* more likely to contain actual clock speed
*/
uint32_t ahb_clock = SystemCoreClock;
uint32_t apb1_clock = get_bus_clock(ahb_clock,
u32_t ahb_clock = SystemCoreClock;
u32_t apb1_clock = get_bus_clock(ahb_clock,
CONFIG_CLOCK_STM32_APB1_PRESCALER);
uint32_t apb2_clock = get_bus_clock(ahb_clock,
u32_t apb2_clock = get_bus_clock(ahb_clock,
CONFIG_CLOCK_STM32_APB2_PRESCALER);
ARG_UNUSED(clock);

36
drivers/clock_control/stm32f107xx_clock.c
View file

@ -21,7 +21,7 @@
#include <clock_control/stm32_clock_control.h>
struct stm32f10x_rcc_data {
uint8_t *base;
u8_t *base;
};
static inline int stm32f10x_clock_control_on(struct device *dev,
@ -30,7 +30,7 @@ static inline int stm32f10x_clock_control_on(struct device *dev,
struct stm32f10x_rcc_data *data = dev->driver_data;
volatile struct stm32f10x_rcc *rcc =
(struct stm32f10x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
u32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
@ -48,7 +48,7 @@ static inline int stm32f10x_clock_control_off(struct device *dev,
struct stm32f10x_rcc_data *data = dev->driver_data;
volatile struct stm32f10x_rcc *rcc =
(struct stm32f10x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
u32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
@ -197,10 +197,10 @@ static int pll2mul(int mul)
}
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER */
static uint32_t get_ahb_clock(uint32_t sysclk)
static u32_t get_ahb_clock(u32_t sysclk)
{
/* AHB clock is generated based on SYSCLK */
uint32_t sysclk_div =
u32_t sysclk_div =
CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER;
if (sysclk_div == 0) {
@ -210,7 +210,7 @@ static uint32_t get_ahb_clock(uint32_t sysclk)
return sysclk / sysclk_div;
}
static uint32_t get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
static u32_t get_apb_clock(u32_t ahb_clock, u32_t prescaler)
{
if (prescaler == 0) {
prescaler = 1;
@ -222,15 +222,15 @@ static uint32_t get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
static
int stm32f10x_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
u32_t *rate)
{
ARG_UNUSED(clock);
uint32_t subsys = POINTER_TO_UINT(sub_system);
uint32_t prescaler =
u32_t subsys = POINTER_TO_UINT(sub_system);
u32_t prescaler =
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER;
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
uint32_t ahb_clock =
u32_t ahb_clock =
get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
@ -275,26 +275,26 @@ static int stm32f10x_clock_control_init(struct device *dev)
(struct stm32f10x_rcc *)(data->base);
/* SYSCLK source defaults to HSI */
int sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
uint32_t hpre =
u32_t hpre =
ahb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER);
uint32_t ppre1 =
u32_t ppre1 =
apb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER);
uint32_t ppre2 =
u32_t ppre2 =
apb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER);
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER
uint32_t pll_mul =
u32_t pll_mul =
pllmul(CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
uint32_t pll2_mul =
u32_t pll2_mul =
pll2mul(CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1
uint32_t prediv1 =
u32_t prediv1 =
prediv_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1 */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2
uint32_t prediv2 =
u32_t prediv2 =
prediv_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2);
#endif /* CLOCK_STM32F10X_CONN_LINE_PREDIV2 */
@ -406,7 +406,7 @@ static int stm32f10x_clock_control_init(struct device *dev)
}
static struct stm32f10x_rcc_data stm32f10x_rcc_data = {
.base = (uint8_t *)RCC_BASE,
.base = (u8_t *)RCC_BASE,
};
/* FIXME: move prescaler/multiplier defines into device config */

30
drivers/clock_control/stm32f10x_clock.c
View file

@ -22,7 +22,7 @@
#include <clock_control/stm32_clock_control.h>
struct stm32f10x_rcc_data {
uint8_t *base;
u8_t *base;
};
static inline int stm32f10x_clock_control_on(struct device *dev,
@ -32,7 +32,7 @@ static inline int stm32f10x_clock_control_on(struct device *dev,
volatile struct stm32f10x_rcc *rcc = (struct stm32f10x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
u32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
@ -49,7 +49,7 @@ static inline int stm32f10x_clock_control_off(struct device *dev,
struct stm32f10x_rcc_data *data = dev->driver_data;
volatile struct stm32f10x_rcc *rcc =
(struct stm32f10x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
u32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
@ -139,10 +139,10 @@ static int __pllmul(int mul)
#endif /* CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER */
static uint32_t __get_ahb_clock(uint32_t sysclk)
static u32_t __get_ahb_clock(u32_t sysclk)
{
/* AHB clock is generated based on SYSCLK */
uint32_t sysclk_div = CONFIG_CLOCK_STM32F10X_AHB_PRESCALER;
u32_t sysclk_div = CONFIG_CLOCK_STM32F10X_AHB_PRESCALER;
if (sysclk_div == 0) {
sysclk_div = 1;
@ -150,7 +150,7 @@ static uint32_t __get_ahb_clock(uint32_t sysclk)
return sysclk / sysclk_div;
}
static uint32_t __get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
static u32_t __get_apb_clock(u32_t ahb_clock, u32_t prescaler)
{
if (prescaler == 0) {
prescaler = 1;
@ -160,20 +160,20 @@ static uint32_t __get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
static int stm32f10x_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
u32_t *rate)
{
ARG_UNUSED(clock);
uint32_t subsys = POINTER_TO_UINT(sub_system);
u32_t subsys = POINTER_TO_UINT(sub_system);
uint32_t prescaler = CONFIG_CLOCK_STM32F10X_APB1_PRESCALER;
u32_t prescaler = CONFIG_CLOCK_STM32F10X_APB1_PRESCALER;
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
prescaler = CONFIG_CLOCK_STM32F10X_APB2_PRESCALER;
}
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
uint32_t ahb_clock =
u32_t ahb_clock =
__get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
*rate = __get_apb_clock(ahb_clock, prescaler);
@ -213,11 +213,11 @@ static int stm32f10x_clock_control_init(struct device *dev)
(struct stm32f10x_rcc *)(data->base);
/* SYSCLK source defaults to HSI */
int sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
uint32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F10X_AHB_PRESCALER);
uint32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB1_PRESCALER);
uint32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB2_PRESCALER);
u32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F10X_AHB_PRESCALER);
u32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB1_PRESCALER);
u32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB2_PRESCALER);
#ifdef CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER
uint32_t pllmul = __pllmul(CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER);
u32_t pllmul = __pllmul(CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER */
/* disable PLL */
@ -303,7 +303,7 @@ static int stm32f10x_clock_control_init(struct device *dev)
}
static struct stm32f10x_rcc_data stm32f10x_rcc_data = {
.base = (uint8_t *)RCC_BASE,
.base = (u8_t *)RCC_BASE,
};
/* FIXME: move prescaler/multiplier defines into device config */

38
drivers/clock_control/stm32f4x_clock.c
View file

@ -23,7 +23,7 @@
#include <clock_control/stm32_clock_control.h>
struct stm32f4x_rcc_data {
uint8_t *base;
u8_t *base;
};
static inline int stm32f4x_clock_control_on(struct device *dev,
@ -32,7 +32,7 @@ static inline int stm32f4x_clock_control_on(struct device *dev,
struct stm32f4x_rcc_data *data = dev->driver_data;
volatile struct stm32f4x_rcc *rcc = (struct stm32f4x_rcc *)(data->base);
struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
uint32_t tmpreg = 0; /* Register delay helper */
u32_t tmpreg = 0; /* Register delay helper */
switch (pclken->bus) {
case STM32F4X_CLOCK_BUS_AHB1:
@ -62,7 +62,7 @@ static inline int stm32f4x_clock_control_off(struct device *dev,
struct stm32f4x_rcc_data *data = dev->driver_data;
volatile struct stm32f4x_rcc *rcc = (struct stm32f4x_rcc *)(data->base);
struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
uint32_t tmpreg = 0; /* Register delay helper */
u32_t tmpreg = 0; /* Register delay helper */
switch (pclken->bus) {
case STM32F4X_CLOCK_BUS_AHB1:
@ -170,10 +170,10 @@ static int __pllp_div(int div)
}
#endif /* CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL */
static uint32_t __get_ahb_clock(uint32_t sysclk)
static u32_t __get_ahb_clock(u32_t sysclk)
{
/* AHB clock is generated based on SYSCLK */
uint32_t sysclk_div = CONFIG_CLOCK_STM32F4X_AHB_PRESCALER;
u32_t sysclk_div = CONFIG_CLOCK_STM32F4X_AHB_PRESCALER;
if (sysclk_div == 0) {
sysclk_div = 1;
@ -182,7 +182,7 @@ static uint32_t __get_ahb_clock(uint32_t sysclk)
return sysclk / sysclk_div;
}
static uint32_t __get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
static u32_t __get_apb_clock(u32_t ahb_clock, u32_t prescaler)
{
if (prescaler == 0) {
prescaler = 1;
@ -193,15 +193,15 @@ static uint32_t __get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
static int stm32f4x_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
u32_t *rate)
{
struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
uint32_t ahb_clock =
u32_t ahb_clock =
__get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
uint32_t apb1_clock = __get_apb_clock(ahb_clock,
u32_t apb1_clock = __get_apb_clock(ahb_clock,
CONFIG_CLOCK_STM32F4X_APB1_PRESCALER);
uint32_t apb2_clock = __get_apb_clock(ahb_clock,
u32_t apb2_clock = __get_apb_clock(ahb_clock,
CONFIG_CLOCK_STM32F4X_APB2_PRESCALER);
ARG_UNUSED(clock);
@ -234,17 +234,17 @@ static int stm32f4x_clock_control_init(struct device *dev)
(struct stm32f4x_rcc *)(data->base);
/* SYSCLK source defaults to HSI */
int sysclk_src = STM32F4X_RCC_CFG_SYSCLK_SRC_HSI;
uint32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F4X_AHB_PRESCALER);
uint32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB1_PRESCALER);
uint32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB2_PRESCALER);
u32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F4X_AHB_PRESCALER);
u32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB1_PRESCALER);
u32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB2_PRESCALER);
#ifdef CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL
uint32_t pllmdiv = CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR;
uint32_t pllnmul = CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER;
uint32_t pllpdiv = __pllp_div(CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR);
uint32_t pllqdiv = CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR;
u32_t pllmdiv = CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR;
u32_t pllnmul = CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER;
u32_t pllpdiv = __pllp_div(CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR);
u32_t pllqdiv = CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR;
#endif /* CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL */
/* Register delay helper */
uint32_t tmpreg = 0;
u32_t tmpreg = 0;
/* Enable power control clock */
rcc->apb1enr |= STM32F4X_RCC_APB1ENR_PWREN;
@ -333,7 +333,7 @@ static int stm32f4x_clock_control_init(struct device *dev)
}
static struct stm32f4x_rcc_data stm32f4x_rcc_data = {
.base = (uint8_t *)RCC_BASE,
.base = (u8_t *)RCC_BASE,
};
/* FIXME: move prescaler/multiplier defines into device config */

8
drivers/console/ipm_console_receiver.c
View file

@ -18,8 +18,8 @@
static void ipm_console_thread(void *arg1, void *arg2, void *arg3)
{
uint8_t size32;
uint16_t type;
u8_t size32;
u16_t type;
int ret, key;
struct device *d;
const struct ipm_console_receiver_config_info *config_info;
@ -37,7 +37,7 @@ static void ipm_console_thread(void *arg1, void *arg2, void *arg3)
k_sem_take(&driver_data->sem, K_FOREVER);
ret = sys_ring_buf_get(&driver_data->rb, &type,
(uint8_t *)&config_info->line_buf[pos],
(u8_t *)&config_info->line_buf[pos],
NULL, &size32);
if (ret) {
/* Shouldn't ever happen... */
@ -84,7 +84,7 @@ static void ipm_console_thread(void *arg1, void *arg2, void *arg3)
}
}
static void ipm_console_receive_callback(void *context, uint32_t id,
static void ipm_console_receive_callback(void *context, u32_t id,
volatile void *data)
{
struct device *d;

18
drivers/console/telnet_console.c
View file

@ -55,13 +55,13 @@
*/
struct line_buf {
char buf[TELNET_LINE_SIZE];
uint16_t len;
u16_t len;
};
struct line_buf_rb {
struct line_buf l_bufs[TELNET_LINES];
uint16_t line_in;
uint16_t line_out;
u16_t line_in;
u16_t line_out;
};
static struct line_buf_rb telnet_rb;
@ -160,7 +160,7 @@ static void telnet_rb_switch(void)
static inline struct line_buf *telnet_rb_get_line_out(void)
{
uint16_t out = telnet_rb.line_out;
u16_t out = telnet_rb.line_out;
telnet_rb.line_out++;
if (telnet_rb.line_out == TELNET_LINES) {
@ -256,7 +256,7 @@ static int telnet_console_out_nothing(int c)
return c;
}
static inline void telnet_command_send_reply(uint8_t *msg, uint16_t len)
static inline void telnet_command_send_reply(u8_t *msg, u16_t len)
{
net_pkt_append(out_pkt, len, msg, K_FOREVER);
@ -270,7 +270,7 @@ static inline void telnet_reply_ay_command(void)
{
static const char alive[24] = "Zephyr at your service\r\n";
telnet_command_send_reply((uint8_t *)alive, 24);
telnet_command_send_reply((u8_t *)alive, 24);
}
static inline void telnet_reply_do_command(void)
@ -284,7 +284,7 @@ static inline void telnet_reply_do_command(void)
break;
}
telnet_command_send_reply((uint8_t *)&telnet_cmd,
telnet_command_send_reply((u8_t *)&telnet_cmd,
sizeof(struct telnet_simple_command));
}
@ -354,7 +354,7 @@ static inline bool telnet_handle_command(struct net_pkt *pkt)
static inline void telnet_handle_input(struct net_pkt *pkt)
{
struct console_input *input;
uint16_t len, offset, pos;
u16_t len, offset, pos;
len = net_pkt_appdatalen(pkt);
if (len > CONSOLE_MAX_LINE_LEN || len < TELNET_MIN_MSG) {
@ -503,7 +503,7 @@ error:
}
void telnet_register_input(struct k_fifo *avail, struct k_fifo *lines,
uint8_t (*completion)(char *str, uint8_t len))
u8_t (*completion)(char *str, u8_t len))
{
ARG_UNUSED(completion);

6
drivers/console/telnet_protocol.h
View file

@ -107,11 +107,11 @@
/** Describes a telnet command */
struct telnet_simple_command {
/** Mandatory IAC code */
uint8_t iac;
u8_t iac;
/** Type of operation (see Telnet commands above) */
uint8_t op;
u8_t op;
/** Option code */
uint8_t opt;
u8_t opt;
};
static inline void telnet_command_cpy(struct telnet_simple_command *dst,

20
drivers/console/uart_console.c
View file

@ -132,7 +132,7 @@ extern void __printk_hook_install(int (*fn)(int));
#if defined(CONFIG_CONSOLE_HANDLER)
static struct k_fifo *avail_queue;
static struct k_fifo *lines_queue;
static uint8_t (*completion_cb)(char *line, uint8_t len);
static u8_t (*completion_cb)(char *line, u8_t len);
/* Control characters */
#define ESC 0x1b
@ -148,7 +148,7 @@ static uint8_t (*completion_cb)(char *line, uint8_t len);
#define ANSI_HOME 'H'
#define ANSI_DEL '~'
static int read_uart(struct device *uart, uint8_t *buf, unsigned int size)
static int read_uart(struct device *uart, u8_t *buf, unsigned int size)
{
int rx;
@ -183,7 +183,7 @@ static inline void cursor_restore(void)
printk("\x1b[u");
}
static void insert_char(char *pos, char c, uint8_t end)
static void insert_char(char *pos, char c, u8_t end)
{
char tmp;
@ -211,7 +211,7 @@ static void insert_char(char *pos, char c, uint8_t end)
cursor_restore();
}
static void del_char(char *pos, uint8_t end)
static void del_char(char *pos, u8_t end)
{
uart_poll_out(uart_console_dev, '\b');
@ -244,9 +244,9 @@ enum {
static atomic_t esc_state;
static unsigned int ansi_val, ansi_val_2;
static uint8_t cur, end;
static u8_t cur, end;
static void handle_ansi(uint8_t byte, char *line)
static void handle_ansi(u8_t byte, char *line)
{
if (atomic_test_and_clear_bit(&esc_state, ESC_ANSI_FIRST)) {
if (!isdigit(byte)) {
@ -342,7 +342,7 @@ void uart_console_isr(struct device *unused)
while (uart_irq_update(uart_console_dev) &&
uart_irq_is_pending(uart_console_dev)) {
static struct console_input *cmd;
uint8_t byte;
u8_t byte;
int rx;
if (!uart_irq_rx_ready(uart_console_dev)) {
@ -430,7 +430,7 @@ void uart_console_isr(struct device *unused)
static void console_input_init(void)
{
uint8_t c;
u8_t c;
uart_irq_rx_disable(uart_console_dev);
uart_irq_tx_disable(uart_console_dev);
@ -446,7 +446,7 @@ static void console_input_init(void)
}
void uart_register_input(struct k_fifo *avail, struct k_fifo *lines,
uint8_t (*completion)(char *str, uint8_t len))
u8_t (*completion)(char *str, u8_t len))
{
avail_queue = avail;
lines_queue = lines;
@ -492,7 +492,7 @@ static int uart_console_init(struct device *arg)
#ifdef CONFIG_USB_UART_CONSOLE
while (1) {
uint32_t dtr = 0;
u32_t dtr = 0;
uart_line_ctrl_get(uart_console_dev, LINE_CTRL_DTR, &dtr);
if (dtr) {

8
drivers/console/uart_pipe.c
View file

@ -21,7 +21,7 @@
static struct device *uart_pipe_dev;
static uint8_t *recv_buf;
static u8_t *recv_buf;
static size_t recv_buf_len;
static uart_pipe_recv_cb app_cb;
static size_t recv_off;
@ -53,7 +53,7 @@ static void uart_pipe_isr(struct device *unused)
}
}
int uart_pipe_send(const uint8_t *data, int len)
int uart_pipe_send(const u8_t *data, int len)
{
while (len--) {
uart_poll_out(uart_pipe_dev, *data++);
@ -64,7 +64,7 @@ int uart_pipe_send(const uint8_t *data, int len)
static void uart_pipe_setup(struct device *uart)
{
uint8_t c;
u8_t c;
uart_irq_rx_disable(uart);
uart_irq_tx_disable(uart);
@ -79,7 +79,7 @@ static void uart_pipe_setup(struct device *uart)
uart_irq_rx_enable(uart);
}
void uart_pipe_register(uint8_t *buf, size_t len, uart_pipe_recv_cb cb)
void uart_pipe_register(u8_t *buf, size_t len, uart_pipe_recv_cb cb)
{
recv_buf = buf;
recv_buf_len = len;

6
drivers/counter/counter_dtmr_cmsdk_apb.c
View file

@ -50,13 +50,13 @@ static int counter_dtmr_cmsdk_apb_stop(struct device *dev)
return 0;
}
static uint32_t counter_dtmr_cmsdk_apb_read(struct device *dev)
static u32_t counter_dtmr_cmsdk_apb_read(struct device *dev)
{
const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Return Counter Value */
uint32_t value = 0;
u32_t value = 0;
value = DUALTIMER_MAX_RELOAD - cfg->dtimer->timer1value;
@ -65,7 +65,7 @@ static uint32_t counter_dtmr_cmsdk_apb_read(struct device *dev)
static int counter_dtmr_cmsdk_apb_set_alarm(struct device *dev,
counter_callback_t callback,
uint32_t count, void *user_data)
u32_t count, void *user_data)
{
return -ENODEV;
}

6
drivers/counter/counter_qmsi_aon.c
View file

@ -29,9 +29,9 @@ static int aon_counter_qmsi_stop(struct device *dev)
return 0;
}
static uint32_t aon_counter_qmsi_read(struct device *dev)
static u32_t aon_counter_qmsi_read(struct device *dev)
{
uint32_t value;
u32_t value;
qm_aonc_get_value(QM_AONC_0, &value);
@ -40,7 +40,7 @@ static uint32_t aon_counter_qmsi_read(struct device *dev)
static int aon_counter_qmsi_set_alarm(struct device *dev,
counter_callback_t callback,
uint32_t count, void *user_data)
u32_t count, void *user_data)
{
return -ENODEV;
}

22
drivers/counter/counter_qmsi_aonpt.c
View file

@ -26,7 +26,7 @@ struct aon_data {
struct k_sem sem;
#endif
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
#endif
};
@ -98,9 +98,9 @@ static int aon_timer_qmsi_stop(struct device *dev)
return 0;
}
static uint32_t aon_timer_qmsi_read(struct device *dev)
static u32_t aon_timer_qmsi_read(struct device *dev)
{
uint32_t value;
u32_t value;
qm_aonpt_get_value(QM_AONC_0, &value);
@ -109,7 +109,7 @@ static uint32_t aon_timer_qmsi_read(struct device *dev)
static int aon_timer_qmsi_set_alarm(struct device *dev,
counter_callback_t callback,
uint32_t count, void *user_data)
u32_t count, void *user_data)
{
qm_aonpt_config_t qmsi_cfg;
int result = 0;
@ -142,7 +142,7 @@ static int aon_timer_qmsi_set_alarm(struct device *dev,
return result;
}
static uint32_t aon_timer_qmsi_get_pending_int(struct device *dev)
static u32_t aon_timer_qmsi_get_pending_int(struct device *dev)
{
return QM_AONC[QM_AONC_0]->aonpt_stat;
}
@ -158,14 +158,14 @@ static const struct counter_driver_api aon_timer_qmsi_api = {
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static qm_aonc_context_t aonc_ctx;
static void aonpt_qmsi_set_power_state(struct device *dev, uint32_t power_state)
static void aonpt_qmsi_set_power_state(struct device *dev, u32_t power_state)
{
struct aon_data *context = dev->driver_data;
context->device_power_state = power_state;
}
static uint32_t aonpt_qmsi_get_power_state(struct device *dev)
static u32_t aonpt_qmsi_get_power_state(struct device *dev)
{
struct aon_data *context = dev->driver_data;
@ -194,17 +194,17 @@ static int aonpt_resume_device_from_suspend(struct device *dev)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int aonpt_qmsi_device_ctrl(struct device *dev, uint32_t ctrl_command,
static int aonpt_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return aonpt_suspend_device(dev);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return aonpt_resume_device_from_suspend(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = aonpt_qmsi_get_power_state(dev);
*((u32_t *)context) = aonpt_qmsi_get_power_state(dev);
return 0;
}

6
drivers/counter/counter_tmr_cmsdk_apb.c
View file

@ -50,13 +50,13 @@ static int counter_tmr_cmsdk_apb_stop(struct device *dev)
return 0;
}
static uint32_t counter_tmr_cmsdk_apb_read(struct device *dev)
static u32_t counter_tmr_cmsdk_apb_read(struct device *dev)
{
const struct counter_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Return Counter Value */
uint32_t value = 0;
u32_t value = 0;
value = TIMER_MAX_RELOAD - cfg->timer->value;
@ -65,7 +65,7 @@ static uint32_t counter_tmr_cmsdk_apb_read(struct device *dev)
static int counter_tmr_cmsdk_apb_set_alarm(struct device *dev,
counter_callback_t callback,
uint32_t count, void *user_data)
u32_t count, void *user_data)
{
return -ENODEV;
}

36
drivers/counter/dualtimer_cmsdk_apb.h
View file

@ -14,41 +14,41 @@ extern "C" {
struct dualtimer_cmsdk_apb {
/* Offset: 0x000 (R/W) Timer 1 Load */
volatile uint32_t timer1load;
volatile u32_t timer1load;
/* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
volatile uint32_t timer1value;
volatile u32_t timer1value;
/* Offset: 0x008 (R/W) Timer 1 Control */
volatile uint32_t timer1ctrl;
volatile u32_t timer1ctrl;
/* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
volatile uint32_t timer1intclr;
volatile u32_t timer1intclr;
/* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
volatile uint32_t timer1ris;
volatile u32_t timer1ris;
/* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
volatile uint32_t timer1mis;
volatile u32_t timer1mis;
/* Offset: 0x018 (R/W) Background Load Register */
volatile uint32_t timer1bgload;
volatile u32_t timer1bgload;
/* Reserved */
volatile uint32_t reserved0;
volatile u32_t reserved0;
/* Offset: 0x020 (R/W) Timer 2 Load */
volatile uint32_t timer2load;
volatile u32_t timer2load;
/* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
volatile uint32_t timer2value;
volatile u32_t timer2value;
/* Offset: 0x028 (R/W) Timer 2 Control */
volatile uint32_t timer2ctrl;
volatile u32_t timer2ctrl;
/* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
volatile uint32_t timer2intclr;
volatile u32_t timer2intclr;
/* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
volatile uint32_t timer2ris;
volatile u32_t timer2ris;
/* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
volatile uint32_t timer2mis;
volatile u32_t timer2mis;
/* Offset: 0x038 (R/W) Background Load Register */
volatile uint32_t timer2bgload;
volatile u32_t timer2bgload;
/* Reserved */
volatile uint32_t reserved1[945];
volatile u32_t reserved1[945];
/* Offset: 0xF00 (R/W) Integration Test Control Register */
volatile uint32_t itcr;
volatile u32_t itcr;
/* Offset: 0xF04 ( /W) Integration Test Output Set Register */
volatile uint32_t itop;
volatile u32_t itop;
};
#define DUALTIMER_CTRL_EN (1 << 7)

10
drivers/counter/timer_cmsdk_apb.h
View file

@ -14,16 +14,16 @@ extern "C" {
struct timer_cmsdk_apb {
/* Offset: 0x000 (R/W) control register */
volatile uint32_t ctrl;
volatile u32_t ctrl;
/* Offset: 0x004 (R/W) current value register */
volatile uint32_t value;
volatile u32_t value;
/* Offset: 0x008 (R/W) reload value register */
volatile uint32_t reload;
volatile u32_t reload;
union {
/* Offset: 0x00C (R/ ) interrupt status register */
volatile uint32_t intstatus;
volatile u32_t intstatus;
/* Offset: 0x00C ( /W) interruptclear register */
volatile uint32_t intclear;
volatile u32_t intclear;
};
};

10
drivers/counter/timer_dtmr_cmsdk_apb.c
View file

@ -36,7 +36,7 @@ struct timer_dtmr_cmsdk_apb_cfg {
};
struct timer_dtmr_cmsdk_apb_dev_data {
uint32_t load;
u32_t load;
enum dtimer_status_t status;
};
@ -73,14 +73,14 @@ static int timer_dtmr_cmsdk_apb_stop(struct device *dev)
return 0;
}
static uint32_t timer_dtmr_cmsdk_apb_read(struct device *dev)
static u32_t timer_dtmr_cmsdk_apb_read(struct device *dev)
{
const struct timer_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
struct timer_dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Return Timer Value */
uint32_t value = 0;
u32_t value = 0;
value = data->load - cfg->dtimer->timer1value;
@ -89,7 +89,7 @@ static uint32_t timer_dtmr_cmsdk_apb_read(struct device *dev)
static int timer_dtmr_cmsdk_apb_set_alarm(struct device *dev,
counter_callback_t callback,
uint32_t count, void *user_data)
u32_t count, void *user_data)
{
const struct timer_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
@ -115,7 +115,7 @@ static int timer_dtmr_cmsdk_apb_set_alarm(struct device *dev,
return 0;
}
static uint32_t timer_dtmr_cmsdk_apb_get_pending_int(struct device *dev)
static u32_t timer_dtmr_cmsdk_apb_get_pending_int(struct device *dev)
{
const struct timer_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;

10
drivers/counter/timer_tmr_cmsdk_apb.c
View file

@ -36,7 +36,7 @@ struct timer_tmr_cmsdk_apb_cfg {
};
struct timer_tmr_cmsdk_apb_dev_data {
uint32_t load;
u32_t load;
enum timer_status_t status;
};
@ -73,14 +73,14 @@ static int timer_tmr_cmsdk_apb_stop(struct device *dev)
return 0;
}
static uint32_t timer_tmr_cmsdk_apb_read(struct device *dev)
static u32_t timer_tmr_cmsdk_apb_read(struct device *dev)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Return Counter Value */
uint32_t value = 0;
u32_t value = 0;
value = data->load - cfg->timer->value;
@ -89,7 +89,7 @@ static uint32_t timer_tmr_cmsdk_apb_read(struct device *dev)
static int timer_tmr_cmsdk_apb_set_alarm(struct device *dev,
counter_callback_t callback,
uint32_t count, void *user_data)
u32_t count, void *user_data)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
@ -117,7 +117,7 @@ static int timer_tmr_cmsdk_apb_set_alarm(struct device *dev,
return 0;
}
static uint32_t timer_tmr_cmsdk_apb_get_pending_int(struct device *dev)
static u32_t timer_tmr_cmsdk_apb_get_pending_int(struct device *dev)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;

8
drivers/crc/crc16_sw.c
View file

@ -6,17 +6,17 @@
#include <crc16.h>
uint16_t crc16(const uint8_t *src, size_t len, uint16_t polynomial,
uint16_t initial_value)
u16_t crc16(const u8_t *src, size_t len, u16_t polynomial,
u16_t initial_value)
{
uint16_t crc = initial_value;
u16_t crc = initial_value;
size_t i, b;
/* src length + crc width of zeros appended */
for (i = 0; i < len + sizeof(crc); i++) {
for (b = 0; b < 8; b++) {
uint16_t divide = crc & 0x8000;
u16_t divide = crc & 0x8000;
crc = (crc << 1);

76
drivers/crypto/crypto_ataes132a.c
View file

@ -36,17 +36,17 @@ static void ataes132a_init_states(void)
}
}
static int ataes132a_send_command(struct device *dev, uint8_t opcode,
uint8_t mode, uint8_t *params,
uint8_t nparams, uint8_t *response,
uint8_t *nresponse)
static int ataes132a_send_command(struct device *dev, u8_t opcode,
u8_t mode, u8_t *params,
u8_t nparams, u8_t *response,
u8_t *nresponse)
{
int retry_count = 0;
struct ataes132a_device_data *data = dev->driver_data;
const struct ataes132a_device_config *cfg = dev->config->config_info;
uint8_t count;
uint8_t status;
uint8_t crc[2];
u8_t count;
u8_t status;
u8_t crc[2];
int i, i2c_return;
count = nparams + 5;
@ -192,19 +192,19 @@ int ataes132a_init(struct device *dev)
}
int ataes132a_aes_ccm_decrypt(struct device *dev,
uint8_t key_id,
u8_t key_id,
struct ataes132a_mac_mode *mac_mode,
struct ataes132a_mac_packet *mac_packet,
struct cipher_aead_pkt *aead_op,
uint8_t *nonce_buf)
u8_t *nonce_buf)
{
uint8_t command_mode = 0x0;
u8_t command_mode = 0x0;
struct ataes132a_device_data *data = dev->driver_data;
uint8_t out_len;
uint8_t in_buf_len;
uint8_t return_code;
uint8_t expected_out_len;
uint8_t param_buffer[52];
u8_t out_len;
u8_t in_buf_len;
u8_t return_code;
u8_t expected_out_len;
u8_t param_buffer[52];
if (!aead_op) {
SYS_LOG_ERR("Parameter cannot be null");
@ -392,18 +392,18 @@ int ataes132a_aes_ccm_decrypt(struct device *dev,
}
int ataes132a_aes_ccm_encrypt(struct device *dev,
uint8_t key_id,
u8_t key_id,
struct ataes132a_mac_mode *mac_mode,
struct cipher_aead_pkt *aead_op,
uint8_t *nonce_buf,
uint8_t *mac_count)
u8_t *nonce_buf,
u8_t *mac_count)
{
uint8_t command_mode = 0x0;
u8_t command_mode = 0x0;
struct ataes132a_device_data *data = dev->driver_data;
uint8_t buf_len;
uint8_t out_len;
uint8_t return_code;
uint8_t param_buffer[40];
u8_t buf_len;
u8_t out_len;
u8_t return_code;
u8_t param_buffer[40];
if (!aead_op) {
SYS_LOG_ERR("Parameter cannot be null");
@ -580,14 +580,14 @@ int ataes132a_aes_ccm_encrypt(struct device *dev,
}
int ataes132a_aes_ecb_block(struct device *dev,
uint8_t key_id,
u8_t key_id,
struct cipher_pkt *pkt)
{
struct ataes132a_device_data *data = dev->driver_data;
uint8_t buf_len;
uint8_t out_len;
uint8_t return_code;
uint8_t param_buffer[19];
u8_t buf_len;
u8_t out_len;
u8_t return_code;
u8_t param_buffer[19];
if (!pkt) {
SYS_LOG_ERR("Parameter cannot be null");
@ -668,16 +668,16 @@ int ataes132a_aes_ecb_block(struct device *dev,
}
static int do_ccm_encrypt_mac(struct cipher_ctx *ctx,
struct cipher_aead_pkt *aead_op, uint8_t *nonce)
struct cipher_aead_pkt *aead_op, u8_t *nonce)
{
struct device *dev = ctx->device;
struct ataes132a_driver_state *state = ctx->drv_sessn_state;
struct ataes132a_mac_mode mac_mode;
uint8_t key_id;
u8_t key_id;
key_id = state->key_id;
assert(*(uint8_t *)ctx->key.handle == key_id);
assert(*(u8_t *)ctx->key.handle == key_id);
/* Removing all this salt from the MAC reduces the protection
* but allows any other crypto implementations to authorize
@ -717,16 +717,16 @@ static int do_ccm_encrypt_mac(struct cipher_ctx *ctx,
}
static int do_ccm_decrypt_auth(struct cipher_ctx *ctx,
struct cipher_aead_pkt *aead_op, uint8_t *nonce)
struct cipher_aead_pkt *aead_op, u8_t *nonce)
{
struct device *dev = ctx->device;
struct ataes132a_driver_state *state = ctx->drv_sessn_state;
struct ataes132a_mac_mode mac_mode;
uint8_t key_id;
u8_t key_id;
key_id = state->key_id;
assert(*(uint8_t *)ctx->key.handle == key_id);
assert(*(u8_t *)ctx->key.handle == key_id);
/* Removing all this salt from the MAC reduces the protection
* but allows any other crypto implementations to authorize
@ -766,11 +766,11 @@ static int do_block(struct cipher_ctx *ctx, struct cipher_pkt *pkt)
{
struct device *dev = ctx->device;
struct ataes132a_driver_state *state = ctx->drv_sessn_state;
uint8_t key_id;
u8_t key_id;
key_id = state->key_id;
assert(*(uint8_t *)ctx->key.handle == key_id);
assert(*(u8_t *)ctx->key.handle == key_id);
if (pkt->out_buf_max < 16) {
SYS_LOG_ERR("Not enough space available in out buffer.");
@ -797,10 +797,10 @@ int ataes132a_session_setup(struct device *dev, struct cipher_ctx *ctx,
enum cipher_algo algo, enum cipher_mode mode,
enum cipher_op op_type)
{
uint8_t key_id = *((uint8_t *)ctx->key.handle);
u8_t key_id = *((u8_t *)ctx->key.handle);
struct ataes132a_device_data *data = dev->driver_data;
const struct ataes132a_device_config *cfg = dev->config->config_info;
uint8_t config;
u8_t config;
if (ataes132a_state[key_id].in_use) {
SYS_LOG_ERR("Session in progress");

66
drivers/crypto/crypto_ataes132a_priv.h
View file

@ -110,14 +110,14 @@
#define CRC16_POLY 0x8005
void ataes132a_atmel_crc(uint8_t *input, uint8_t length,
uint8_t *output)
void ataes132a_atmel_crc(u8_t *input, u8_t length,
u8_t *output)
{
int i, j;
uint8_t bit;
uint16_t crc;
uint16_t double_carry;
uint8_t higher_crc_bit;
u8_t bit;
u16_t crc;
u16_t double_carry;
u8_t higher_crc_bit;
for (i = 0, crc = 0; i < length; i++) {
for (j = 7; j >= 0; j--) {
@ -133,15 +133,15 @@ void ataes132a_atmel_crc(uint8_t *input, uint8_t length,
}
}
*(uint16_t *)output = crc << 8 | crc >> 8;
*(u16_t *)output = crc << 8 | crc >> 8;
}
static inline int burst_write_i2c(struct device *dev, uint16_t dev_addr,
uint16_t start_addr, uint8_t *buf,
uint8_t num_bytes)
static inline int burst_write_i2c(struct device *dev, u16_t dev_addr,
u16_t start_addr, u8_t *buf,
u8_t num_bytes)
{
const struct i2c_driver_api *api = dev->driver_api;
uint8_t addr_buffer[2];
u8_t addr_buffer[2];
struct i2c_msg msg[2];
addr_buffer[1] = start_addr & 0xFF;
@ -158,12 +158,12 @@ static inline int burst_write_i2c(struct device *dev, uint16_t dev_addr,
}
static inline int burst_read_i2c(struct device *dev, uint16_t dev_addr,
uint16_t start_addr, uint8_t *buf,
uint8_t num_bytes)
static inline int burst_read_i2c(struct device *dev, u16_t dev_addr,
u16_t start_addr, u8_t *buf,
u8_t num_bytes)
{
const struct i2c_driver_api *api = dev->driver_api;
uint8_t addr_buffer[2];
u8_t addr_buffer[2];
struct i2c_msg msg[2];
addr_buffer[1] = start_addr & 0xFF;
@ -179,35 +179,35 @@ static inline int burst_read_i2c(struct device *dev, uint16_t dev_addr,
return api->transfer(dev, msg, 2, dev_addr);
}
static inline int read_reg_i2c(struct device *dev, uint16_t dev_addr,
uint16_t reg_addr, uint8_t *value)
static inline int read_reg_i2c(struct device *dev, u16_t dev_addr,
u16_t reg_addr, u8_t *value)
{
return burst_read_i2c(dev, dev_addr, reg_addr, value, 1);
}
static inline int write_reg_i2c(struct device *dev, uint16_t dev_addr,
uint16_t reg_addr, uint8_t value)
static inline int write_reg_i2c(struct device *dev, u16_t dev_addr,
u16_t reg_addr, u8_t value)
{
return burst_write_i2c(dev, dev_addr, reg_addr, &value, 1);
}
struct ataes132a_device_config {
const char *i2c_port;
uint16_t i2c_addr;
uint8_t i2c_speed;
u16_t i2c_addr;
u8_t i2c_speed;
};
struct ataes132a_device_data {
struct device *i2c;
uint8_t command_buffer[64];
u8_t command_buffer[64];
struct k_sem device_sem;
};
struct ataes132a_driver_state {
bool in_use;
uint8_t key_id;
uint8_t key_config;
uint8_t chip_config;
u8_t key_id;
u8_t key_config;
u8_t chip_config;
};
/**
@ -216,9 +216,9 @@ struct ataes132a_driver_state {
*/
struct ataes132a_mac_packet {
/** Key storage id used on CCM encryption */
uint8_t encryption_key_id;
u8_t encryption_key_id;
/** MAC Count value */
uint8_t encryption_mac_count;
u8_t encryption_mac_count;
};
/**
@ -312,11 +312,11 @@ int ataes132a_init(struct device *i2c_dev);
* @return Returns 0 in case of success and an error code otherwise.
*/
int ataes132a_aes_ccm_decrypt(struct device *i2c_dev,
uint8_t key_id,
u8_t key_id,
struct ataes132a_mac_mode *mac_mode,
struct ataes132a_mac_packet *mac_packet,
struct cipher_aead_pkt *aead_op,
uint8_t *nonce_buf);
u8_t *nonce_buf);
/**
* @brief ATAES132A CCM encrypt function
@ -360,11 +360,11 @@ int ataes132a_aes_ccm_decrypt(struct device *i2c_dev,
* @return Returns 0 in case of success and an error code otherwise.
*/
int ataes132a_aes_ccm_encrypt(struct device *i2c_dev,
uint8_t key_id,
u8_t key_id,
struct ataes132a_mac_mode *mac_mode,
struct cipher_aead_pkt *aead_op,
uint8_t *nonce_buf,
uint8_t *mac_count);
u8_t *nonce_buf,
u8_t *mac_count);
/**
* @brief ATAES132A ECM block function
@ -388,7 +388,7 @@ int ataes132a_aes_ccm_encrypt(struct device *i2c_dev,
* @return Returns 0 in case of success and an error code otherwise.
*/
int ataes132a_aes_ecb_block(struct device *i2c_dev,
uint8_t key_id,
u8_t key_id,
struct cipher_pkt *pkt);
#endif /* _ATAES132A_PRIV_ */

12
drivers/crypto/tc_shim.c
View file

@ -26,7 +26,7 @@
static struct tc_shim_drv_state tc_driver_state[CRYPTO_MAX_SESSION];
static int do_cbc_encrypt(struct cipher_ctx *ctx, struct cipher_pkt *op,
uint8_t *iv)
u8_t *iv)
{
struct tc_shim_drv_state *data = ctx->drv_sessn_state;
@ -44,7 +44,7 @@ static int do_cbc_encrypt(struct cipher_ctx *ctx, struct cipher_pkt *op,
}
static int do_cbc_decrypt(struct cipher_ctx *ctx, struct cipher_pkt *op,
uint8_t *iv)
u8_t *iv)
{
struct tc_shim_drv_state *data = ctx->drv_sessn_state;
@ -71,10 +71,10 @@ static int do_cbc_decrypt(struct cipher_ctx *ctx, struct cipher_pkt *op,
static int do_ctr_op(struct cipher_ctx *ctx, struct cipher_pkt *op,
uint8_t *iv)
u8_t *iv)
{
struct tc_shim_drv_state *data = ctx->drv_sessn_state;
uint8_t ctr[16] = {0}; /* CTR mode Counter = iv:ctr */
u8_t ctr[16] = {0}; /* CTR mode Counter = iv:ctr */
int ivlen = ctx->keylen - (ctx->mode_params.ctr_info.ctr_len >> 3);
/* Tinycrypt takes the last 4 bytes of the counter parameter as the
@ -93,7 +93,7 @@ static int do_ctr_op(struct cipher_ctx *ctx, struct cipher_pkt *op,
}
static int do_ccm_encrypt_mac(struct cipher_ctx *ctx,
struct cipher_aead_pkt *aead_op, uint8_t *nonce)
struct cipher_aead_pkt *aead_op, u8_t *nonce)
{
struct tc_ccm_mode_struct ccm;
struct tc_shim_drv_state *data = ctx->drv_sessn_state;
@ -125,7 +125,7 @@ static int do_ccm_encrypt_mac(struct cipher_ctx *ctx,
}
static int do_ccm_decrypt_auth(struct cipher_ctx *ctx,
struct cipher_aead_pkt *aead_op, uint8_t *nonce)
struct cipher_aead_pkt *aead_op, u8_t *nonce)
{
struct tc_ccm_mode_struct ccm;
struct tc_shim_drv_state *data = ctx->drv_sessn_state;

36
drivers/display/mb_display.c
View file

@ -38,21 +38,21 @@ struct mb_display {
struct k_timer timer; /* Rendering timer */
uint8_t img_count; /* Image count */
u8_t img_count; /* Image count */
uint8_t cur_img; /* Current image or character to show */
u8_t cur_img; /* Current image or character to show */
uint8_t scroll:3, /* Scroll shift */
u8_t scroll:3, /* Scroll shift */
first:1, /* First frame of a scroll sequence */
loop:1, /* Loop to beginning */
text:1, /* We're showing a string (not image) */
img_sep:1; /* One column image separation */
/* The following variables track the currently shown image */
uint8_t cur; /* Currently rendered row */
uint32_t row[3]; /* Content (columns) for each row */
int64_t expiry; /* When to stop showing current image */
int32_t duration; /* Duration for each shown image */
u8_t cur; /* Currently rendered row */
u32_t row[3]; /* Content (columns) for each row */
s64_t expiry; /* When to stop showing current image */
s32_t duration; /* Duration for each shown image */
union {
const struct mb_image *img; /* Array of images to show */
@ -64,7 +64,7 @@ struct mb_display {
};
struct x_y {
uint8_t x:4,
u8_t x:4,
y:4;
};
@ -78,7 +78,7 @@ static const struct x_y map[DISPLAY_ROWS][DISPLAY_COLS] = {
};
/* Mask of all the column bits */
static const uint32_t col_mask = (((~0UL) << LED_COL1_GPIO_PIN) &
static const u32_t col_mask = (((~0UL) << LED_COL1_GPIO_PIN) &
((~0UL) >> (31 - LED_COL9_GPIO_PIN)));
static inline const struct mb_image *get_font(char ch)
@ -123,10 +123,10 @@ static void start_image(struct mb_display *disp, const struct mb_image *img)
#define ROW_PIN(n) (LED_ROW1_GPIO_PIN + (n))
static inline void update_pins(struct mb_display *disp, uint32_t val)
static inline void update_pins(struct mb_display *disp, u32_t val)
{
if (IS_ENABLED(CONFIG_MICROBIT_DISPLAY_PIN_GRANULARITY)) {
uint32_t pin, prev = (disp->cur + 2) % 3;
u32_t pin, prev = (disp->cur + 2) % 3;
/* Disable the previous row */
gpio_pin_write(disp->dev, ROW_PIN(prev), 0);
@ -197,7 +197,7 @@ static inline bool last_frame(struct mb_display *disp)
}
}
static inline uint8_t scroll_steps(struct mb_display *disp)
static inline u8_t scroll_steps(struct mb_display *disp)
{
return 5 + disp->img_sep;
}
@ -285,7 +285,7 @@ static struct mb_display display = {
.timer = K_TIMER_INITIALIZER(display.timer, show_row, clear_display),
};
static void start_scroll(struct mb_display *disp, int32_t duration)
static void start_scroll(struct mb_display *disp, s32_t duration)
{
/* Divide total duration by number of scrolling steps */
if (duration) {
@ -300,7 +300,7 @@ static void start_scroll(struct mb_display *disp, int32_t duration)
start_image(disp, get_font(' '));
}
static void start_single(struct mb_display *disp, int32_t duration)
static void start_single(struct mb_display *disp, s32_t duration)
{
disp->duration = duration;
@ -311,8 +311,8 @@ static void start_single(struct mb_display *disp, int32_t duration)
}
}
void mb_display_image(struct mb_display *disp, uint32_t mode, int32_t duration,
const struct mb_image *img, uint8_t img_count)
void mb_display_image(struct mb_display *disp, u32_t mode, s32_t duration,
const struct mb_image *img, u8_t img_count)
{
reset_display(disp);
@ -343,8 +343,8 @@ void mb_display_stop(struct mb_display *disp)
reset_display(disp);
}
void mb_display_print(struct mb_display *disp, uint32_t mode,
int32_t duration, const char *fmt, ...)
void mb_display_print(struct mb_display *disp, u32_t mode,
s32_t duration, const char *fmt, ...)
{
va_list ap;

50
drivers/dma/dma_qmsi.c
View file

@ -29,7 +29,7 @@ struct dma_qmsi_config_info {
};
struct dma_qmsi_context {
uint32_t index;
u32_t index;
struct device *dev;
};
@ -38,11 +38,11 @@ struct dma_qmsi_driver_data {
void (*error[QM_DMA_CHANNEL_NUM])(struct device *dev, void *data);
void *callback_data[QM_DMA_CHANNEL_NUM];
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
qm_dma_context_t saved_ctx;
#endif
void (*dma_user_callback[QM_DMA_CHANNEL_NUM])(struct device *dev,
uint32_t channel_id,
u32_t channel_id,
int error_code);
};
@ -50,11 +50,11 @@ struct dma_qmsi_driver_data {
static struct dma_qmsi_context dma_context[QM_DMA_CHANNEL_NUM];
static void dma_qmsi_config(struct device *dev);
static void dma_callback(void *callback_context, uint32_t len,
static void dma_callback(void *callback_context, u32_t len,
int error_code)
{
struct dma_qmsi_driver_data *data;
uint32_t channel;
u32_t channel;
struct dma_qmsi_context *context = callback_context;
channel = context->index;
@ -68,12 +68,12 @@ static void dma_callback(void *callback_context, uint32_t len,
data->transfer[channel](context->dev, data->callback_data[channel]);
}
static void dma_drv_callback(void *callback_context, uint32_t len,
static void dma_drv_callback(void *callback_context, u32_t len,
int error_code)
{
struct dma_qmsi_context *context = callback_context;
struct dma_qmsi_driver_data *data;
uint32_t channel;
u32_t channel;
channel = context->index;
data = context->dev->driver_data;
@ -81,7 +81,7 @@ static void dma_drv_callback(void *callback_context, uint32_t len,
data->dma_user_callback[channel](context->dev, channel, error_code);
}
static int dma_qmsi_channel_config(struct device *dev, uint32_t channel,
static int dma_qmsi_channel_config(struct device *dev, u32_t channel,
struct dma_channel_config *config)
{
qm_dma_channel_config_t qmsi_cfg;
@ -119,7 +119,7 @@ static int dma_qmsi_channel_config(struct device *dev, uint32_t channel,
return qm_dma_channel_set_config(info->instance, channel, &qmsi_cfg);
}
static int dma_qmsi_transfer_config(struct device *dev, uint32_t channel,
static int dma_qmsi_transfer_config(struct device *dev, u32_t channel,
struct dma_transfer_config *config)
{
const struct dma_qmsi_config_info *info = dev->config->config_info;
@ -128,7 +128,7 @@ static int dma_qmsi_transfer_config(struct device *dev, uint32_t channel,
(qm_dma_transfer_t *)config);
}
static int width_index(uint32_t num_bytes, uint32_t *index)
static int width_index(u32_t num_bytes, u32_t *index)
{
switch (num_bytes) {
case 1:
@ -156,7 +156,7 @@ static int width_index(uint32_t num_bytes, uint32_t *index)
return 0;
}
static int bst_index(uint32_t num_units, uint32_t *index)
static int bst_index(u32_t num_units, u32_t *index)
{
switch (num_units) {
case 1:
@ -190,14 +190,14 @@ static int bst_index(uint32_t num_units, uint32_t *index)
return 0;
}
static int dma_qmsi_chan_config(struct device *dev, uint32_t channel,
static int dma_qmsi_chan_config(struct device *dev, u32_t channel,
struct dma_config *config)
{
const struct dma_qmsi_config_info *info = dev->config->config_info;
struct dma_qmsi_driver_data *data = dev->driver_data;
qm_dma_transfer_t qmsi_transfer_cfg = { 0 };
qm_dma_channel_config_t qmsi_cfg = { 0 };
uint32_t temp = 0;
u32_t temp = 0;
int ret = 0;
if (config->block_count != 1) {
@ -250,16 +250,16 @@ static int dma_qmsi_chan_config(struct device *dev, uint32_t channel,
}
qmsi_transfer_cfg.block_size = config->head_block->block_size;
qmsi_transfer_cfg.source_address = (uint32_t *)
qmsi_transfer_cfg.source_address = (u32_t *)
config->head_block->source_address;
qmsi_transfer_cfg.destination_address = (uint32_t *)
qmsi_transfer_cfg.destination_address = (u32_t *)
config->head_block->dest_address;
return qm_dma_transfer_set_config(info->instance, channel,
&qmsi_transfer_cfg);
}
static int dma_qmsi_transfer_start(struct device *dev, uint32_t channel)
static int dma_qmsi_transfer_start(struct device *dev, u32_t channel)
{
int ret;
const struct dma_qmsi_config_info *info = dev->config->config_info;
@ -271,7 +271,7 @@ static int dma_qmsi_transfer_start(struct device *dev, uint32_t channel)
return ret;
}
static int dma_qmsi_start(struct device *dev, uint32_t channel)
static int dma_qmsi_start(struct device *dev, u32_t channel)
{
int ret;
const struct dma_qmsi_config_info *info = dev->config->config_info;
@ -283,14 +283,14 @@ static int dma_qmsi_start(struct device *dev, uint32_t channel)
return ret;
}
static int dma_qmsi_transfer_stop(struct device *dev, uint32_t channel)
static int dma_qmsi_transfer_stop(struct device *dev, u32_t channel)
{
const struct dma_qmsi_config_info *info = dev->config->config_info;
return qm_dma_transfer_terminate(info->instance, channel);
}
static int dma_qmsi_stop(struct device *dev, uint32_t channel)
static int dma_qmsi_stop(struct device *dev, u32_t channel)
{
const struct dma_qmsi_config_info *info = dev->config->config_info;
@ -308,14 +308,14 @@ static const struct dma_driver_api dma_funcs = {
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void dma_qmsi_set_power_state(struct device *dev, uint32_t power_state)
static void dma_qmsi_set_power_state(struct device *dev, u32_t power_state)
{
struct dma_qmsi_driver_data *ctx = dev->driver_data;
ctx->device_power_state = power_state;
}
static uint32_t dma_qmsi_get_power_state(struct device *dev)
static u32_t dma_qmsi_get_power_state(struct device *dev)
{
struct dma_qmsi_driver_data *ctx = dev->driver_data;
@ -364,17 +364,17 @@ static int dma_resume_device(struct device *dev)
return 0;
}
static int dma_qmsi_device_ctrl(struct device *dev, uint32_t ctrl_command,
static int dma_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return dma_suspend_device(dev);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return dma_resume_device(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = dma_qmsi_get_power_state(dev);
*((u32_t *)context) = dma_qmsi_get_power_state(dev);
}
return 0;

84
drivers/dma/dma_stm32f4x.c
View file

@ -32,37 +32,37 @@
struct dma_stm32_stream_reg {
/* Shared registers */
uint32_t lisr;
uint32_t hisr;
uint32_t lifcr;
uint32_t hifcr;
u32_t lisr;
u32_t hisr;
u32_t lifcr;
u32_t hifcr;
/* Per stream registers */
uint32_t scr;
uint32_t sndtr;
uint32_t spar;
uint32_t sm0ar;
uint32_t sm1ar;
uint32_t sfcr;
u32_t scr;
u32_t sndtr;
u32_t spar;
u32_t sm0ar;
u32_t sm1ar;
u32_t sfcr;
};
struct dma_stm32_stream {
uint32_t direction;
u32_t direction;
struct device *dev;
struct dma_stm32_stream_reg regs;
bool busy;
void (*dma_callback)(struct device *dev, uint32_t id,
void (*dma_callback)(struct device *dev, u32_t id,
int error_code);
};
static struct dma_stm32_device {
uint32_t base;
u32_t base;
struct device *clk;
struct dma_stm32_stream stream[DMA_STM32_MAX_STREAMS];
bool mem2mem;
uint8_t channel_rx;
uint8_t channel_tx;
u8_t channel_rx;
u8_t channel_tx;
} device_data[DMA_STM32_MAX_DEVS];
struct dma_stm32_config {
@ -170,23 +170,23 @@ struct dma_stm32_config {
#define DMA_STM32_SFCR_MASK (DMA_STM32_SFCR_FEIE \
| DMA_STM32_SFCR_DMDIS)
#define SYS_LOG_U32 __attribute((__unused__)) uint32_t
#define SYS_LOG_U32 __attribute((__unused__)) u32_t
static void dma_stm32_1_config(struct dma_stm32_device *ddata);
static void dma_stm32_2_config(struct dma_stm32_device *ddata);
static uint32_t dma_stm32_read(struct dma_stm32_device *ddata, uint32_t reg)
static u32_t dma_stm32_read(struct dma_stm32_device *ddata, u32_t reg)
{
return sys_read32(ddata->base + reg);
}
static void dma_stm32_write(struct dma_stm32_device *ddata,
uint32_t reg, uint32_t val)
u32_t reg, u32_t val)
{
sys_write32(val, ddata->base + reg);
}
static void dma_stm32_dump_reg(struct dma_stm32_device *ddata, uint32_t id)
static void dma_stm32_dump_reg(struct dma_stm32_device *ddata, u32_t id)
{
SYS_LOG_INF("Using stream: %d\n", id);
SYS_LOG_INF("SCR: 0x%x \t(config)\n",
@ -203,10 +203,10 @@ static void dma_stm32_dump_reg(struct dma_stm32_device *ddata, uint32_t id)
dma_stm32_read(ddata, DMA_STM32_SFCR(id)));
}
static uint32_t dma_stm32_irq_status(struct dma_stm32_device *ddata,
uint32_t id)
static u32_t dma_stm32_irq_status(struct dma_stm32_device *ddata,
u32_t id)
{
uint32_t irqs;
u32_t irqs;
if (id & 4) {
irqs = dma_stm32_read(ddata, DMA_STM32_HISR);
@ -218,7 +218,7 @@ static uint32_t dma_stm32_irq_status(struct dma_stm32_device *ddata,
}
static void dma_stm32_irq_clear(struct dma_stm32_device *ddata,
uint32_t id, uint32_t irqs)
u32_t id, u32_t irqs)
{
irqs = irqs << (((id & 2) << 3) | ((id & 1) * 6));
@ -229,12 +229,12 @@ static void dma_stm32_irq_clear(struct dma_stm32_device *ddata,
}
}
static void dma_stm32_irq_handler(void *arg, uint32_t id)
static void dma_stm32_irq_handler(void *arg, u32_t id)
{
struct device *dev = arg;
struct dma_stm32_device *ddata = dev->driver_data;
struct dma_stm32_stream *stream = &ddata->stream[id];
uint32_t irqstatus, config, sfcr;
u32_t irqstatus, config, sfcr;
irqstatus = dma_stm32_irq_status(ddata, id);
config = dma_stm32_read(ddata, DMA_STM32_SCR(id));
@ -261,9 +261,9 @@ static void dma_stm32_irq_handler(void *arg, uint32_t id)
}
static int dma_stm32_disable_stream(struct dma_stm32_device *ddata,
uint32_t id)
u32_t id)
{
uint32_t config;
u32_t config;
int count = 0;
int ret = 0;
@ -289,16 +289,16 @@ static int dma_stm32_disable_stream(struct dma_stm32_device *ddata,
return ret;
}
static int dma_stm32_config_devcpy(struct device *dev, uint32_t id,
static int dma_stm32_config_devcpy(struct device *dev, u32_t id,
struct dma_config *config)
{
struct dma_stm32_device *ddata = dev->driver_data;
struct dma_stm32_stream_reg *regs = &ddata->stream[id].regs;
uint32_t src_bus_width = dma_width_index(config->source_data_size);
uint32_t dst_bus_width = dma_width_index(config->dest_data_size);
uint32_t src_burst_size = dma_burst_index(config->source_burst_length);
uint32_t dst_burst_size = dma_burst_index(config->dest_burst_length);
u32_t src_bus_width = dma_width_index(config->source_data_size);
u32_t dst_bus_width = dma_width_index(config->dest_data_size);
u32_t src_burst_size = dma_burst_index(config->source_burst_length);
u32_t dst_burst_size = dma_burst_index(config->dest_burst_length);
enum dma_channel_direction direction = config->channel_direction;
switch (direction) {
@ -339,7 +339,7 @@ static int dma_stm32_config_devcpy(struct device *dev, uint32_t id,
return 0;
}
static int dma_stm32_config_memcpy(struct device *dev, uint32_t id)
static int dma_stm32_config_memcpy(struct device *dev, u32_t id)
{
struct dma_stm32_device *ddata = dev->driver_data;
struct dma_stm32_stream_reg *regs = &ddata->stream[id].regs;
@ -357,7 +357,7 @@ static int dma_stm32_config_memcpy(struct device *dev, uint32_t id)
return 0;
}
static int dma_stm32_config(struct device *dev, uint32_t id,
static int dma_stm32_config(struct device *dev, u32_t id,
struct dma_config *config)
{
struct dma_stm32_device *ddata = dev->driver_data;
@ -380,11 +380,11 @@ static int dma_stm32_config(struct device *dev, uint32_t id,
stream->direction = config->channel_direction;
if (stream->direction == MEMORY_TO_PERIPHERAL) {
regs->sm0ar = (uint32_t)config->head_block->source_address;
regs->spar = (uint32_t)config->head_block->dest_address;
regs->sm0ar = (u32_t)config->head_block->source_address;
regs->spar = (u32_t)config->head_block->dest_address;
} else {
regs->spar = (uint32_t)config->head_block->source_address;
regs->sm0ar = (uint32_t)config->head_block->dest_address;
regs->spar = (u32_t)config->head_block->source_address;
regs->sm0ar = (u32_t)config->head_block->dest_address;
}
if (stream->direction == MEMORY_TO_MEMORY) {
@ -398,11 +398,11 @@ static int dma_stm32_config(struct device *dev, uint32_t id,
return ret;
}
static int dma_stm32_start(struct device *dev, uint32_t id)
static int dma_stm32_start(struct device *dev, u32_t id)
{
struct dma_stm32_device *ddata = dev->driver_data;
struct dma_stm32_stream_reg *regs = &ddata->stream[id].regs;
uint32_t irqstatus;
u32_t irqstatus;
int ret;
ret = dma_stm32_disable_stream(ddata, id);
@ -432,11 +432,11 @@ static int dma_stm32_start(struct device *dev, uint32_t id)
return 0;
}
static int dma_stm32_stop(struct device *dev, uint32_t id)
static int dma_stm32_stop(struct device *dev, u32_t id)
{
struct dma_stm32_device *ddata = dev->driver_data;
struct dma_stm32_stream *stream = &ddata->stream[id];
uint32_t scr, sfcr, irqstatus;
u32_t scr, sfcr, irqstatus;
int ret;
/* Disable all IRQs */

24
drivers/flash/flash_stm32f3x.c
View file

@ -12,10 +12,10 @@
static int flash_stm32_erase(struct device *dev, off_t offset, size_t size)
{
uint32_t first_page_addr = 0;
uint32_t last_page_addr = 0;
uint16_t no_of_pages = size / CONFIG_FLASH_PAGE_SIZE;
uint16_t page_index = 0;
u32_t first_page_addr = 0;
u32_t last_page_addr = 0;
u16_t no_of_pages = size / CONFIG_FLASH_PAGE_SIZE;
u16_t page_index = 0;
/* Check offset and size alignment. */
if (((offset % CONFIG_FLASH_PAGE_SIZE) != 0) ||
@ -55,7 +55,7 @@ static int flash_stm32_erase(struct device *dev, off_t offset, size_t size)
static int flash_stm32_read(struct device *dev, off_t offset,
void *data, size_t len)
{
uint32_t address = CONFIG_FLASH_BASE_ADDRESS + offset;
u32_t address = CONFIG_FLASH_BASE_ADDRESS + offset;
__ASSERT_NO_MSG(IS_FLASH_PROGRAM_ADDRESS(address));
@ -67,12 +67,12 @@ static int flash_stm32_read(struct device *dev, off_t offset,
static int flash_stm32_write(struct device *dev, off_t offset,
const void *data, size_t len)
{
uint16_t halfword = 0;
u16_t halfword = 0;
uint32_t address =
u32_t address =
CONFIG_FLASH_BASE_ADDRESS + offset;
uint8_t remainder = 0;
u8_t remainder = 0;
if ((len % 2) != 0) {
remainder = 1;
@ -81,8 +81,8 @@ static int flash_stm32_write(struct device *dev, off_t offset,
len = len / 2;
while (len--) {
halfword = *((uint8_t *)data++);
halfword |= *((uint8_t *)data++) << 8;
halfword = *((u8_t *)data++);
halfword |= *((u8_t *)data++) << 8;
if (flash_stm32_program_halfword(dev, address, halfword)
!= FLASH_COMPLETE) {
return -EINVAL;
@ -91,7 +91,7 @@ static int flash_stm32_write(struct device *dev, off_t offset,
}
if (remainder) {
halfword = (*((uint16_t *)data)) & 0x00FF;
halfword = (*((u16_t *)data)) & 0x00FF;
if (flash_stm32_program_halfword(dev, address, halfword)
!= FLASH_COMPLETE) {
return -EINVAL;
@ -132,7 +132,7 @@ static const struct flash_driver_api flash_stm32_api = {
};
static const struct flash_stm32_dev_config flash_device_config = {
.base = (uint32_t *)FLASH_R_BASE,
.base = (u32_t *)FLASH_R_BASE,
.pclken = { .bus = STM32_CLOCK_BUS_APB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH},
};

30
drivers/flash/flash_stm32f3x.h
View file

@ -13,7 +13,7 @@
#include <flash_registers.h>
struct flash_stm32_dev_config {
uint32_t *base;
u32_t *base;
struct stm32_pclken pclken;
};
@ -29,7 +29,7 @@ struct flash_stm32_dev_data {
(volatile struct stm32_flash *)(base)
/* Flash programming timeout definition. */
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
#define FLASH_ER_PRG_TIMEOUT ((u32_t)0x000B0000)
enum flash_status {
FLASH_BUSY = 1,
@ -43,24 +43,24 @@ void flash_stm32_lock(struct device *flash);
void flash_stm32_unlock(struct device *flash);
uint8_t flash_stm32_program_halfword(struct device *flash,
uint32_t address,
uint16_t data);
u8_t flash_stm32_program_halfword(struct device *flash,
u32_t address,
u16_t data);
uint8_t flash_stm32_program_word(struct device *flash,
uint32_t address,
uint32_t data);
u8_t flash_stm32_program_word(struct device *flash,
u32_t address,
u32_t data);
void flash_stm32_read_data(void *data, uint32_t address, size_t len);
void flash_stm32_read_data(void *data, u32_t address, size_t len);
uint8_t flash_stm32_wait_for_last_operation(struct device *flash,
uint32_t timeout);
u8_t flash_stm32_wait_for_last_operation(struct device *flash,
u32_t timeout);
uint8_t flash_stm32_get_status(struct device *flash);
u8_t flash_stm32_get_status(struct device *flash);
uint8_t flash_stm32_erase_page(struct device *flash,
uint32_t page_address);
u8_t flash_stm32_erase_page(struct device *flash,
u32_t page_address);
uint8_t flash_stm32_erase_all_pages(struct device *flash);
u8_t flash_stm32_erase_all_pages(struct device *flash);
#endif /* DRIVERS_FLASH_FLASH_STM32_H_ */

50
drivers/flash/flash_stm32f3x_priv.c
View file

@ -32,11 +32,11 @@ void flash_stm32_lock(struct device *flash)
reg->cr |= FLASH_CR_LOCK;
}
uint8_t flash_stm32_program_halfword(struct device *flash,
uint32_t address,
uint16_t data)
u8_t flash_stm32_program_halfword(struct device *flash,
u32_t address,
u16_t data)
{
uint8_t status = FLASH_COMPLETE;
u8_t status = FLASH_COMPLETE;
const struct flash_stm32_dev_config *config = FLASH_CFG(flash);
@ -50,7 +50,7 @@ uint8_t flash_stm32_program_halfword(struct device *flash,
if (status == FLASH_COMPLETE) {
reg->cr |= FLASH_CR_PG;
*(volatile uint16_t *)address = data;
*(volatile u16_t *)address = data;
status = flash_stm32_wait_for_last_operation(flash,
FLASH_ER_PRG_TIMEOUT);
@ -61,11 +61,11 @@ uint8_t flash_stm32_program_halfword(struct device *flash,
return status;
}
uint8_t flash_stm32_program_word(struct device *flash,
uint32_t address,
uint32_t data)
u8_t flash_stm32_program_word(struct device *flash,
u32_t address,
u32_t data)
{
uint8_t status = FLASH_COMPLETE;
u8_t status = FLASH_COMPLETE;
const struct flash_stm32_dev_config *config = FLASH_CFG(flash);
@ -79,7 +79,7 @@ uint8_t flash_stm32_program_word(struct device *flash,
if (status == FLASH_COMPLETE) {
reg->cr |= FLASH_CR_PG;
*(volatile uint16_t *)address = (uint16_t)data;
*(volatile u16_t *)address = (u16_t)data;
status = flash_stm32_wait_for_last_operation(flash,
FLASH_ER_PRG_TIMEOUT);
@ -87,7 +87,7 @@ uint8_t flash_stm32_program_word(struct device *flash,
if (status == FLASH_COMPLETE) {
address += 2;
*(volatile uint16_t *)address = data >> 16;
*(volatile u16_t *)address = data >> 16;
status = flash_stm32_wait_for_last_operation(flash,
FLASH_ER_PRG_TIMEOUT);
@ -99,10 +99,10 @@ uint8_t flash_stm32_program_word(struct device *flash,
return status;
}
uint8_t flash_stm32_wait_for_last_operation(struct device *flash,
uint32_t timeout)
u8_t flash_stm32_wait_for_last_operation(struct device *flash,
u32_t timeout)
{
uint8_t status = FLASH_COMPLETE;
u8_t status = FLASH_COMPLETE;
/* Check for the FLASH Status */
status = flash_stm32_get_status(flash);
@ -120,9 +120,9 @@ uint8_t flash_stm32_wait_for_last_operation(struct device *flash,
return status;
}
uint8_t flash_stm32_get_status(struct device *flash)
u8_t flash_stm32_get_status(struct device *flash)
{
uint8_t status = FLASH_COMPLETE;
u8_t status = FLASH_COMPLETE;
const struct flash_stm32_dev_config *config = FLASH_CFG(flash);
@ -134,12 +134,12 @@ uint8_t flash_stm32_get_status(struct device *flash)
break;
}
if ((reg->sr & FLASH_SR_WRPERR) != (uint32_t)0x00) {
if ((reg->sr & FLASH_SR_WRPERR) != (u32_t)0x00) {
status = FLASH_ERROR_WRITE_PROTECTION;
break;
}
if ((reg->sr & FLASH_SR_PGERR) != (uint32_t)0x00) {
if ((reg->sr & FLASH_SR_PGERR) != (u32_t)0x00) {
status = FLASH_ERROR_PROGRAM;
break;
}
@ -148,10 +148,10 @@ uint8_t flash_stm32_get_status(struct device *flash)
return status;
}
uint8_t flash_stm32_erase_page(struct device *flash,
uint32_t page_address)
u8_t flash_stm32_erase_page(struct device *flash,
u32_t page_address)
{
uint8_t status = FLASH_COMPLETE;
u8_t status = FLASH_COMPLETE;
const struct flash_stm32_dev_config *config = FLASH_CFG(flash);
@ -176,9 +176,9 @@ uint8_t flash_stm32_erase_page(struct device *flash,
return status;
}
uint8_t flash_stm32_erase_all_pages(struct device *flash)
u8_t flash_stm32_erase_all_pages(struct device *flash)
{
uint8_t status = FLASH_COMPLETE;
u8_t status = FLASH_COMPLETE;
const struct flash_stm32_dev_config *config = FLASH_CFG(flash);
@ -200,9 +200,9 @@ uint8_t flash_stm32_erase_all_pages(struct device *flash)
return status;
}
void flash_stm32_read_data(void *data, uint32_t address, size_t len)
void flash_stm32_read_data(void *data, u32_t address, size_t len)
{
uint8_t *addr = INT_TO_POINTER(address);
u8_t *addr = INT_TO_POINTER(address);
memcpy(data, addr, len);
}

18
drivers/flash/flash_stm32f4x.c
View file

@ -19,14 +19,14 @@ struct flash_priv {
struct k_sem sem;
};
static bool valid_range(off_t offset, uint32_t len)
static bool valid_range(off_t offset, u32_t len)
{
return offset >= 0 && (offset + len - 1 <= STM32F4X_FLASH_END);
}
static int check_status(struct stm32f4x_flash *regs)
{
uint32_t const error =
u32_t const error =
FLASH_FLAG_WRPERR |
FLASH_FLAG_PGAERR |
FLASH_FLAG_RDERR |
@ -43,7 +43,7 @@ static int check_status(struct stm32f4x_flash *regs)
static int wait_flash_idle(struct stm32f4x_flash *regs)
{
uint32_t timeout = STM32F4X_FLASH_TIMEOUT;
u32_t timeout = STM32F4X_FLASH_TIMEOUT;
int rc;
rc = check_status(regs);
@ -62,9 +62,9 @@ static int wait_flash_idle(struct stm32f4x_flash *regs)
return 0;
}
static int write_byte(off_t offset, uint8_t val, struct stm32f4x_flash *regs)
static int write_byte(off_t offset, u8_t val, struct stm32f4x_flash *regs)
{
uint32_t tmp;
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
@ -84,7 +84,7 @@ static int write_byte(off_t offset, uint8_t val, struct stm32f4x_flash *regs)
/* flush the register write */
tmp = regs->ctrl;
*((uint8_t *) offset + CONFIG_FLASH_BASE_ADDRESS) = val;
*((u8_t *) offset + CONFIG_FLASH_BASE_ADDRESS) = val;
rc = wait_flash_idle(regs);
regs->ctrl &= (~FLASH_CR_PG);
@ -92,9 +92,9 @@ static int write_byte(off_t offset, uint8_t val, struct stm32f4x_flash *regs)
return rc;
}
static int erase_sector(uint16_t sector, struct stm32f4x_flash *regs)
static int erase_sector(u16_t sector, struct stm32f4x_flash *regs)
{
uint32_t tmp;
u32_t tmp;
int rc;
/* if the control register is locked, do not fail silently */
@ -199,7 +199,7 @@ static int flash_stm32f4x_write(struct device *dev, off_t offset,
k_sem_take(&p->sem, K_FOREVER);
for (i = 0; i < len; i++, offset++) {
rc = write_byte(offset, ((const uint8_t *) data)[i], p->regs);
rc = write_byte(offset, ((const u8_t *) data)[i], p->regs);
if (rc < 0) {
k_sem_give(&p->sem);
return rc;

8
drivers/flash/soc_flash_mcux.c
View file

@ -32,7 +32,7 @@ struct flash_priv {
static int flash_mcux_erase(struct device *dev, off_t offset, size_t len)
{
struct flash_priv *priv = dev->driver_data;
uint32_t addr;
u32_t addr;
status_t rc;
int key;
@ -49,7 +49,7 @@ static int flash_mcux_read(struct device *dev, off_t offset,
void *data, size_t len)
{
struct flash_priv *priv = dev->driver_data;
uint32_t addr;
u32_t addr;
/*
* The MCUX supports different flash chips whose valid ranges are
@ -67,14 +67,14 @@ static int flash_mcux_write(struct device *dev, off_t offset,
const void *data, size_t len)
{
struct flash_priv *priv = dev->driver_data;
uint32_t addr;
u32_t addr;
status_t rc;
int key;
addr = offset + priv->config.PFlashBlockBase;
key = irq_lock();
rc = FLASH_Program(&priv->config, addr, (uint32_t *) data, len);
rc = FLASH_Program(&priv->config, addr, (u32_t *) data, len);
irq_unlock(key);
return (rc == kStatus_Success) ? 0 : -EINVAL;

42
drivers/flash/soc_flash_nrf5.c
View file

@ -14,7 +14,7 @@
#include <flash.h>
#include <string.h>
static inline bool is_aligned_32(uint32_t data)
static inline bool is_aligned_32(u32_t data)
{
return (data & 0x3) ? false : true;
}
@ -55,11 +55,11 @@ static int flash_nrf5_read(struct device *dev, off_t addr,
static int flash_nrf5_write(struct device *dev, off_t addr,
const void *data, size_t len)
{
uint32_t addr_word;
uint32_t tmp_word;
u32_t addr_word;
u32_t tmp_word;
void *data_word;
uint32_t remaining = len;
uint32_t count = 0;
u32_t remaining = len;
u32_t count = 0;
if (!is_addr_valid(addr, len)) {
return -EINVAL;
@ -74,34 +74,34 @@ static int flash_nrf5_write(struct device *dev, off_t addr,
/* If not aligned, read first word, update and write it back */
if (!is_aligned_32(addr)) {
tmp_word = *(uint32_t *)(addr_word);
count = sizeof(uint32_t) - (addr & 0x3);
tmp_word = *(u32_t *)(addr_word);
count = sizeof(u32_t) - (addr & 0x3);
if (count > len) {
count = len;
}
memcpy((uint8_t *)&tmp_word + (addr & 0x3), data, count);
memcpy((u8_t *)&tmp_word + (addr & 0x3), data, count);
nvmc_wait_ready();
*(uint32_t *)addr_word = tmp_word;
*(u32_t *)addr_word = tmp_word;
addr_word = addr + count;
remaining -= count;
}
/* Write all the 4-byte aligned data */
data_word = (void *) data + count;
while (remaining >= sizeof(uint32_t)) {
while (remaining >= sizeof(u32_t)) {
nvmc_wait_ready();
*(uint32_t *)addr_word = *(uint32_t *)data_word;
addr_word += sizeof(uint32_t);
data_word += sizeof(uint32_t);
remaining -= sizeof(uint32_t);
*(u32_t *)addr_word = *(u32_t *)data_word;
addr_word += sizeof(u32_t);
data_word += sizeof(u32_t);
remaining -= sizeof(u32_t);
}
/* Write remaining data */
if (remaining) {
tmp_word = *(uint32_t *)(addr_word);
memcpy((uint8_t *)&tmp_word, data_word, remaining);
tmp_word = *(u32_t *)(addr_word);
memcpy((u8_t *)&tmp_word, data_word, remaining);
nvmc_wait_ready();
*(uint32_t *)addr_word = tmp_word;
*(u32_t *)addr_word = tmp_word;
}
nvmc_wait_ready();
@ -111,8 +111,8 @@ static int flash_nrf5_write(struct device *dev, off_t addr,
static int flash_nrf5_erase(struct device *dev, off_t addr, size_t size)
{
uint32_t pg_size = NRF_FICR->CODEPAGESIZE;
uint32_t n_pages = size / pg_size;
u32_t pg_size = NRF_FICR->CODEPAGESIZE;
u32_t n_pages = size / pg_size;
/* Erase can only be done per page */
if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
@ -131,8 +131,8 @@ static int flash_nrf5_erase(struct device *dev, off_t addr, size_t size)
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een << NVMC_CONFIG_WEN_Pos;
nvmc_wait_ready();
for (uint32_t i = 0; i < n_pages; i++) {
NRF_NVMC->ERASEPAGE = (uint32_t)addr + (i * pg_size);
for (u32_t i = 0; i < n_pages; i++) {
NRF_NVMC->ERASEPAGE = (u32_t)addr + (i * pg_size);
nvmc_wait_ready();
}

34
drivers/flash/soc_flash_qmsi.c
View file

@ -20,7 +20,7 @@ struct soc_flash_data {
struct k_sem sem;
#endif
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
qm_flash_context_t saved_ctx[QM_FLASH_NUM];
#endif
};
@ -41,12 +41,12 @@ static struct soc_flash_data soc_flash_context;
#define RP_GET(dev) (NULL)
#endif
static inline bool is_aligned_32(uint32_t data)
static inline bool is_aligned_32(u32_t data)
{
return (data & 0x3) ? false : true;
}
static qm_flash_region_t flash_region(uint32_t addr)
static qm_flash_region_t flash_region(u32_t addr)
{
if ((addr >= QM_FLASH_REGION_SYS_0_BASE) && (addr <
(QM_FLASH_REGION_SYS_0_BASE + CONFIG_SOC_FLASH_QMSI_SYS_SIZE))) {
@ -65,7 +65,7 @@ static qm_flash_region_t flash_region(uint32_t addr)
return QM_FLASH_REGION_NUM;
}
static uint32_t get_page_num(uint32_t addr)
static u32_t get_page_num(u32_t addr)
{
switch (flash_region(addr)) {
case QM_FLASH_REGION_SYS:
@ -101,9 +101,9 @@ static int flash_qmsi_read(struct device *dev, off_t addr,
return -EIO;
}
for (uint32_t i = 0; i < (len >> 2); i++) {
for (u32_t i = 0; i < (len >> 2); i++) {
UNALIGNED_PUT(sys_read32(addr + (i << 2)),
(uint32_t *)data + i);
(u32_t *)data + i);
}
return 0;
@ -114,7 +114,7 @@ static int flash_qmsi_write(struct device *dev, off_t addr,
{
qm_flash_t flash = QM_FLASH_0;
qm_flash_region_t reg;
uint32_t data_word = 0, offset = 0, f_addr = 0;
u32_t data_word = 0, offset = 0, f_addr = 0;
if ((!is_aligned_32(len)) || (!is_aligned_32(addr))) {
return -EINVAL;
@ -129,8 +129,8 @@ static int flash_qmsi_write(struct device *dev, off_t addr,
return -EIO;
}
for (uint32_t i = 0; i < (len >> 2); i++) {
data_word = UNALIGNED_GET((uint32_t *)data + i);
for (u32_t i = 0; i < (len >> 2); i++) {
data_word = UNALIGNED_GET((u32_t *)data + i);
reg = flash_region(addr + (i << 2));
f_addr = addr + (i << 2);
@ -172,7 +172,7 @@ static int flash_qmsi_erase(struct device *dev, off_t addr, size_t size)
{
qm_flash_t flash = QM_FLASH_0;
qm_flash_region_t reg;
uint32_t page = 0;
u32_t page = 0;
/* starting address needs to be a 2KB aligned address */
if (addr & QM_FLASH_ADDRESS_MASK) {
@ -194,7 +194,7 @@ static int flash_qmsi_erase(struct device *dev, off_t addr, size_t size)
return -EIO;
}
for (uint32_t i = 0; i < (size >> QM_FLASH_PAGE_SIZE_BITS); i++) {
for (u32_t i = 0; i < (size >> QM_FLASH_PAGE_SIZE_BITS); i++) {
page = get_page_num(addr) + i;
#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS)
if (page >= (CONFIG_SOC_FLASH_QMSI_SYS_SIZE >>
@ -256,14 +256,14 @@ static const struct flash_driver_api flash_qmsi_api = {
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void flash_qmsi_set_power_state(struct device *dev, uint32_t power_state)
static void flash_qmsi_set_power_state(struct device *dev, u32_t power_state)
{
struct soc_flash_data *ctx = dev->driver_data;
ctx->device_power_state = power_state;
}
static uint32_t flash_qmsi_get_power_state(struct device *dev)
static u32_t flash_qmsi_get_power_state(struct device *dev)
{
struct soc_flash_data *ctx = dev->driver_data;
@ -296,17 +296,17 @@ static int flash_qmsi_resume_device(struct device *dev)
return 0;
}
static int flash_qmsi_device_ctrl(struct device *dev, uint32_t ctrl_command,
static int flash_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return flash_qmsi_suspend_device(dev);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return flash_qmsi_resume_device(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = flash_qmsi_get_power_state(dev);
*((u32_t *)context) = flash_qmsi_get_power_state(dev);
}
return 0;

56
drivers/flash/spi_flash_w25qxxdv.c
View file

@ -16,8 +16,8 @@
static inline int spi_flash_wb_id(struct device *dev)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t buf[W25QXXDV_LEN_CMD_AND_ID];
uint32_t temp_data;
u8_t buf[W25QXXDV_LEN_CMD_AND_ID];
u32_t temp_data;
buf[0] = W25QXXDV_CMD_RDID;
@ -26,9 +26,9 @@ static inline int spi_flash_wb_id(struct device *dev)
return -EIO;
}
temp_data = ((uint32_t) buf[1]) << 16;
temp_data |= ((uint32_t) buf[2]) << 8;
temp_data |= (uint32_t) buf[3];
temp_data = ((u32_t) buf[1]) << 16;
temp_data |= ((u32_t) buf[2]) << 8;
temp_data |= (u32_t) buf[3];
if (temp_data != W25QXXDV_RDID_VALUE) {
return -ENODEV;
@ -59,10 +59,10 @@ static int spi_flash_wb_config(struct device *dev)
return spi_flash_wb_id(dev);
}
static int spi_flash_wb_reg_read(struct device *dev, uint8_t *data)
static int spi_flash_wb_reg_read(struct device *dev, u8_t *data)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t buf[2];
u8_t buf[2];
if (spi_transceive(driver_data->spi, data, 2, buf, 2) != 0) {
return -EIO;
@ -75,7 +75,7 @@ static int spi_flash_wb_reg_read(struct device *dev, uint8_t *data)
static inline void wait_for_flash_idle(struct device *dev)
{
uint8_t buf[2];
u8_t buf[2];
buf[0] = W25QXXDV_CMD_RDSR;
spi_flash_wb_reg_read(dev, buf);
@ -86,10 +86,10 @@ static inline void wait_for_flash_idle(struct device *dev)
}
}
static int spi_flash_wb_reg_write(struct device *dev, uint8_t *data)
static int spi_flash_wb_reg_write(struct device *dev, u8_t *data)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t buf;
u8_t buf;
wait_for_flash_idle(dev);
@ -105,7 +105,7 @@ static int spi_flash_wb_read(struct device *dev, off_t offset, void *data,
size_t len)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t *buf = driver_data->buf;
u8_t *buf = driver_data->buf;
if (len > CONFIG_SPI_FLASH_W25QXXDV_MAX_DATA_LEN || offset < 0) {
return -ENODEV;
@ -121,9 +121,9 @@ static int spi_flash_wb_read(struct device *dev, off_t offset, void *data,
wait_for_flash_idle(dev);
buf[0] = W25QXXDV_CMD_READ;
buf[1] = (uint8_t) (offset >> 16);
buf[2] = (uint8_t) (offset >> 8);
buf[3] = (uint8_t) offset;
buf[1] = (u8_t) (offset >> 16);
buf[2] = (u8_t) (offset >> 8);
buf[3] = (u8_t) offset;
memset(buf + W25QXXDV_LEN_CMD_ADDRESS, 0, len);
@ -144,7 +144,7 @@ static int spi_flash_wb_write(struct device *dev, off_t offset,
const void *data, size_t len)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t *buf = driver_data->buf;
u8_t *buf = driver_data->buf;
if (len > CONFIG_SPI_FLASH_W25QXXDV_MAX_DATA_LEN || offset < 0) {
return -ENOTSUP;
@ -170,9 +170,9 @@ static int spi_flash_wb_write(struct device *dev, off_t offset,
wait_for_flash_idle(dev);
buf[0] = W25QXXDV_CMD_PP;
buf[1] = (uint8_t) (offset >> 16);
buf[2] = (uint8_t) (offset >> 8);
buf[3] = (uint8_t) offset;
buf[1] = (u8_t) (offset >> 16);
buf[2] = (u8_t) (offset >> 8);
buf[3] = (u8_t) offset;
memcpy(buf + W25QXXDV_LEN_CMD_ADDRESS, data, len);
@ -193,7 +193,7 @@ static int spi_flash_wb_write(struct device *dev, off_t offset,
static int spi_flash_wb_write_protection_set(struct device *dev, bool enable)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t buf = 0;
u8_t buf = 0;
k_sem_take(&driver_data->sem, K_FOREVER);
@ -224,9 +224,9 @@ static inline int spi_flash_wb_erase_internal(struct device *dev,
off_t offset, size_t size)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t buf[W25QXXDV_LEN_CMD_ADDRESS];
uint8_t erase_opcode;
uint32_t len;
u8_t buf[W25QXXDV_LEN_CMD_ADDRESS];
u8_t erase_opcode;
u32_t len;
if (offset < 0) {
return -ENOTSUP;
@ -263,9 +263,9 @@ static inline int spi_flash_wb_erase_internal(struct device *dev,
}
buf[0] = erase_opcode;
buf[1] = (uint8_t) (offset >> 16);
buf[2] = (uint8_t) (offset >> 8);
buf[3] = (uint8_t) offset;
buf[1] = (u8_t) (offset >> 16);
buf[2] = (u8_t) (offset >> 8);
buf[3] = (u8_t) offset;
/* Assume write protection has been disabled. Note that w25qxxdv
* flash automatically turns on write protection at the completion
@ -277,10 +277,10 @@ static inline int spi_flash_wb_erase_internal(struct device *dev,
static int spi_flash_wb_erase(struct device *dev, off_t offset, size_t size)
{
struct spi_flash_data *const driver_data = dev->driver_data;
uint8_t *buf = driver_data->buf;
u8_t *buf = driver_data->buf;
int ret = 0;
uint32_t new_offset = offset;
uint32_t size_remaining = size;
u32_t new_offset = offset;
u32_t size_remaining = size;
if ((offset < 0) || ((offset & W25QXXDV_SECTOR_MASK) != 0) ||
((size + offset) > CONFIG_SPI_FLASH_W25QXXDV_FLASH_SIZE) ||

2
drivers/flash/spi_flash_w25qxxdv.h
View file

@ -16,7 +16,7 @@
struct spi_flash_data {
struct device *spi;
uint8_t buf[CONFIG_SPI_FLASH_W25QXXDV_MAX_DATA_LEN +
u8_t buf[CONFIG_SPI_FLASH_W25QXXDV_MAX_DATA_LEN +
W25QXXDV_LEN_CMD_ADDRESS];
struct k_sem sem;
};

18
drivers/gpio/gpio_atmel_sam3.c
View file

@ -34,7 +34,7 @@ struct gpio_sam3_runtime {
sys_slist_t cb;
};
static void _config(struct device *dev, uint32_t mask, int flags)
static void _config(struct device *dev, u32_t mask, int flags)
{
const struct gpio_sam3_config *cfg = dev->config->config_info;
@ -107,7 +107,7 @@ static void _config(struct device *dev, uint32_t mask, int flags)
* @return 0 if successful, failed otherwise
*/
static int gpio_sam3_config(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
@ -134,7 +134,7 @@ static int gpio_sam3_config(struct device *dev, int access_op,
* @return 0 if successful, failed otherwise
*/
static int gpio_sam3_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value)
u32_t pin, u32_t value)
{
const struct gpio_sam3_config *cfg = dev->config->config_info;
@ -175,7 +175,7 @@ static int gpio_sam3_write(struct device *dev, int access_op,
* @return 0 if successful, failed otherwise
*/
static int gpio_sam3_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
u32_t pin, u32_t *value)
{
const struct gpio_sam3_config *cfg = dev->config->config_info;
@ -199,7 +199,7 @@ static void gpio_sam3_isr(void *arg)
struct device *dev = (struct device *)arg;
const struct gpio_sam3_config *cfg = dev->config->config_info;
struct gpio_sam3_runtime *context = dev->driver_data;
uint32_t int_stat;
u32_t int_stat;
int_stat = cfg->port->isr;
@ -218,10 +218,10 @@ static int gpio_sam3_manage_callback(struct device *dev,
}
static int gpio_sam3_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
const struct gpio_sam3_config *cfg = dev->config->config_info;
uint32_t mask;
u32_t mask;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
@ -240,10 +240,10 @@ static int gpio_sam3_enable_callback(struct device *dev,
}
static int gpio_sam3_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
const struct gpio_sam3_config *cfg = dev->config->config_info;
uint32_t mask;
u32_t mask;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:

16
drivers/gpio/gpio_cc32xx.c
View file

@ -42,7 +42,7 @@ struct gpio_cc32xx_data {
/* list of registered callbacks */
sys_slist_t callbacks;
/* callback enable pin bitmask */
uint32_t pin_callback_enables;
u32_t pin_callback_enables;
};
#define DEV_CFG(dev) \
@ -51,7 +51,7 @@ struct gpio_cc32xx_data {
((struct gpio_cc32xx_data *)(dev)->driver_data)
static inline int gpio_cc32xx_config(struct device *port,
int access_op, uint32_t pin, int flags)
int access_op, u32_t pin, int flags)
{
const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
unsigned long port_base = gpio_config->port_base;
@ -92,7 +92,7 @@ static inline int gpio_cc32xx_config(struct device *port,
}
static inline int gpio_cc32xx_write(struct device *port,
int access_op, uint32_t pin, uint32_t value)
int access_op, u32_t pin, u32_t value)
{
const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
unsigned long port_base = gpio_config->port_base;
@ -111,7 +111,7 @@ static inline int gpio_cc32xx_write(struct device *port,
}
static inline int gpio_cc32xx_read(struct device *port,
int access_op, uint32_t pin, uint32_t *value)
int access_op, u32_t pin, u32_t *value)
{
const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
unsigned long port_base = gpio_config->port_base;
@ -142,7 +142,7 @@ static int gpio_cc32xx_manage_callback(struct device *dev,
static int gpio_cc32xx_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_cc32xx_data *data = DEV_DATA(dev);
@ -157,7 +157,7 @@ static int gpio_cc32xx_enable_callback(struct device *dev,
static int gpio_cc32xx_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_cc32xx_data *data = DEV_DATA(dev);
@ -175,10 +175,10 @@ static void gpio_cc32xx_port_isr(void *arg)
struct device *dev = arg;
const struct gpio_cc32xx_config *config = DEV_CFG(dev);
struct gpio_cc32xx_data *data = DEV_DATA(dev);
uint32_t enabled_int, int_status;
u32_t enabled_int, int_status;
/* See which interrupts triggered: */
int_status = (uint32_t)MAP_GPIOIntStatus(config->port_base, 1);
int_status = (u32_t)MAP_GPIOIntStatus(config->port_base, 1);
enabled_int = int_status & data->pin_callback_enables;

20
drivers/gpio/gpio_cmsdk_ahb.c
View file

@ -38,7 +38,7 @@ struct gpio_cmsdk_ahb_dev_data {
sys_slist_t gpio_cb;
};
static void cmsdk_ahb_gpio_config(struct device *dev, uint32_t mask, int flags)
static void cmsdk_ahb_gpio_config(struct device *dev, u32_t mask, int flags)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
@ -105,7 +105,7 @@ static void cmsdk_ahb_gpio_config(struct device *dev, uint32_t mask, int flags)
* @return 0 if successful, failed otherwise
*/
static int gpio_cmsdk_ahb_config(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
@ -132,10 +132,10 @@ static int gpio_cmsdk_ahb_config(struct device *dev, int access_op,
* @return 0 if successful, failed otherwise
*/
static int gpio_cmsdk_ahb_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value)
u32_t pin, u32_t value)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
uint32_t key;
u32_t key;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
@ -186,7 +186,7 @@ static int gpio_cmsdk_ahb_write(struct device *dev, int access_op,
* @return 0 if successful, failed otherwise
*/
static int gpio_cmsdk_ahb_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
u32_t pin, u32_t *value)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
@ -210,7 +210,7 @@ static void gpio_cmsdk_ahb_isr(void *arg)
struct device *dev = (struct device *)arg;
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;
uint32_t int_stat;
u32_t int_stat;
int_stat = cfg->port->intstatus;
@ -232,10 +232,10 @@ static int gpio_cmsdk_ahb_manage_callback(struct device *dev,
}
static int gpio_cmsdk_ahb_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
uint32_t mask;
u32_t mask;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
@ -254,10 +254,10 @@ static int gpio_cmsdk_ahb_enable_callback(struct device *dev,
}
static int gpio_cmsdk_ahb_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
uint32_t mask;
u32_t mask;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:

36
drivers/gpio/gpio_cmsdk_ahb.h
View file

@ -15,41 +15,41 @@ extern "C" {
/* ARM LTD CMSDK AHB General Purpose Input/Output (GPIO) */
struct gpio_cmsdk_ahb {
/* Offset: 0x000 (r/w) data register */
volatile uint32_t data;
volatile u32_t data;
/* Offset: 0x004 (r/w) data output latch register */
volatile uint32_t dataout;
volatile uint32_t reserved0[2];
volatile u32_t dataout;
volatile u32_t reserved0[2];
/* Offset: 0x010 (r/w) output enable set register */
volatile uint32_t outenableset;
volatile u32_t outenableset;
/* Offset: 0x014 (r/w) output enable clear register */
volatile uint32_t outenableclr;
volatile u32_t outenableclr;
/* Offset: 0x018 (r/w) alternate function set register */
volatile uint32_t altfuncset;
volatile u32_t altfuncset;
/* Offset: 0x01c (r/w) alternate function clear register */
volatile uint32_t altfuncclr;
volatile u32_t altfuncclr;
/* Offset: 0x020 (r/w) interrupt enable set register */
volatile uint32_t intenset;
volatile u32_t intenset;
/* Offset: 0x024 (r/w) interrupt enable clear register */
volatile uint32_t intenclr;
volatile u32_t intenclr;
/* Offset: 0x028 (r/w) interrupt type set register */
volatile uint32_t inttypeset;
volatile u32_t inttypeset;
/* Offset: 0x02c (r/w) interrupt type clear register */
volatile uint32_t inttypeclr;
volatile u32_t inttypeclr;
/* Offset: 0x030 (r/w) interrupt polarity set register */
volatile uint32_t intpolset;
volatile u32_t intpolset;
/* Offset: 0x034 (r/w) interrupt polarity clear register */
volatile uint32_t intpolclr;
volatile u32_t intpolclr;
union {
/* Offset: 0x038 (r/ ) interrupt status register */
volatile uint32_t intstatus;
volatile u32_t intstatus;
/* Offset: 0x038 ( /w) interrupt clear register */
volatile uint32_t intclear;
volatile u32_t intclear;
};
volatile uint32_t reserved1[241];
volatile u32_t reserved1[241];
/* Offset: 0x400 - 0x7fc lower byte masked access register (r/w) */
volatile uint32_t lb_masked[256];
volatile u32_t lb_masked[256];
/* Offset: 0x800 - 0xbfc upper byte masked access register (r/w) */
volatile uint32_t ub_masked[256];
volatile u32_t ub_masked[256];
};
#ifdef __cplusplus

86
drivers/gpio/gpio_dw.c
View file

@ -35,19 +35,19 @@
* Other architectures as ARM and x86 configure IP through MMIO registers
*/
#ifdef GPIO_DW_IO_ACCESS
static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset)
static inline u32_t dw_read(u32_t base_addr, u32_t offset)
{
return sys_in32(base_addr + offset);
}
static inline void dw_write(uint32_t base_addr, uint32_t offset,
uint32_t val)
static inline void dw_write(u32_t base_addr, u32_t offset,
u32_t val)
{
sys_out32(val, base_addr + offset);
}
static void dw_set_bit(uint32_t base_addr, uint32_t offset,
uint32_t bit, uint8_t value)
static void dw_set_bit(u32_t base_addr, u32_t offset,
u32_t bit, u8_t value)
{
if (!value) {
sys_io_clear_bit(base_addr + offset, bit);
@ -56,19 +56,19 @@ static void dw_set_bit(uint32_t base_addr, uint32_t offset,
}
}
#else
static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset)
static inline u32_t dw_read(u32_t base_addr, u32_t offset)
{
return sys_read32(base_addr + offset);
}
static inline void dw_write(uint32_t base_addr, uint32_t offset,
uint32_t val)
static inline void dw_write(u32_t base_addr, u32_t offset,
u32_t val)
{
sys_write32(val, base_addr + offset);
}
static void dw_set_bit(uint32_t base_addr, uint32_t offset,
uint32_t bit, uint8_t value)
static void dw_set_bit(u32_t base_addr, u32_t offset,
u32_t bit, u8_t value)
{
if (!value) {
sys_clear_bit(base_addr + offset, bit);
@ -114,12 +114,12 @@ static inline void _gpio_dw_clock_off(struct device *port)
#endif
#ifdef CONFIG_SOC_QUARK_SE_C1000_SS
static inline void dw_set_both_edges(uint32_t base_addr, uint32_t pin)
static inline void dw_set_both_edges(u32_t base_addr, u32_t pin)
{
ARG_UNUSED(base_addr);
ARG_UNUSED(pin);
}
static inline int dw_base_to_block_base(uint32_t base_addr)
static inline int dw_base_to_block_base(u32_t base_addr)
{
return base_addr;
}
@ -129,17 +129,17 @@ static inline int dw_interrupt_support(const struct gpio_dw_config *config)
return 1;
}
#else
static inline void dw_set_both_edges(uint32_t base_addr, uint32_t pin)
static inline void dw_set_both_edges(u32_t base_addr, u32_t pin)
{
dw_set_bit(base_addr, INT_BOTHEDGE, pin, 1);
}
static inline int dw_base_to_block_base(uint32_t base_addr)
static inline int dw_base_to_block_base(u32_t base_addr)
{
return (base_addr & 0xFFFFFFC0);
}
static inline int dw_derive_port_from_base(uint32_t base_addr)
static inline int dw_derive_port_from_base(u32_t base_addr)
{
uint32_t port = (base_addr & 0x3f) / 12;
u32_t port = (base_addr & 0x3f) / 12;
return port;
}
static inline int dw_interrupt_support(const struct gpio_dw_config *config)
@ -149,12 +149,12 @@ static inline int dw_interrupt_support(const struct gpio_dw_config *config)
#endif
static inline void dw_interrupt_config(struct device *port, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
struct gpio_dw_runtime *context = port->driver_data;
const struct gpio_dw_config *config = port->config->config_info;
uint32_t base_addr = dw_base_to_block_base(context->base_addr);
uint8_t flag_is_set;
u32_t base_addr = dw_base_to_block_base(context->base_addr);
u8_t flag_is_set;
ARG_UNUSED(access_op);
@ -188,12 +188,12 @@ static inline void dw_interrupt_config(struct device *port, int access_op,
}
static inline void dw_pin_config(struct device *port,
uint32_t pin, int flags)
u32_t pin, int flags)
{
struct gpio_dw_runtime *context = port->driver_data;
const struct gpio_dw_config *config = port->config->config_info;
uint32_t base_addr = dw_base_to_block_base(context->base_addr);
uint32_t port_base_addr = context->base_addr;
u32_t base_addr = dw_base_to_block_base(context->base_addr);
u32_t port_base_addr = context->base_addr;
int interrupt_support = dw_interrupt_support(config);
if (interrupt_support) {
@ -220,7 +220,7 @@ static inline void dw_port_config(struct device *port, int flags)
}
static inline int gpio_dw_config(struct device *port, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
return -EINVAL;
@ -235,10 +235,10 @@ static inline int gpio_dw_config(struct device *port, int access_op,
}
static inline int gpio_dw_write(struct device *port, int access_op,
uint32_t pin, uint32_t value)
u32_t pin, u32_t value)
{
struct gpio_dw_runtime *context = port->driver_data;
uint32_t base_addr = context->base_addr;
u32_t base_addr = context->base_addr;
if (GPIO_ACCESS_BY_PIN == access_op) {
dw_set_bit(base_addr, SWPORTA_DR, pin, value);
@ -250,12 +250,12 @@ static inline int gpio_dw_write(struct device *port, int access_op,
}
static inline int gpio_dw_read(struct device *port, int access_op,
uint32_t pin, uint32_t *value)
u32_t pin, u32_t *value)
{
struct gpio_dw_runtime *context = port->driver_data;
uint32_t base_addr = context->base_addr;
u32_t base_addr = context->base_addr;
#ifndef CONFIG_SOC_QUARK_SE_C1000_SS
uint32_t ext_port = EXT_PORTA;
u32_t ext_port = EXT_PORTA;
#endif
#ifdef CONFIG_SOC_QUARK_SE_C1000_SS
@ -297,11 +297,11 @@ static inline int gpio_dw_manage_callback(struct device *port,
}
static inline int gpio_dw_enable_callback(struct device *port, int access_op,
uint32_t pin)
u32_t pin)
{
const struct gpio_dw_config *config = port->config->config_info;
struct gpio_dw_runtime *context = port->driver_data;
uint32_t base_addr = dw_base_to_block_base(context->base_addr);
u32_t base_addr = dw_base_to_block_base(context->base_addr);
if (GPIO_ACCESS_BY_PIN == access_op) {
dw_write(base_addr, PORTA_EOI, BIT(pin));
@ -315,11 +315,11 @@ static inline int gpio_dw_enable_callback(struct device *port, int access_op,
}
static inline int gpio_dw_disable_callback(struct device *port, int access_op,
uint32_t pin)
u32_t pin)
{
const struct gpio_dw_config *config = port->config->config_info;
struct gpio_dw_runtime *context = port->driver_data;
uint32_t base_addr = dw_base_to_block_base(context->base_addr);
u32_t base_addr = dw_base_to_block_base(context->base_addr);
if (GPIO_ACCESS_BY_PIN == access_op) {
dw_set_bit(base_addr, INTMASK, pin, 1);
@ -331,14 +331,14 @@ static inline int gpio_dw_disable_callback(struct device *port, int access_op,
}
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void gpio_dw_set_power_state(struct device *port, uint32_t power_state)
static void gpio_dw_set_power_state(struct device *port, u32_t power_state)
{
struct gpio_dw_runtime *context = port->driver_data;
context->device_power_state = power_state;
}
static uint32_t gpio_dw_get_power_state(struct device *port)
static u32_t gpio_dw_get_power_state(struct device *port)
{
struct gpio_dw_runtime *context = port->driver_data;
@ -364,17 +364,17 @@ static inline int gpio_dw_resume_from_suspend_port(struct device *port)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int gpio_dw_device_ctrl(struct device *port, uint32_t ctrl_command,
static int gpio_dw_device_ctrl(struct device *port, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return gpio_dw_suspend_port(port);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return gpio_dw_resume_from_suspend_port(port);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = gpio_dw_get_power_state(port);
*((u32_t *)context) = gpio_dw_get_power_state(port);
return 0;
}
return 0;
@ -385,12 +385,12 @@ static int gpio_dw_device_ctrl(struct device *port, uint32_t ctrl_command,
#endif
#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_D2000)
static inline void gpio_dw_unmask_int(uint32_t mask_addr)
static inline void gpio_dw_unmask_int(u32_t mask_addr)
{
sys_write32(sys_read32(mask_addr) & INT_UNMASK_IA, mask_addr);
}
#elif CONFIG_SOC_QUARK_SE_C1000_SS
static inline void gpio_dw_unmask_int(uint32_t mask_addr)
static inline void gpio_dw_unmask_int(u32_t mask_addr)
{
sys_write32(sys_read32(mask_addr) & INT_ENABLE_ARC, mask_addr);
}
@ -402,8 +402,8 @@ static void gpio_dw_isr(void *arg)
{
struct device *port = (struct device *)arg;
struct gpio_dw_runtime *context = port->driver_data;
uint32_t base_addr = dw_base_to_block_base(context->base_addr);
uint32_t int_status;
u32_t base_addr = dw_base_to_block_base(context->base_addr);
u32_t int_status;
int_status = dw_read(base_addr, INTSTATUS);
@ -460,7 +460,7 @@ static int gpio_dw_initialize(struct device *port)
{
struct gpio_dw_runtime *context = port->driver_data;
const struct gpio_dw_config *config = port->config->config_info;
uint32_t base_addr;
u32_t base_addr;
if (!gpio_dw_setup(port)) {
port->driver_api = NULL;

8
drivers/gpio/gpio_dw.h
View file

@ -23,8 +23,8 @@ extern "C" {
typedef void (*gpio_config_irq_t)(struct device *port);
struct gpio_dw_config {
uint32_t bits;
uint32_t irq_num; /* set to 0 if GPIO port cannot interrupt */
u32_t bits;
u32_t irq_num; /* set to 0 if GPIO port cannot interrupt */
gpio_config_irq_t config_func;
#ifdef CONFIG_GPIO_DW_SHARED_IRQ
@ -37,7 +37,7 @@ struct gpio_dw_config {
};
struct gpio_dw_runtime {
uint32_t base_addr;
u32_t base_addr;
#ifdef CONFIG_PCI
struct pci_dev_info pci_dev;
#endif /* CONFIG_PCI */
@ -47,7 +47,7 @@ struct gpio_dw_runtime {
#endif
sys_slist_t callbacks;
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
#endif
};

18
drivers/gpio/gpio_fe310.c
View file

@ -41,8 +41,8 @@ struct gpio_fe310_t {
};
struct gpio_fe310_config {
uint32_t gpio_base_addr;
uint32_t gpio_irq_base;
u32_t gpio_base_addr;
u32_t gpio_irq_base;
fe310_cfg_func_t gpio_cfg_func;
};
@ -101,7 +101,7 @@ static void gpio_fe310_irq_handler(void *arg)
*/
static int gpio_fe310_config(struct device *dev,
int access_op,
uint32_t pin,
u32_t pin,
int flags)
{
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
@ -209,8 +209,8 @@ static int gpio_fe310_config(struct device *dev,
*/
static int gpio_fe310_write(struct device *dev,
int access_op,
uint32_t pin,
uint32_t value)
u32_t pin,
u32_t value)
{
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
@ -244,8 +244,8 @@ static int gpio_fe310_write(struct device *dev,
*/
static int gpio_fe310_read(struct device *dev,
int access_op,
uint32_t pin,
uint32_t *value)
u32_t pin,
u32_t *value)
{
volatile struct gpio_fe310_t *gpio = DEV_GPIO(dev);
@ -281,7 +281,7 @@ static int gpio_fe310_manage_callback(struct device *dev,
static int gpio_fe310_enable_callback(struct device *dev,
int access_op,
uint32_t pin)
u32_t pin)
{
const struct gpio_fe310_config *cfg = DEV_GPIO_CFG(dev);
@ -299,7 +299,7 @@ static int gpio_fe310_enable_callback(struct device *dev,
static int gpio_fe310_disable_callback(struct device *dev,
int access_op,
uint32_t pin)
u32_t pin)
{
const struct gpio_fe310_config *cfg = DEV_GPIO_CFG(dev);

20
drivers/gpio/gpio_mcux.c
View file

@ -24,19 +24,19 @@ struct gpio_mcux_data {
/* port ISR callback routine address */
sys_slist_t callbacks;
/* pin callback routine enable flags, by pin number */
uint32_t pin_callback_enables;
u32_t pin_callback_enables;
};
static int gpio_mcux_configure(struct device *dev,
int access_op, uint32_t pin, int flags)
int access_op, u32_t pin, int flags)
{
const struct gpio_mcux_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base;
PORT_Type *port_base = config->port_base;
port_interrupt_t port_interrupt = 0;
uint32_t mask = 0;
uint32_t pcr = 0;
uint8_t i;
u32_t mask = 0;
u32_t pcr = 0;
u8_t i;
/* Check for an invalid pin configuration */
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
@ -125,7 +125,7 @@ static int gpio_mcux_configure(struct device *dev,
}
static int gpio_mcux_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value)
int access_op, u32_t pin, u32_t value)
{
const struct gpio_mcux_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base;
@ -153,7 +153,7 @@ static int gpio_mcux_write(struct device *dev,
}
static int gpio_mcux_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
int access_op, u32_t pin, u32_t *value)
{
const struct gpio_mcux_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base;
@ -180,7 +180,7 @@ static int gpio_mcux_manage_callback(struct device *dev,
}
static int gpio_mcux_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_mcux_data *data = dev->driver_data;
@ -194,7 +194,7 @@ static int gpio_mcux_enable_callback(struct device *dev,
}
static int gpio_mcux_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_mcux_data *data = dev->driver_data;
@ -212,7 +212,7 @@ static void gpio_mcux_port_isr(void *arg)
struct device *dev = (struct device *)arg;
const struct gpio_mcux_config *config = dev->config->config_info;
struct gpio_mcux_data *data = dev->driver_data;
uint32_t enabled_int, int_status;
u32_t enabled_int, int_status;
int_status = config->port_base->ISFR;
enabled_int = int_status & data->pin_callback_enables;

14
drivers/gpio/gpio_mmio32.c
View file

@ -30,7 +30,7 @@
#include <errno.h>
static int gpio_mmio32_config(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
struct gpio_mmio32_context *context = dev->driver_data;
const struct gpio_mmio32_config *config = context->config;
@ -58,13 +58,13 @@ static int gpio_mmio32_config(struct device *dev, int access_op,
}
static int gpio_mmio32_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value)
u32_t pin, u32_t value)
{
struct gpio_mmio32_context *context = dev->driver_data;
const struct gpio_mmio32_config *config = context->config;
volatile uint32_t *reg = config->reg;
uint32_t mask = config->mask;
uint32_t invert = context->invert;
volatile u32_t *reg = config->reg;
u32_t mask = config->mask;
u32_t invert = context->invert;
unsigned int key;
if (access_op == GPIO_ACCESS_BY_PIN) {
@ -86,11 +86,11 @@ static int gpio_mmio32_write(struct device *dev, int access_op,
}
static int gpio_mmio32_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
u32_t pin, u32_t *value)
{
struct gpio_mmio32_context *context = dev->driver_data;
const struct gpio_mmio32_config *config = context->config;
uint32_t bits;
u32_t bits;
bits = (*config->reg ^ context->invert) & config->mask;
if (access_op == GPIO_ACCESS_BY_PIN) {

82
drivers/gpio/gpio_nrf5.c
View file

@ -30,59 +30,59 @@
/* GPIO structure for nRF5X. More detailed description of each register can be found in nrf5X.h */
struct _gpio {
__I uint32_t RESERVED0[321];
__IO uint32_t OUT;
__IO uint32_t OUTSET;
__IO uint32_t OUTCLR;
__I u32_t RESERVED0[321];
__IO u32_t OUT;
__IO u32_t OUTSET;
__IO u32_t OUTCLR;
__I uint32_t IN;
__IO uint32_t DIR;
__IO uint32_t DIRSET;
__IO uint32_t DIRCLR;
__IO uint32_t LATCH;
__IO uint32_t DETECTMODE;
__I uint32_t RESERVED1[118];
__IO uint32_t PIN_CNF[32];
__I u32_t IN;
__IO u32_t DIR;
__IO u32_t DIRSET;
__IO u32_t DIRCLR;
__IO u32_t LATCH;
__IO u32_t DETECTMODE;
__I u32_t RESERVED1[118];
__IO u32_t PIN_CNF[32];
};
/* GPIOTE structure for nRF5X. More detailed description of each register can be found in nrf5X.h */
struct _gpiote {
__O uint32_t TASKS_OUT[8];
__I uint32_t RESERVED0[4];
__O u32_t TASKS_OUT[8];
__I u32_t RESERVED0[4];
__O uint32_t TASKS_SET[8];
__I uint32_t RESERVED1[4];
__O u32_t TASKS_SET[8];
__I u32_t RESERVED1[4];
__O uint32_t TASKS_CLR[8];
__I uint32_t RESERVED2[32];
__IO uint32_t EVENTS_IN[8];
__I uint32_t RESERVED3[23];
__IO uint32_t EVENTS_PORT;
__I uint32_t RESERVED4[97];
__IO uint32_t INTENSET;
__IO uint32_t INTENCLR;
__I uint32_t RESERVED5[129];
__IO uint32_t CONFIG[8];
__O u32_t TASKS_CLR[8];
__I u32_t RESERVED2[32];
__IO u32_t EVENTS_IN[8];
__I u32_t RESERVED3[23];
__IO u32_t EVENTS_PORT;
__I u32_t RESERVED4[97];
__IO u32_t INTENSET;
__IO u32_t INTENCLR;
__I u32_t RESERVED5[129];
__IO u32_t CONFIG[8];
};
/** Configuration data */
struct gpio_nrf5_config {
/* GPIO module base address */
uint32_t gpio_base_addr;
u32_t gpio_base_addr;
/* Port Control module base address */
uint32_t port_base_addr;
u32_t port_base_addr;
/* GPIO Task Event base address */
uint32_t gpiote_base_addr;
u32_t gpiote_base_addr;
};
struct gpio_nrf5_data {
/* list of registered callbacks */
sys_slist_t callbacks;
/* pin callback routine enable flags, by pin number */
uint32_t pin_callback_enables;
u32_t pin_callback_enables;
/*@todo: move GPIOTE channel management to a separate module */
uint32_t gpiote_chan_mask;
u32_t gpiote_chan_mask;
};
/* convenience defines for GPIO */
@ -126,7 +126,7 @@ struct gpio_nrf5_data {
#define GPIOTE_CFG_PIN_GET(config) ((config & GPIOTE_CONFIG_PSEL_Msk) >> \
GPIOTE_CONFIG_PSEL_Pos)
static int gpiote_find_channel(struct device *dev, uint32_t pin)
static int gpiote_find_channel(struct device *dev, u32_t pin)
{
volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
@ -146,10 +146,10 @@ static int gpiote_find_channel(struct device *dev, uint32_t pin)
* @brief Configure pin or port
*/
static int gpio_nrf5_config(struct device *dev,
int access_op, uint32_t pin, int flags)
int access_op, u32_t pin, int flags)
{
/* Note D0D1 is not supported so we switch to S0S1. */
static const uint32_t drive_strength[4][4] = {
static const u32_t drive_strength[4][4] = {
{GPIO_DRIVE_S0S1, GPIO_DRIVE_S0H1, 0, GPIO_DRIVE_S0D1},
{GPIO_DRIVE_H0S1, GPIO_DRIVE_H0H1, 0, GPIO_DRIVE_H0D1},
{0, 0, 0, 0},
@ -162,7 +162,7 @@ static int gpio_nrf5_config(struct device *dev,
if (access_op == GPIO_ACCESS_BY_PIN) {
/* Check pull */
uint8_t pull = GPIO_PULL_DISABLE;
u8_t pull = GPIO_PULL_DISABLE;
int ds_low = (flags & GPIO_DS_LOW_MASK) >> GPIO_DS_LOW_POS;
int ds_high = (flags & GPIO_DS_HIGH_MASK) >> GPIO_DS_HIGH_POS;
@ -201,7 +201,7 @@ static int gpio_nrf5_config(struct device *dev,
}
if (flags & GPIO_INT) {
uint32_t config = 0;
u32_t config = 0;
if (flags & GPIO_INT_EDGE) {
if (flags & GPIO_INT_DOUBLE_EDGE) {
@ -242,7 +242,7 @@ static int gpio_nrf5_config(struct device *dev,
}
static int gpio_nrf5_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
int access_op, u32_t pin, u32_t *value)
{
volatile struct _gpio *gpio = GPIO_STRUCT(dev);
@ -255,7 +255,7 @@ static int gpio_nrf5_read(struct device *dev,
}
static int gpio_nrf5_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value)
int access_op, u32_t pin, u32_t value)
{
volatile struct _gpio *gpio = GPIO_STRUCT(dev);
@ -283,7 +283,7 @@ static int gpio_nrf5_manage_callback(struct device *dev,
static int gpio_nrf5_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
@ -310,7 +310,7 @@ static int gpio_nrf5_enable_callback(struct device *dev,
static int gpio_nrf5_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
@ -345,7 +345,7 @@ static void gpio_nrf5_port_isr(void *arg)
struct device *dev = arg;
volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
uint32_t enabled_int, int_status = 0;
u32_t enabled_int, int_status = 0;
int i;
for (i = 0; i < GPIOTE_CHAN_COUNT; i++) {

42
drivers/gpio/gpio_pcal9535a.c
View file

@ -75,7 +75,7 @@ static inline int _has_i2c_master(struct device *dev)
*
* @return 0 if successful, failed otherwise.
*/
static int _read_port_regs(struct device *dev, uint8_t reg,
static int _read_port_regs(struct device *dev, u8_t reg,
union gpio_pcal9535a_port_data *buf)
{
const struct gpio_pcal9535a_config * const config =
@ -83,7 +83,7 @@ static int _read_port_regs(struct device *dev, uint8_t reg,
struct gpio_pcal9535a_drv_data * const drv_data =
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
struct device * const i2c_master = drv_data->i2c_master;
uint16_t i2c_addr = config->i2c_slave_addr;
u16_t i2c_addr = config->i2c_slave_addr;
int ret;
ret = i2c_burst_read(i2c_master, i2c_addr, reg, buf->byte, 2);
@ -111,7 +111,7 @@ error:
*
* @return 0 if successful, failed otherwise.
*/
static int _write_port_regs(struct device *dev, uint8_t reg,
static int _write_port_regs(struct device *dev, u8_t reg,
union gpio_pcal9535a_port_data *buf)
{
const struct gpio_pcal9535a_config * const config =
@ -119,7 +119,7 @@ static int _write_port_regs(struct device *dev, uint8_t reg,
struct gpio_pcal9535a_drv_data * const drv_data =
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
struct device * const i2c_master = drv_data->i2c_master;
uint16_t i2c_addr = config->i2c_slave_addr;
u16_t i2c_addr = config->i2c_slave_addr;
int ret;
SYS_LOG_DBG("PCAL9535A[0x%X]: Write: REG[0x%X] = 0x%X, REG[0x%X] = "
@ -146,13 +146,13 @@ static int _write_port_regs(struct device *dev, uint8_t reg,
* @return 0 if successful, failed otherwise
*/
static int _setup_pin_dir(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
struct gpio_pcal9535a_drv_data * const drv_data =
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
union gpio_pcal9535a_port_data *port = &drv_data->reg_cache.dir;
uint16_t bit_mask;
uint16_t new_value = 0;
u16_t bit_mask;
u16_t new_value = 0;
int ret;
switch (access_op) {
@ -198,13 +198,13 @@ done:
* @return 0 if successful, failed otherwise
*/
static int _setup_pin_pullupdown(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
struct gpio_pcal9535a_drv_data * const drv_data =
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
union gpio_pcal9535a_port_data *port;
uint16_t bit_mask;
uint16_t new_value = 0;
u16_t bit_mask;
u16_t new_value = 0;
int ret;
/* If disabling pull up/down, there is no need to set the selection
@ -291,13 +291,13 @@ done:
* @return 0 if successful, failed otherwise
*/
static int _setup_pin_polarity(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
struct gpio_pcal9535a_drv_data * const drv_data =
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
union gpio_pcal9535a_port_data *port = &drv_data->reg_cache.pol_inv;
uint16_t bit_mask;
uint16_t new_value = 0;
u16_t bit_mask;
u16_t new_value = 0;
int ret;
switch (access_op) {
@ -346,14 +346,14 @@ done:
* @return 0 if successful, failed otherwise
*/
static int gpio_pcal9535a_config(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
int ret;
#if (CONFIG_SYS_LOG_GPIO_PCAL9535A_LEVEL >= SYS_LOG_LEVEL_DEBUG)
const struct gpio_pcal9535a_config * const config =
dev->config->config_info;
uint16_t i2c_addr = config->i2c_slave_addr;
u16_t i2c_addr = config->i2c_slave_addr;
#endif
if (!_has_i2c_master(dev)) {
@ -396,13 +396,13 @@ done:
* @return 0 if successful, failed otherwise
*/
static int gpio_pcal9535a_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value)
u32_t pin, u32_t value)
{
struct gpio_pcal9535a_drv_data * const drv_data =
(struct gpio_pcal9535a_drv_data * const)dev->driver_data;
union gpio_pcal9535a_port_data *port = &drv_data->reg_cache.output;
uint16_t bit_mask;
uint16_t new_value;
u16_t bit_mask;
u16_t new_value;
int ret;
if (!_has_i2c_master(dev)) {
@ -456,7 +456,7 @@ done:
* @return 0 if successful, failed otherwise
*/
static int gpio_pcal9535a_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
u32_t pin, u32_t *value)
{
union gpio_pcal9535a_port_data buf;
int ret;
@ -498,7 +498,7 @@ static int gpio_pcal9535a_manage_callback(struct device *dev,
}
static int gpio_pcal9535a_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
ARG_UNUSED(dev);
ARG_UNUSED(access_op);
@ -508,7 +508,7 @@ static int gpio_pcal9535a_enable_callback(struct device *dev,
}
static int gpio_pcal9535a_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
ARG_UNUSED(dev);
ARG_UNUSED(access_op);

14
drivers/gpio/gpio_pcal9535a.h
View file

@ -26,16 +26,16 @@ struct gpio_pcal9535a_config {
const char * const i2c_master_dev_name;
/** The slave address of the chip */
uint16_t i2c_slave_addr;
u16_t i2c_slave_addr;
uint8_t stride[2];
u8_t stride[2];
};
/** Store the port 0/1 data for each register pair. */
union gpio_pcal9535a_port_data {
uint16_t all;
uint8_t port[2];
uint8_t byte[2];
u16_t all;
u8_t port[2];
u8_t byte[2];
};
/** Runtime driver data */
@ -47,7 +47,7 @@ struct gpio_pcal9535a_drv_data {
* Specify polarity inversion of pin. This is used for ouput as
* the polarity inversion registers on chip affects inputs only.
*/
uint32_t out_pol_inv;
u32_t out_pol_inv;
struct {
union gpio_pcal9535a_port_data output;
@ -57,7 +57,7 @@ struct gpio_pcal9535a_drv_data {
union gpio_pcal9535a_port_data pud_sel;
} reg_cache;
uint8_t stride[2];
u8_t stride[2];
};
#ifdef __cplusplus

30
drivers/gpio/gpio_pulpino.c
View file

@ -21,17 +21,17 @@ typedef void (*pulpino_cfg_func_t)(void);
/* pulpino GPIO register-set structure */
struct gpio_pulpino_t {
uint32_t paddir;
uint32_t padin;
uint32_t padout;
uint32_t inten;
uint32_t inttype0;
uint32_t inttype1;
uint32_t intstatus;
u32_t paddir;
u32_t padin;
u32_t padout;
u32_t inten;
u32_t inttype0;
u32_t inttype1;
u32_t intstatus;
};
struct gpio_pulpino_config {
uint32_t gpio_base_addr;
u32_t gpio_base_addr;
pulpino_cfg_func_t gpio_cfg_func;
};
@ -69,7 +69,7 @@ static void gpio_pulpino_irq_handler(void *arg)
*/
static int gpio_pulpino_config(struct device *dev,
int access_op,
uint32_t pin,
u32_t pin,
int flags)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
@ -138,8 +138,8 @@ static int gpio_pulpino_config(struct device *dev,
*/
static int gpio_pulpino_write(struct device *dev,
int access_op,
uint32_t pin,
uint32_t value)
u32_t pin,
u32_t value)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
@ -166,8 +166,8 @@ static int gpio_pulpino_write(struct device *dev,
*/
static int gpio_pulpino_read(struct device *dev,
int access_op,
uint32_t pin,
uint32_t *value)
u32_t pin,
u32_t *value)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
@ -200,7 +200,7 @@ static int gpio_pulpino_manage_callback(struct device *dev,
static int gpio_pulpino_enable_callback(struct device *dev,
int access_op,
uint32_t pin)
u32_t pin)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);
@ -215,7 +215,7 @@ static int gpio_pulpino_enable_callback(struct device *dev,
static int gpio_pulpino_disable_callback(struct device *dev,
int access_op,
uint32_t pin)
u32_t pin)
{
volatile struct gpio_pulpino_t *gpio = DEV_GPIO(dev);

48
drivers/gpio/gpio_qmsi.c
View file

@ -22,17 +22,17 @@
struct gpio_qmsi_config {
qm_gpio_t gpio;
uint8_t num_pins;
u8_t num_pins;
};
struct gpio_qmsi_runtime {
sys_slist_t callbacks;
uint32_t pin_callbacks;
u32_t pin_callbacks;
#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
struct k_sem sem;
#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
#endif
};
@ -45,14 +45,14 @@ struct gpio_qmsi_runtime {
static int gpio_qmsi_init(struct device *dev);
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void gpio_qmsi_set_power_state(struct device *dev, uint32_t power_state)
static void gpio_qmsi_set_power_state(struct device *dev, u32_t power_state)
{
struct gpio_qmsi_runtime *context = dev->driver_data;
context->device_power_state = power_state;
}
static uint32_t gpio_qmsi_get_power_state(struct device *dev)
static u32_t gpio_qmsi_get_power_state(struct device *dev)
{
struct gpio_qmsi_runtime *context = dev->driver_data;
@ -100,17 +100,17 @@ static int gpio_resume_device_from_suspend(struct device *dev)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int gpio_qmsi_device_ctrl(struct device *port, uint32_t ctrl_command,
static int gpio_qmsi_device_ctrl(struct device *port, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return gpio_suspend_device(port);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return gpio_resume_device_from_suspend(port);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = gpio_qmsi_get_power_state(port);
*((u32_t *)context) = gpio_qmsi_get_power_state(port);
return 0;
}
return 0;
@ -137,18 +137,18 @@ static struct gpio_qmsi_runtime gpio_aon_runtime;
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int gpio_aon_device_ctrl(struct device *port, uint32_t ctrl_command,
static int gpio_aon_device_ctrl(struct device *port, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
uint32_t device_pm_state = *(uint32_t *)context;
u32_t device_pm_state = *(u32_t *)context;
if (device_pm_state == DEVICE_PM_SUSPEND_STATE ||
device_pm_state == DEVICE_PM_ACTIVE_STATE) {
gpio_qmsi_set_power_state(port, device_pm_state);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = gpio_qmsi_get_power_state(port);
*((u32_t *)context) = gpio_qmsi_get_power_state(port);
}
return 0;
}
@ -160,18 +160,18 @@ DEVICE_DEFINE(gpio_aon, CONFIG_GPIO_QMSI_1_NAME, &gpio_qmsi_init,
#endif /* CONFIG_GPIO_QMSI_1 */
static void gpio_qmsi_callback(void *data, uint32_t status)
static void gpio_qmsi_callback(void *data, u32_t status)
{
struct device *port = data;
struct gpio_qmsi_runtime *context = port->driver_data;
const uint32_t enabled_mask = context->pin_callbacks & status;
const u32_t enabled_mask = context->pin_callbacks & status;
if (enabled_mask) {
_gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
}
}
static void qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
static void qmsi_write_bit(u32_t *target, u8_t bit, u8_t value)
{
if (value) {
sys_set_bit((uintptr_t) target, bit);
@ -180,7 +180,7 @@ static void qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
}
}
static inline void qmsi_pin_config(struct device *port, uint32_t pin, int flags)
static inline void qmsi_pin_config(struct device *port, u32_t pin, int flags)
{
const struct gpio_qmsi_config *gpio_config = port->config->config_info;
qm_gpio_t gpio = gpio_config->gpio;
@ -224,7 +224,7 @@ static inline void qmsi_pin_config(struct device *port, uint32_t pin, int flags)
static inline void qmsi_port_config(struct device *port, int flags)
{
const struct gpio_qmsi_config *gpio_config = port->config->config_info;
uint8_t num_pins = gpio_config->num_pins;
u8_t num_pins = gpio_config->num_pins;
int i;
for (i = 0; i < num_pins; i++) {
@ -233,7 +233,7 @@ static inline void qmsi_port_config(struct device *port, int flags)
}
static inline int gpio_qmsi_config(struct device *port,
int access_op, uint32_t pin, int flags)
int access_op, u32_t pin, int flags)
{
/* If the pin/port is set to receive interrupts, make sure the pin
is an input */
@ -250,7 +250,7 @@ static inline int gpio_qmsi_config(struct device *port,
}
static inline int gpio_qmsi_write(struct device *port,
int access_op, uint32_t pin, uint32_t value)
int access_op, u32_t pin, u32_t value)
{
const struct gpio_qmsi_config *gpio_config = port->config->config_info;
qm_gpio_t gpio = gpio_config->gpio;
@ -276,7 +276,7 @@ static inline int gpio_qmsi_write(struct device *port,
}
static inline int gpio_qmsi_read(struct device *port,
int access_op, uint32_t pin, uint32_t *value)
int access_op, u32_t pin, u32_t *value)
{
const struct gpio_qmsi_config *gpio_config = port->config->config_info;
qm_gpio_t gpio = gpio_config->gpio;
@ -286,7 +286,7 @@ static inline int gpio_qmsi_read(struct device *port,
qm_gpio_read_pin(gpio, pin, &state);
*value = state;
} else {
qm_gpio_read_port(gpio, (uint32_t *const) value);
qm_gpio_read_port(gpio, (u32_t *const) value);
}
return 0;
@ -304,7 +304,7 @@ static inline int gpio_qmsi_manage_callback(struct device *port,
}
static inline int gpio_qmsi_enable_callback(struct device *port,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_qmsi_runtime *context = port->driver_data;
@ -325,7 +325,7 @@ static inline int gpio_qmsi_enable_callback(struct device *port,
}
static inline int gpio_qmsi_disable_callback(struct device *port,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_qmsi_runtime *context = port->driver_data;
@ -346,7 +346,7 @@ static inline int gpio_qmsi_disable_callback(struct device *port,
return 0;
}
static uint32_t gpio_qmsi_get_pending_int(struct device *dev)
static u32_t gpio_qmsi_get_pending_int(struct device *dev)
{
const struct gpio_qmsi_config *gpio_config = dev->config->config_info;
qm_gpio_t gpio = gpio_config->gpio;

46
drivers/gpio/gpio_qmsi_ss.c
View file

@ -17,17 +17,17 @@
struct ss_gpio_qmsi_config {
qm_ss_gpio_t gpio;
uint8_t num_pins;
u8_t num_pins;
};
struct ss_gpio_qmsi_runtime {
sys_slist_t callbacks;
uint32_t pin_callbacks;
u32_t pin_callbacks;
#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
struct k_sem sem;
#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
qm_ss_gpio_context_t gpio_ctx;
#endif
};
@ -40,14 +40,14 @@ struct ss_gpio_qmsi_runtime {
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void ss_gpio_qmsi_set_power_state(struct device *dev,
uint32_t power_state)
u32_t power_state)
{
struct ss_gpio_qmsi_runtime *context = dev->driver_data;
context->device_power_state = power_state;
}
static uint32_t ss_gpio_qmsi_get_power_state(struct device *dev)
static u32_t ss_gpio_qmsi_get_power_state(struct device *dev)
{
struct ss_gpio_qmsi_runtime *context = dev->driver_data;
@ -84,17 +84,17 @@ static int ss_gpio_resume_device_from_suspend(struct device *dev)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int ss_gpio_qmsi_device_ctrl(struct device *port, uint32_t ctrl_command,
static int ss_gpio_qmsi_device_ctrl(struct device *port, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return ss_gpio_suspend_device(port);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return ss_gpio_resume_device_from_suspend(port);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = ss_gpio_qmsi_get_power_state(port);
*((u32_t *)context) = ss_gpio_qmsi_get_power_state(port);
}
return 0;
}
@ -132,18 +132,18 @@ DEVICE_DEFINE(ss_gpio_1, CONFIG_GPIO_QMSI_SS_1_NAME, &ss_gpio_qmsi_init,
#endif /* CONFIG_GPIO_QMSI_SS_1 */
static void ss_gpio_qmsi_callback(void *data, uint32_t status)
static void ss_gpio_qmsi_callback(void *data, u32_t status)
{
struct device *port = data;
struct ss_gpio_qmsi_runtime *context = port->driver_data;
const uint32_t enabled_mask = context->pin_callbacks & status;
const u32_t enabled_mask = context->pin_callbacks & status;
if (enabled_mask) {
_gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
}
}
static void ss_qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
static void ss_qmsi_write_bit(u32_t *target, u8_t bit, u8_t value)
{
if (value) {
sys_set_bit((uintptr_t) target, bit);
@ -152,13 +152,13 @@ static void ss_qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
}
}
static inline void ss_qmsi_pin_config(struct device *port, uint32_t pin,
static inline void ss_qmsi_pin_config(struct device *port, u32_t pin,
int flags)
{
const struct ss_gpio_qmsi_config *gpio_config =
port->config->config_info;
qm_ss_gpio_t gpio = gpio_config->gpio;
uint32_t controller;
u32_t controller;
qm_ss_gpio_port_config_t cfg = { 0 };
@ -214,7 +214,7 @@ static inline void ss_qmsi_port_config(struct device *port, int flags)
{
const struct ss_gpio_qmsi_config *gpio_config =
port->config->config_info;
uint8_t num_pins = gpio_config->num_pins;
u8_t num_pins = gpio_config->num_pins;
int i;
for (i = 0; i < num_pins; i++) {
@ -223,7 +223,7 @@ static inline void ss_qmsi_port_config(struct device *port, int flags)
}
static inline int ss_gpio_qmsi_config(struct device *port, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
/* check for an invalid pin configuration */
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
@ -239,7 +239,7 @@ static inline int ss_gpio_qmsi_config(struct device *port, int access_op,
}
static inline int ss_gpio_qmsi_write(struct device *port, int access_op,
uint32_t pin, uint32_t value)
u32_t pin, u32_t value)
{
const struct ss_gpio_qmsi_config *gpio_config =
port->config->config_info;
@ -267,7 +267,7 @@ static inline int ss_gpio_qmsi_write(struct device *port, int access_op,
}
static inline int ss_gpio_qmsi_read(struct device *port, int access_op,
uint32_t pin, uint32_t *value)
u32_t pin, u32_t *value)
{
const struct ss_gpio_qmsi_config *gpio_config =
port->config->config_info;
@ -296,7 +296,7 @@ static inline int ss_gpio_qmsi_manage_callback(struct device *port,
}
static inline int ss_gpio_qmsi_enable_callback(struct device *port,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct ss_gpio_qmsi_runtime *context = port->driver_data;
@ -318,7 +318,7 @@ static inline int ss_gpio_qmsi_enable_callback(struct device *port,
}
static inline int ss_gpio_qmsi_disable_callback(struct device *port,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct ss_gpio_qmsi_runtime *context = port->driver_data;
@ -365,7 +365,7 @@ static int ss_gpio_qmsi_init(struct device *port)
{
const struct ss_gpio_qmsi_config *gpio_config =
port->config->config_info;
uint32_t *scss_intmask = NULL;
u32_t *scss_intmask = NULL;
if (IS_ENABLED(CONFIG_GPIO_QMSI_API_REENTRANCY)) {
k_sem_init(RP_GET(port), 0, UINT_MAX);
@ -383,7 +383,7 @@ static int ss_gpio_qmsi_init(struct device *port)
ss_clk_gpio_enable(QM_SS_GPIO_0);
scss_intmask =
(uint32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_0_int_mask;
(u32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_0_int_mask;
*scss_intmask &= ~BIT(8);
break;
#endif /* CONFIG_GPIO_QMSI_SS_0 */
@ -397,7 +397,7 @@ static int ss_gpio_qmsi_init(struct device *port)
ss_clk_gpio_enable(QM_SS_GPIO_1);
scss_intmask =
(uint32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_1_int_mask;
(u32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_1_int_mask;
*scss_intmask &= ~BIT(8);
break;
#endif /* CONFIG_GPIO_QMSI_SS_1 */

34
drivers/gpio/gpio_sch.c
View file

@ -38,12 +38,12 @@
#endif /* GPIO_SCH_LEGACY_IO_PORTS_ACCESS */
#define DEFINE_MM_REG_READ(__reg, __off) \
static inline uint32_t _read_##__reg(uint32_t addr) \
static inline u32_t _read_##__reg(u32_t addr) \
{ \
return _REG_READ(addr + __off); \
}
#define DEFINE_MM_REG_WRITE(__reg, __off) \
static inline void _write_##__reg(uint32_t data, uint32_t addr) \
static inline void _write_##__reg(u32_t data, u32_t addr) \
{ \
_REG_WRITE(data, addr + __off); \
}
@ -55,8 +55,8 @@ DEFINE_MM_REG_WRITE(gtne, GPIO_SCH_REG_GTNE)
DEFINE_MM_REG_READ(gts, GPIO_SCH_REG_GTS)
DEFINE_MM_REG_WRITE(gts, GPIO_SCH_REG_GTS)
static void _set_bit(uint32_t base_addr,
uint32_t bit, uint8_t set)
static void _set_bit(u32_t base_addr,
u32_t bit, u8_t set)
{
if (!set) {
_REG_CLEAR_BIT(base_addr, bit);
@ -66,8 +66,8 @@ static void _set_bit(uint32_t base_addr,
}
#define DEFINE_MM_REG_SET_BIT(__reg, __off) \
static inline void _set_bit_##__reg(uint32_t addr, \
uint32_t bit, uint8_t set) \
static inline void _set_bit_##__reg(u32_t addr, \
u32_t bit, u8_t set) \
{ \
_set_bit(addr + __off, bit, set); \
}
@ -78,18 +78,18 @@ DEFINE_MM_REG_SET_BIT(glvl, GPIO_SCH_REG_GLVL)
DEFINE_MM_REG_SET_BIT(gtpe, GPIO_SCH_REG_GTPE)
DEFINE_MM_REG_SET_BIT(gtne, GPIO_SCH_REG_GTNE)
static inline void _set_data_reg(uint32_t *reg, uint8_t pin, uint8_t set)
static inline void _set_data_reg(u32_t *reg, u8_t pin, u8_t set)
{
*reg &= ~(BIT(pin));
*reg |= (set << pin) & BIT(pin);
}
static void _gpio_pin_config(struct device *dev, uint32_t pin, int flags)
static void _gpio_pin_config(struct device *dev, u32_t pin, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data;
uint8_t active_high = 0;
uint8_t active_low = 0;
u8_t active_high = 0;
u8_t active_low = 0;
_set_bit_gen(info->regs, pin, 1);
_set_bit_gio(info->regs, pin, !(flags & GPIO_DIR_MASK));
@ -123,7 +123,7 @@ static inline void _gpio_port_config(struct device *dev, int flags)
}
static int gpio_sch_config(struct device *dev,
int access_op, uint32_t pin, int flags)
int access_op, u32_t pin, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
@ -141,7 +141,7 @@ static int gpio_sch_config(struct device *dev,
}
static int gpio_sch_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value)
int access_op, u32_t pin, u32_t value)
{
const struct gpio_sch_config *info = dev->config->config_info;
@ -159,7 +159,7 @@ static int gpio_sch_write(struct device *dev,
}
static int gpio_sch_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
int access_op, u32_t pin, u32_t *value)
{
const struct gpio_sch_config *info = dev->config->config_info;
@ -189,7 +189,7 @@ static void _gpio_sch_poll_status(void *arg1, void *unused1, void *unused2)
_write_gts(_read_gts(info->regs), info->regs);
while (gpio->poll) {
uint32_t status;
u32_t status;
status = _read_gts(info->regs);
if (!status) {
@ -241,13 +241,13 @@ static int gpio_sch_manage_callback(struct device *dev,
}
static int gpio_sch_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
const struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
uint32_t bits = BIT(pin);
u32_t bits = BIT(pin);
if (pin >= info->bits) {
return -ENOTSUP;
@ -270,7 +270,7 @@ static int gpio_sch_enable_callback(struct device *dev,
}
static int gpio_sch_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
const struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data;

16
drivers/gpio/gpio_sch.h
View file

@ -24,9 +24,9 @@
#define GPIO_SCH_REG_GTS (0x1C)
struct gpio_sch_config {
uint32_t regs;
uint8_t bits;
uint8_t stride[3];
u32_t regs;
u8_t bits;
u8_t stride[3];
};
#define GPIO_SCH_POLLING_STACK_SIZE 1024
@ -38,13 +38,13 @@ struct gpio_sch_data {
struct k_timer poll_timer;
struct {
uint32_t gtpe;
uint32_t gtne;
u32_t gtpe;
u32_t gtne;
} int_regs;
uint32_t cb_enabled;
uint8_t poll;
uint8_t stride[3];
u32_t cb_enabled;
u8_t poll;
u8_t stride[3];
};
#endif /* __GPIO_SCH_H__ */

16
drivers/gpio/gpio_stm32.c
View file

@ -41,7 +41,7 @@ static void gpio_stm32_isr(int line, void *arg)
* @brief Configure pin or port
*/
static int gpio_stm32_config(struct device *dev, int access_op,
uint32_t pin, int flags)
u32_t pin, int flags)
{
const struct gpio_stm32_config *cfg = dev->config->config_info;
int pincfg;
@ -93,7 +93,7 @@ static int gpio_stm32_config(struct device *dev, int access_op,
* @brief Set the pin or port output
*/
static int gpio_stm32_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value)
u32_t pin, u32_t value)
{
const struct gpio_stm32_config *cfg = dev->config->config_info;
@ -108,7 +108,7 @@ static int gpio_stm32_write(struct device *dev, int access_op,
* @brief Read the pin or port status
*/
static int gpio_stm32_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
u32_t pin, u32_t *value)
{
const struct gpio_stm32_config *cfg = dev->config->config_info;
@ -133,7 +133,7 @@ static int gpio_stm32_manage_callback(struct device *dev,
}
static int gpio_stm32_enable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_stm32_data *data = dev->driver_data;
@ -147,7 +147,7 @@ static int gpio_stm32_enable_callback(struct device *dev,
}
static int gpio_stm32_disable_callback(struct device *dev,
int access_op, uint32_t pin)
int access_op, u32_t pin)
{
struct gpio_stm32_data *data = dev->driver_data;
@ -203,7 +203,7 @@ static int gpio_stm32_init(struct device *device)
#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr, __bus) \
static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
.base = (uint32_t *)__base_addr, \
.base = (u32_t *)__base_addr, \
.port = __port, \
.pclken = { .bus = __bus, .enr = __cenr } \
}; \
@ -224,7 +224,7 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
/* TODO: Change F1 to work similarly to F4 */
#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __clock) \
static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
.base = (uint32_t *)__base_addr, \
.base = (u32_t *)__base_addr, \
.port = __port, \
.clock_subsys = UINT_TO_POINTER(__clock) \
}; \
@ -242,7 +242,7 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr) \
static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
.base = (uint32_t *)__base_addr, \
.base = (u32_t *)__base_addr, \
.port = __port, \
.pclken = { .bus = STM32F4X_CLOCK_BUS_AHB1, .enr = __cenr }, \
}; \

10
drivers/gpio/gpio_stm32.h
View file

@ -48,7 +48,7 @@
*/
struct gpio_stm32_config {
/* port base address */
uint32_t *base;
u32_t *base;
/* IO port */
enum stm32_pin_port port;
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
@ -66,7 +66,7 @@ struct gpio_stm32_config {
*/
struct gpio_stm32_data {
/* Enabled INT pins generating a cb */
uint32_t cb_pins;
u32_t cb_pins;
/* user ISR cb */
sys_slist_t cb;
};
@ -89,7 +89,7 @@ int stm32_gpio_flags_to_conf(int flags, int *conf);
* @param func GPIO mode
* @param altf Alternate function
*/
int stm32_gpio_configure(uint32_t *base_addr, int pin, int func, int altf);
int stm32_gpio_configure(u32_t *base_addr, int pin, int func, int altf);
/**
* @brief helper for setting of GPIO pin output
@ -98,7 +98,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int func, int altf);
* @param pin IO pin
* @param value 1, 0
*/
int stm32_gpio_set(uint32_t *base, int pin, int value);
int stm32_gpio_set(u32_t *base, int pin, int value);
/**
* @brief helper for reading of GPIO pin value
@ -107,7 +107,7 @@ int stm32_gpio_set(uint32_t *base, int pin, int value);
* @param pin IO pin
* @return pin value
*/
int stm32_gpio_get(uint32_t *base, int pin);
int stm32_gpio_get(u32_t *base, int pin);
/**
* @brief enable interrupt source for GPIO pin

2
drivers/gpio/gpio_utils.h
View file

@ -42,7 +42,7 @@ static inline void _gpio_manage_callback(sys_slist_t *callbacks,
*/
static inline void _gpio_fire_callbacks(sys_slist_t *list,
struct device *port,
uint32_t pins)
u32_t pins)
{
struct gpio_callback *cb;

52
drivers/grove/lcd_rgb.c
View file

@ -23,20 +23,20 @@
#define GROVE_RGB_BACKLIGHT_ADDR (0x62)
struct command {
uint8_t control;
uint8_t data;
u8_t control;
u8_t data;
};
struct glcd_data {
struct device *i2c;
uint8_t input_set;
uint8_t display_switch;
uint8_t function;
u8_t input_set;
u8_t display_switch;
u8_t function;
};
struct glcd_driver {
uint16_t lcd_addr;
uint16_t rgb_addr;
u16_t lcd_addr;
u16_t rgb_addr;
};
@ -74,7 +74,7 @@ struct glcd_driver {
#define REGISTER_G 0x03
#define REGISTER_B 0x02
static uint8_t color_define[][3] = {
static u8_t color_define[][3] = {
{ 255, 255, 255 }, /* white */
{ 255, 0, 0 }, /* red */
{ 0, 255, 0 }, /* green */
@ -85,15 +85,15 @@ static uint8_t color_define[][3] = {
/********************************************
* PRIVATE FUNCTIONS
*******************************************/
static void _rgb_reg_set(struct device * const i2c, uint8_t addr, uint8_t dta)
static void _rgb_reg_set(struct device * const i2c, u8_t addr, u8_t dta)
{
uint8_t data[2] = { addr, dta };
u8_t data[2] = { addr, dta };
i2c_write(i2c, data, sizeof(data), GROVE_RGB_BACKLIGHT_ADDR);
}
static inline void _sleep(uint32_t sleep_in_ms)
static inline void _sleep(u32_t sleep_in_ms)
{
k_busy_wait(SLEEP_IN_US(sleep_in_ms));
}
@ -107,7 +107,7 @@ void glcd_print(struct device *port, char *data, uint32_t size)
const struct glcd_driver * const rom = (struct glcd_driver *)
port->config->config_info;
struct glcd_data *dev = port->driver_data;
uint8_t buf[] = { GLCD_CMD_SET_CGRAM_ADDR, 0 };
u8_t buf[] = { GLCD_CMD_SET_CGRAM_ADDR, 0 };
int i;
for (i = 0; i < size; i++) {
@ -117,7 +117,7 @@ void glcd_print(struct device *port, char *data, uint32_t size)
}
void glcd_cursor_pos_set(struct device *port, uint8_t col, uint8_t row)
void glcd_cursor_pos_set(struct device *port, u8_t col, u8_t row)
{
const struct glcd_driver * const rom = (struct glcd_driver *)
port->config->config_info;
@ -143,7 +143,7 @@ void glcd_clear(struct device *port)
const struct glcd_driver * const rom = (struct glcd_driver *)
port->config->config_info;
struct glcd_data *dev = port->driver_data;
uint8_t clear[] = { 0, GLCD_CMD_SCREEN_CLEAR };
u8_t clear[] = { 0, GLCD_CMD_SCREEN_CLEAR };
i2c_write(dev->i2c, clear, sizeof(clear), rom->lcd_addr);
SYS_LOG_DBG("clear, delay 20 ms");
@ -151,12 +151,12 @@ void glcd_clear(struct device *port)
}
void glcd_display_state_set(struct device *port, uint8_t opt)
void glcd_display_state_set(struct device *port, u8_t opt)
{
const struct glcd_driver * const rom = (struct glcd_driver *)
port->config->config_info;
struct glcd_data *dev = port->driver_data;
uint8_t data[] = { 0, 0 };
u8_t data[] = { 0, 0 };
dev->display_switch = opt;
data[1] = (opt | GLCD_CMD_DISPLAY_SWITCH);
@ -168,7 +168,7 @@ void glcd_display_state_set(struct device *port, uint8_t opt)
}
uint8_t glcd_display_state_get(struct device *port)
u8_t glcd_display_state_get(struct device *port)
{
struct glcd_data *dev = port->driver_data;
@ -176,11 +176,11 @@ uint8_t glcd_display_state_get(struct device *port)
}
void glcd_input_state_set(struct device *port, uint8_t opt)
void glcd_input_state_set(struct device *port, u8_t opt)
{
const struct glcd_driver * const rom = port->config->config_info;
struct glcd_data *dev = port->driver_data;
uint8_t data[] = { 0, 0 };
u8_t data[] = { 0, 0 };
dev->input_set = opt;
data[1] = (opt | GLCD_CMD_INPUT_SET);
@ -191,7 +191,7 @@ void glcd_input_state_set(struct device *port, uint8_t opt)
}
uint8_t glcd_input_state_get(struct device *port)
u8_t glcd_input_state_get(struct device *port)
{
struct glcd_data *dev = port->driver_data;
@ -199,7 +199,7 @@ uint8_t glcd_input_state_get(struct device *port)
}
void glcd_color_select(struct device *port, uint8_t color)
void glcd_color_select(struct device *port, u8_t color)
{
if (color > 3) {
SYS_LOG_WRN("selected color is too high a value");
@ -211,7 +211,7 @@ void glcd_color_select(struct device *port, uint8_t color)
}
void glcd_color_set(struct device *port, uint8_t r, uint8_t g, uint8_t b)
void glcd_color_set(struct device *port, u8_t r, u8_t g, u8_t b)
{
struct glcd_data * const dev = port->driver_data;
@ -221,11 +221,11 @@ void glcd_color_set(struct device *port, uint8_t r, uint8_t g, uint8_t b)
}
void glcd_function_set(struct device *port, uint8_t opt)
void glcd_function_set(struct device *port, u8_t opt)
{
const struct glcd_driver * const rom = port->config->config_info;
struct glcd_data *dev = port->driver_data;
uint8_t data[] = { 0, 0 };
u8_t data[] = { 0, 0 };
dev->function = opt;
data[1] = (opt | GLCD_CMD_FUNCTION_SET);
@ -237,7 +237,7 @@ void glcd_function_set(struct device *port, uint8_t opt)
}
uint8_t glcd_function_get(struct device *port)
u8_t glcd_function_get(struct device *port)
{
struct glcd_data *dev = port->driver_data;
@ -248,7 +248,7 @@ uint8_t glcd_function_get(struct device *port)
int glcd_initialize(struct device *port)
{
struct glcd_data *dev = port->driver_data;
uint8_t cmd;
u8_t cmd;
SYS_LOG_DBG("initialize called");

10
drivers/grove/light_sensor.c
View file

@ -18,7 +18,7 @@ struct gls_data {
struct device *adc;
struct adc_seq_entry sample;
struct adc_seq_table adc_table;
uint8_t adc_buffer[4];
u8_t adc_buffer[4];
};
static int gls_sample_fetch(struct device *dev, enum sensor_channel chan)
@ -33,11 +33,11 @@ static int gls_channel_get(struct device *dev,
struct sensor_value *val)
{
struct gls_data *drv_data = dev->driver_data;
uint16_t analog_val;
u16_t analog_val;
double ldr_val, dval;
/* rescale sample from 12bit (Zephyr) to 10bit (Grove) */
analog_val = ((uint16_t)drv_data->adc_buffer[1] << 8) |
analog_val = ((u16_t)drv_data->adc_buffer[1] << 8) |
drv_data->adc_buffer[0];
analog_val = analog_val >> 2;
@ -49,8 +49,8 @@ static int gls_channel_get(struct device *dev,
ldr_val = (1023.0 - analog_val) * 10.0 / analog_val;
dval = 10000.0 / pow(ldr_val * 15.0, 4.0/3.0);
val->val1 = (int32_t)dval;
val->val2 = ((int32_t)(dval * 1000000)) % 1000000;
val->val1 = (s32_t)dval;
val->val2 = ((s32_t)(dval * 1000000)) % 1000000;
return 0;
}

10
drivers/grove/temperature_sensor.c
View file

@ -25,7 +25,7 @@ struct gts_data {
struct device *adc;
struct adc_seq_entry sample;
struct adc_seq_table adc_table;
uint8_t adc_buffer[4];
u8_t adc_buffer[4];
};
static int gts_sample_fetch(struct device *dev, enum sensor_channel chan)
@ -40,11 +40,11 @@ static int gts_channel_get(struct device *dev,
struct sensor_value *val)
{
struct gts_data *drv_data = dev->driver_data;
uint16_t analog_val;
u16_t analog_val;
double dval;
/* rescale sample from 12bit (Zephyr) to 10bit (Grove) */
analog_val = ((uint16_t)drv_data->adc_buffer[1] << 8) |
analog_val = ((u16_t)drv_data->adc_buffer[1] << 8) |
drv_data->adc_buffer[0];
analog_val = analog_val >> 2;
@ -56,8 +56,8 @@ static int gts_channel_get(struct device *dev,
dval = 1 / (log(1023.0 / analog_val - 1.0) / B_CONST +
1 / 298.15) - 273.15;
val->val1 = (int32_t)dval;
val->val2 = ((int32_t)(dval * 1000000)) % 1000000;
val->val1 = (s32_t)dval;
val->val2 = ((s32_t)(dval * 1000000)) % 1000000;
return 0;
}

52
drivers/i2c/i2c_atmel_sam3.c
View file

@ -62,11 +62,11 @@ struct i2c_sam3_dev_data {
struct k_sem device_sync_sem;
union dev_config dev_config;
volatile uint32_t state;
volatile u32_t state;
uint8_t *xfr_buf;
uint32_t xfr_len;
uint32_t xfr_flags;
u8_t *xfr_buf;
u32_t xfr_len;
u32_t xfr_flags;
};
@ -76,7 +76,7 @@ struct i2c_sam3_dev_data {
* @param dev Device struct
* @return Value used for TWI_CWGR register.
*/
static uint32_t clk_div_calc(struct device *dev)
static u32_t clk_div_calc(struct device *dev)
{
#if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 84000000)
@ -109,11 +109,11 @@ static uint32_t clk_div_calc(struct device *dev)
*/
struct i2c_sam3_dev_data * const dev_data = dev->driver_data;
uint32_t i2c_clk;
uint32_t cldiv, chdiv, ckdiv;
uint32_t i2c_h_min_time, i2c_l_min_time;
uint32_t cldiv_min, chdiv_min;
uint32_t mck;
u32_t i2c_clk;
u32_t cldiv, chdiv, ckdiv;
u32_t i2c_h_min_time, i2c_l_min_time;
u32_t cldiv_min, chdiv_min;
u32_t mck;
/* The T(low) and T(high) are used to calculate CLDIV and CHDIV.
* Since we treat both clock low and clock high to have same period,
@ -188,8 +188,8 @@ static int i2c_sam3_runtime_configure(struct device *dev, uint32_t config)
{
const struct i2c_sam3_dev_config * const cfg = dev->config->config_info;
struct i2c_sam3_dev_data * const dev_data = dev->driver_data;
uint32_t reg;
uint32_t clk;
u32_t reg;
u32_t clk;
dev_data->dev_config.raw = config;
reg = 0;
@ -232,7 +232,7 @@ static void i2c_sam3_isr(void *arg)
* This is because reading from status register will clear certain
* bits, and thus status might be ignored afterwards.
*/
static inline void sr_bits_set_wait(struct device *dev, uint32_t bits)
static inline void sr_bits_set_wait(struct device *dev, u32_t bits)
{
const struct i2c_sam3_dev_config *const cfg = dev->config->config_info;
@ -245,7 +245,7 @@ static inline void sr_bits_set_wait(struct device *dev, uint32_t bits)
static inline void status_reg_clear(struct device *dev)
{
const struct i2c_sam3_dev_config *const cfg = dev->config->config_info;
uint32_t stat_reg;
u32_t stat_reg;
do {
stat_reg = cfg->port->sr;
@ -268,12 +268,12 @@ static inline void status_reg_clear(struct device *dev)
} while (stat_reg);
}
static inline void transfer_setup(struct device *dev, uint16_t slave_address)
static inline void transfer_setup(struct device *dev, u16_t slave_address)
{
const struct i2c_sam3_dev_config *const cfg = dev->config->config_info;
struct i2c_sam3_dev_data * const dev_data = dev->driver_data;
uint32_t mmr;
uint32_t iadr;
u32_t mmr;
u32_t iadr;
/* Set slave address */
if (dev_data->dev_config.bits.use_10_bit_addr) {
@ -308,7 +308,7 @@ static inline int msg_write(struct device *dev)
/* Setup PDC to do DMA transfer */
cfg->port->pdc.ptcr = PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS;
cfg->port->pdc.tpr = (uint32_t)dev_data->xfr_buf;
cfg->port->pdc.tpr = (u32_t)dev_data->xfr_buf;
cfg->port->pdc.tcr = dev_data->xfr_len;
/* Enable TX related interrupts.
@ -353,9 +353,9 @@ static inline int msg_read(struct device *dev)
{
const struct i2c_sam3_dev_config *const cfg = dev->config->config_info;
struct i2c_sam3_dev_data * const dev_data = dev->driver_data;
uint32_t stat_reg;
uint32_t ctrl_reg;
uint32_t last_len;
u32_t stat_reg;
u32_t ctrl_reg;
u32_t last_len;
/* To read from slave */
cfg->port->mmr |= TWI_MMR_MREAD;
@ -384,7 +384,7 @@ static inline int msg_read(struct device *dev)
while (dev_data->xfr_len > 0) {
/* Setup PDC to do DMA transfer. */
cfg->port->pdc.ptcr = PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS;
cfg->port->pdc.rpr = (uint32_t)dev_data->xfr_buf;
cfg->port->pdc.rpr = (u32_t)dev_data->xfr_buf;
/* Note that we need to set the STOP bit before reading
* last byte from RHR. So we need to process the last byte
@ -449,14 +449,14 @@ static inline int msg_read(struct device *dev)
}
static int i2c_sam3_transfer(struct device *dev,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t slave_address)
struct i2c_msg *msgs, u8_t num_msgs,
u16_t slave_address)
{
const struct i2c_sam3_dev_config *const cfg = dev->config->config_info;
struct i2c_sam3_dev_data * const dev_data = dev->driver_data;
struct i2c_msg *cur_msg = msgs;
uint8_t msg_left = num_msgs;
uint32_t pflags = 0;
u8_t msg_left = num_msgs;
u32_t pflags = 0;
int ret = 0;
int xfr_ret;

32
drivers/i2c/i2c_dw.c
View file

@ -39,10 +39,10 @@
static inline void _i2c_dw_data_ask(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
uint32_t data;
uint8_t tx_empty;
int8_t rx_empty;
uint8_t cnt;
u32_t data;
u8_t tx_empty;
s8_t rx_empty;
u8_t cnt;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;
@ -124,7 +124,7 @@ static void _i2c_dw_data_read(struct device *dev)
static int _i2c_dw_data_send(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
uint32_t data = 0;
u32_t data = 0;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;
@ -169,7 +169,7 @@ static int _i2c_dw_data_send(struct device *dev)
static inline void _i2c_dw_transfer_complete(struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
uint32_t value;
u32_t value;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;
@ -185,7 +185,7 @@ static void i2c_dw_isr(void *arg)
struct device *port = (struct device *)arg;
struct i2c_dw_dev_config * const dw = port->driver_data;
union ic_interrupt_register intr_stat;
uint32_t value;
u32_t value;
int ret = 0;
volatile struct i2c_dw_registers * const regs =
@ -293,10 +293,10 @@ done:
}
static int _i2c_dw_setup(struct device *dev, uint16_t slave_address)
static int _i2c_dw_setup(struct device *dev, u16_t slave_address)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
uint32_t value;
u32_t value;
union ic_con_register ic_con;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;
@ -402,13 +402,13 @@ static int _i2c_dw_setup(struct device *dev, uint16_t slave_address)
}
static int i2c_dw_transfer(struct device *dev,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t slave_address)
struct i2c_msg *msgs, u8_t num_msgs,
u16_t slave_address)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
struct i2c_msg *cur_msg = msgs;
uint8_t msg_left = num_msgs;
uint8_t pflags;
u8_t msg_left = num_msgs;
u8_t pflags;
int ret;
volatile struct i2c_dw_registers * const regs =
@ -514,11 +514,11 @@ static int i2c_dw_transfer(struct device *dev,
return ret;
}
static int i2c_dw_runtime_configure(struct device *dev, uint32_t config)
static int i2c_dw_runtime_configure(struct device *dev, u32_t config)
{
struct i2c_dw_dev_config * const dw = dev->driver_data;
uint32_t value = 0;
uint32_t rc = 0;
u32_t value = 0;
u32_t rc = 0;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)dw->base_address;

22
drivers/i2c/i2c_dw.h
View file

@ -85,8 +85,8 @@ typedef void (*i2c_isr_cb_t)(struct device *port);
struct i2c_dw_rom_config {
uint32_t irq_num;
uint32_t interrupt_mask;
u32_t irq_num;
u32_t interrupt_mask;
i2c_isr_cb_t config_func;
#ifdef CONFIG_I2C_DW_SHARED_IRQ
@ -96,21 +96,21 @@ struct i2c_dw_rom_config {
struct i2c_dw_dev_config {
uint32_t base_address;
u32_t base_address;
struct k_sem device_sync_sem;
union dev_config app_config;
uint8_t *xfr_buf;
uint32_t xfr_len;
uint32_t rx_pending;
u8_t *xfr_buf;
u32_t xfr_len;
u32_t rx_pending;
uint16_t hcnt;
uint16_t lcnt;
u16_t hcnt;
u16_t lcnt;
volatile uint8_t state; /* last direction of transfer */
uint8_t request_bytes;
uint8_t xfr_flags;
volatile u8_t state; /* last direction of transfer */
u8_t request_bytes;
u8_t xfr_flags;
bool support_hs_mode;
#ifdef CONFIG_PCI
struct pci_dev_info pci_dev;

258
drivers/i2c/i2c_dw_registers.h
View file

@ -23,17 +23,17 @@ extern "C" {
#define IC_CON_MASTER_MODE (1 << 0)
union ic_con_register {
uint16_t raw;
u16_t raw;
struct {
uint16_t master_mode : 1 __packed;
uint16_t speed : 2 __packed;
uint16_t addr_slave_10bit : 1 __packed;
uint16_t addr_master_10bit : 1 __packed;
uint16_t restart_en : 1 __packed;
uint16_t slave_disable : 1 __packed;
uint16_t stop_det : 1 __packed;
uint16_t tx_empty_ctl : 1 __packed;
uint16_t rx_fifo_full : 1 __packed;
u16_t master_mode : 1 __packed;
u16_t speed : 2 __packed;
u16_t addr_slave_10bit : 1 __packed;
u16_t addr_master_10bit : 1 __packed;
u16_t restart_en : 1 __packed;
u16_t slave_disable : 1 __packed;
u16_t stop_det : 1 __packed;
u16_t tx_empty_ctl : 1 __packed;
u16_t rx_fifo_full : 1 __packed;
} bits;
};
@ -45,13 +45,13 @@ union ic_con_register {
#define IC_DATA_CMD_RESTART (1 << 10)
union ic_data_cmd_register {
uint16_t raw;
u16_t raw;
struct {
uint16_t dat : 8 __packed;
uint16_t cmd : 1 __packed;
uint16_t stop : 1 __packed;
uint16_t restart : 1 __packed;
uint16_t reserved : 4 __packed;
u16_t dat : 8 __packed;
u16_t cmd : 1 __packed;
u16_t stop : 1 __packed;
u16_t restart : 1 __packed;
u16_t reserved : 4 __packed;
} bits;
};
@ -60,11 +60,11 @@ union ic_data_cmd_register {
#define IC_ENABLE_ABORT (1 << 1)
union ic_enable_register {
uint16_t raw;
u16_t raw;
struct {
uint16_t enable : 1 __packed;
uint16_t abort : 1 __packed;
uint16_t reserved : 13 __packed;
u16_t enable : 1 __packed;
u16_t abort : 1 __packed;
u16_t reserved : 13 __packed;
} bits;
};
@ -87,78 +87,78 @@ union ic_enable_register {
union ic_interrupt_register {
uint16_t raw;
u16_t raw;
struct {
uint16_t rx_under : 1 __packed;
uint16_t rx_over : 1 __packed;
uint16_t rx_full : 1 __packed;
uint16_t tx_over : 1 __packed;
uint16_t tx_empty : 1 __packed;
uint16_t rd_req : 1 __packed;
uint16_t tx_abrt : 1 __packed;
uint16_t rx_done : 1 __packed;
uint16_t activity : 1 __packed;
uint16_t stop_det : 1 __packed;
uint16_t start_det : 1 __packed;
uint16_t gen_call : 1 __packed;
uint16_t restart_det : 1 __packed;
uint16_t mst_on_hold : 1 __packed;
uint16_t reserved : 2 __packed;
u16_t rx_under : 1 __packed;
u16_t rx_over : 1 __packed;
u16_t rx_full : 1 __packed;
u16_t tx_over : 1 __packed;
u16_t tx_empty : 1 __packed;
u16_t rd_req : 1 __packed;
u16_t tx_abrt : 1 __packed;
u16_t rx_done : 1 __packed;
u16_t activity : 1 __packed;
u16_t stop_det : 1 __packed;
u16_t start_det : 1 __packed;
u16_t gen_call : 1 __packed;
u16_t restart_det : 1 __packed;
u16_t mst_on_hold : 1 __packed;
u16_t reserved : 2 __packed;
} bits;
};
/* IC_TAR */
union ic_tar_register {
uint16_t raw;
u16_t raw;
struct {
uint16_t ic_tar : 9 __packed;
uint16_t gc_or_start : 1 __packed;
uint16_t special : 1 __packed;
uint16_t ic_10bitaddr_master : 1 __packed;
uint16_t reserved : 3 __packed;
u16_t ic_tar : 9 __packed;
u16_t gc_or_start : 1 __packed;
u16_t special : 1 __packed;
u16_t ic_10bitaddr_master : 1 __packed;
u16_t reserved : 3 __packed;
} bits;
};
/* IC_SAR */
union ic_sar_register {
uint16_t raw;
u16_t raw;
struct {
uint16_t ic_sar : 9 __packed;
uint16_t reserved : 6 __packed;
u16_t ic_sar : 9 __packed;
u16_t reserved : 6 __packed;
} bits;
};
/* IC_STATUS */
union ic_status_register {
uint32_t raw;
u32_t raw;
struct {
uint32_t activity : 1 __packed;
uint32_t tfnf : 1 __packed;
uint32_t tfe : 1 __packed;
uint32_t rfne : 1 __packed;
uint32_t rff : 1 __packed;
uint32_t mst_activity : 1 __packed;
uint32_t slv_activity : 1 __packed;
uint32_t reserved : 24 __packed;
u32_t activity : 1 __packed;
u32_t tfnf : 1 __packed;
u32_t tfe : 1 __packed;
u32_t rfne : 1 __packed;
u32_t rff : 1 __packed;
u32_t mst_activity : 1 __packed;
u32_t slv_activity : 1 __packed;
u32_t reserved : 24 __packed;
} bits;
};
union ic_comp_param_1_register {
uint32_t raw;
u32_t raw;
struct {
uint32_t apb_data_width : 2 __packed;
uint32_t max_speed_mode : 2 __packed;
uint32_t hc_count_values : 1 __packed;
uint32_t intr_io : 1 __packed;
uint32_t has_dma : 1 __packed;
uint32_t add_encoded_params : 1 __packed;
uint32_t rx_buffer_depth : 8 __packed;
uint32_t tx_buffer_depth : 8 __packed;
uint32_t reserved : 7 __packed;
u32_t apb_data_width : 2 __packed;
u32_t max_speed_mode : 2 __packed;
u32_t hc_count_values : 1 __packed;
u32_t intr_io : 1 __packed;
u32_t has_dma : 1 __packed;
u32_t add_encoded_params : 1 __packed;
u32_t rx_buffer_depth : 8 __packed;
u32_t tx_buffer_depth : 8 __packed;
u32_t reserved : 7 __packed;
} bits;
};
@ -177,80 +177,80 @@ union ic_comp_param_1_register {
*/
struct i2c_dw_registers {
union ic_con_register ic_con; /* offset 0x00 */
uint16_t dummy1;
u16_t dummy1;
union ic_tar_register ic_tar; /* offset 0x04 */
uint16_t dummy2;
u16_t dummy2;
union ic_sar_register ic_sar; /* offset 0x08 */
uint16_t dummy3;
uint16_t ic_hs_maddr; /* offset 0x0C */
uint16_t dummy4;
u16_t dummy3;
u16_t ic_hs_maddr; /* offset 0x0C */
u16_t dummy4;
union ic_data_cmd_register ic_data_cmd; /* offset 0x10 */
uint16_t dummy5;
uint16_t ic_ss_scl_hcnt; /* offset 0x14 */
uint16_t dummy6;
uint16_t ic_ss_scl_lcnt; /* offset 0x18 */
uint16_t dummy7;
uint16_t ic_fs_scl_hcnt; /* offset 0x1C */
uint16_t dummy8;
uint16_t ic_fs_scl_lcnt; /* offset 0x20 */
uint16_t dummy9;
uint16_t ic_hs_scl_hcnt; /* offset 0x24 */
uint16_t dummy10;
uint16_t ic_hs_scl_lcnt; /* offset 0x28 */
uint16_t dummy11;
u16_t dummy5;
u16_t ic_ss_scl_hcnt; /* offset 0x14 */
u16_t dummy6;
u16_t ic_ss_scl_lcnt; /* offset 0x18 */
u16_t dummy7;
u16_t ic_fs_scl_hcnt; /* offset 0x1C */
u16_t dummy8;
u16_t ic_fs_scl_lcnt; /* offset 0x20 */
u16_t dummy9;
u16_t ic_hs_scl_hcnt; /* offset 0x24 */
u16_t dummy10;
u16_t ic_hs_scl_lcnt; /* offset 0x28 */
u16_t dummy11;
union ic_interrupt_register ic_intr_stat; /* offset 0x2C */
uint16_t dummy12;
u16_t dummy12;
union ic_interrupt_register ic_intr_mask; /* offset 0x30 */
uint16_t dummy13;
u16_t dummy13;
union ic_interrupt_register ic_raw_intr_stat; /* offset 0x34 */
uint16_t dummy14;
uint16_t ic_rx_tl; /* offset 0x38 */
uint16_t dummy15;
uint16_t ic_tx_tl; /* offset 0x3C */
uint16_t dummy16;
uint16_t ic_clr_intr; /* offset 0x40 */
uint16_t dummy17;
uint16_t ic_clr_rx_under; /* offset 0x44 */
uint16_t dummy18;
uint16_t ic_clr_rx_over; /* offset 0x48 */
uint16_t dummy19;
uint16_t ic_clr_tx_over; /* offset 0x4C */
uint16_t dummy20;
uint16_t ic_clr_rd_req; /* offset 0x50 */
uint16_t dummy21;
uint16_t ic_clr_tx_abrt; /* offset 0x54 */
uint16_t dummy22;
uint16_t ic_clr_rx_done; /* offset 0x58 */
uint16_t dummy23;
uint16_t ic_clr_activity; /* offset 0x5C */
uint16_t dummy24;
uint16_t ic_clr_stop_det; /* offset 0x60 */
uint16_t dummy25;
uint16_t ic_clr_start_det; /* offset 0x64 */
uint16_t dummy26;
uint16_t ic_clr_gen_call; /* offset 0x68 */
uint16_t dummy27;
u16_t dummy14;
u16_t ic_rx_tl; /* offset 0x38 */
u16_t dummy15;
u16_t ic_tx_tl; /* offset 0x3C */
u16_t dummy16;
u16_t ic_clr_intr; /* offset 0x40 */
u16_t dummy17;
u16_t ic_clr_rx_under; /* offset 0x44 */
u16_t dummy18;
u16_t ic_clr_rx_over; /* offset 0x48 */
u16_t dummy19;
u16_t ic_clr_tx_over; /* offset 0x4C */
u16_t dummy20;
u16_t ic_clr_rd_req; /* offset 0x50 */
u16_t dummy21;
u16_t ic_clr_tx_abrt; /* offset 0x54 */
u16_t dummy22;
u16_t ic_clr_rx_done; /* offset 0x58 */
u16_t dummy23;
u16_t ic_clr_activity; /* offset 0x5C */
u16_t dummy24;
u16_t ic_clr_stop_det; /* offset 0x60 */
u16_t dummy25;
u16_t ic_clr_start_det; /* offset 0x64 */
u16_t dummy26;
u16_t ic_clr_gen_call; /* offset 0x68 */
u16_t dummy27;
union ic_enable_register ic_enable; /* offset 0x6c */
uint16_t dummy28;
u16_t dummy28;
union ic_status_register ic_status; /* offset 0x70 */
uint32_t ic_txflr; /* offset 0x74 */
uint32_t ic_rxflr; /* offset 0x78 */
uint32_t ic_sda_hold; /* offset 0x7C */
uint32_t ic_tx_abrt_source; /* offset 0x80 */
uint32_t ic_slv_data_nack_only; /* offset 0x84 */
uint32_t ic_dma_cr; /* offset 0x88 */
uint32_t ic_dma_tdlr; /* offset 0x8C */
uint32_t ic_dma_rdlr; /* offset 0x90 */
uint32_t ic_sda_setup; /* offset 0x94 */
uint32_t ic_ack_general_call; /* offset 0x98 */
uint32_t ic_enable_status; /* offset 0x9C */
uint32_t ic_fs_spklen; /* offset 0xA0 */
uint32_t ic_hs_spklen; /* offset 0xA4 */
uint16_t ic_clr_restart_det; /* offset 0xA8 */
uint8_t filler[74];
u32_t ic_txflr; /* offset 0x74 */
u32_t ic_rxflr; /* offset 0x78 */
u32_t ic_sda_hold; /* offset 0x7C */
u32_t ic_tx_abrt_source; /* offset 0x80 */
u32_t ic_slv_data_nack_only; /* offset 0x84 */
u32_t ic_dma_cr; /* offset 0x88 */
u32_t ic_dma_tdlr; /* offset 0x8C */
u32_t ic_dma_rdlr; /* offset 0x90 */
u32_t ic_sda_setup; /* offset 0x94 */
u32_t ic_ack_general_call; /* offset 0x98 */
u32_t ic_enable_status; /* offset 0x9C */
u32_t ic_fs_spklen; /* offset 0xA0 */
u32_t ic_hs_spklen; /* offset 0xA4 */
u16_t ic_clr_restart_det; /* offset 0xA8 */
u8_t filler[74];
union ic_comp_param_1_register ic_comp_param_1; /* offset 0xF4 */
uint32_t ic_comp_version; /* offset 0xF8 */
uint32_t ic_comp_type; /* offset 0xFC */
u32_t ic_comp_version; /* offset 0xF8 */
u32_t ic_comp_type; /* offset 0xFC */
};
#ifdef __cplusplus

14
drivers/i2c/i2c_mcux.c
View file

@ -31,13 +31,13 @@ struct i2c_mcux_data {
status_t callback_status;
};
static int i2c_mcux_configure(struct device *dev, uint32_t dev_config_raw)
static int i2c_mcux_configure(struct device *dev, u32_t dev_config_raw)
{
I2C_Type *base = DEV_BASE(dev);
const struct i2c_mcux_config *config = DEV_CFG(dev);
union dev_config dev_config = (union dev_config)dev_config_raw;
uint32_t clock_freq;
uint32_t baudrate;
u32_t clock_freq;
u32_t baudrate;
if (!dev_config.bits.is_master_device) {
return -EINVAL;
@ -81,9 +81,9 @@ static void i2c_mcux_master_transfer_callback(I2C_Type *base,
k_sem_give(&data->device_sync_sem);
}
static uint32_t i2c_mcux_convert_flags(int msg_flags)
static u32_t i2c_mcux_convert_flags(int msg_flags)
{
uint32_t flags = 0;
u32_t flags = 0;
if (!(msg_flags & I2C_MSG_STOP)) {
flags |= kI2C_TransferNoStopFlag;
@ -97,7 +97,7 @@ static uint32_t i2c_mcux_convert_flags(int msg_flags)
}
static int i2c_mcux_transfer(struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
u8_t num_msgs, u16_t addr)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_mcux_data *data = DEV_DATA(dev);
@ -159,7 +159,7 @@ static int i2c_mcux_init(struct device *dev)
I2C_Type *base = DEV_BASE(dev);
const struct i2c_mcux_config *config = DEV_CFG(dev);
struct i2c_mcux_data *data = DEV_DATA(dev);
uint32_t clock_freq;
u32_t clock_freq;
i2c_master_config_t master_config;
int error;

12
drivers/i2c/i2c_nrf5.c
View file

@ -39,15 +39,15 @@ struct i2c_nrf5_config {
struct i2c_nrf5_data {
struct k_sem sem;
uint32_t rxd:1;
uint32_t txd:1;
uint32_t err:1;
uint32_t stopped:1;
u32_t rxd:1;
u32_t txd:1;
u32_t err:1;
u32_t stopped:1;
struct device *gpio;
};
static int i2c_nrf5_configure(struct device *dev, uint32_t dev_config_raw)
static int i2c_nrf5_configure(struct device *dev, u32_t dev_config_raw)
{
const struct i2c_nrf5_config *config = dev->config->config_info;
union dev_config dev_config = (union dev_config)dev_config_raw;
@ -199,7 +199,7 @@ static int i2c_nrf5_write(struct device *dev,
}
static int i2c_nrf5_transfer(struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
u8_t num_msgs, u16_t addr)
{
const struct i2c_nrf5_config *config = dev->config->config_info;
volatile NRF_TWI_Type *twi = config->base;

22
drivers/i2c/i2c_qmsi.c
View file

@ -36,20 +36,20 @@ struct i2c_qmsi_driver_data {
int transfer_status;
struct k_sem sem;
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
qm_i2c_context_t i2c_ctx;
#endif
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void i2c_qmsi_set_power_state(struct device *dev, uint32_t power_state)
static void i2c_qmsi_set_power_state(struct device *dev, u32_t power_state)
{
struct i2c_qmsi_driver_data *drv_data = dev->driver_data;
drv_data->device_power_state = power_state;
}
static uint32_t i2c_qmsi_get_power_state(struct device *dev)
static u32_t i2c_qmsi_get_power_state(struct device *dev)
{
struct i2c_qmsi_driver_data *drv_data = dev->driver_data;
@ -87,17 +87,17 @@ static int i2c_resume_device_from_suspend(struct device *dev)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int i2c_device_ctrl(struct device *dev, uint32_t ctrl_command,
static int i2c_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return i2c_suspend_device(dev);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return i2c_resume_device_from_suspend(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = i2c_qmsi_get_power_state(dev);
*((u32_t *)context) = i2c_qmsi_get_power_state(dev);
return 0;
}
@ -139,7 +139,7 @@ DEVICE_DEFINE(i2c_1, CONFIG_I2C_1_NAME, &i2c_qmsi_init,
#endif /* CONFIG_I2C_1 */
static int i2c_qmsi_configure(struct device *dev, uint32_t config)
static int i2c_qmsi_configure(struct device *dev, u32_t config)
{
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
@ -185,7 +185,7 @@ static int i2c_qmsi_configure(struct device *dev, uint32_t config)
}
static void transfer_complete(void *data, int rc, qm_i2c_status_t status,
uint32_t len)
u32_t len)
{
struct device *dev = (struct device *) data;
struct i2c_qmsi_driver_data *driver_data;
@ -196,7 +196,7 @@ static void transfer_complete(void *data, int rc, qm_i2c_status_t status,
}
static int i2c_qmsi_transfer(struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
u8_t num_msgs, u16_t addr)
{
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
@ -210,7 +210,7 @@ static int i2c_qmsi_transfer(struct device *dev, struct i2c_msg *msgs,
device_busy_set(dev);
for (int i = 0; i < num_msgs; i++) {
uint8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
u8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
bool stop = (msgs[i].flags & I2C_MSG_STOP) == I2C_MSG_STOP;
qm_i2c_transfer_t xfer = { 0 };
if (op == I2C_MSG_WRITE) {

28
drivers/i2c/i2c_qmsi_ss.c
View file

@ -31,21 +31,21 @@ struct i2c_qmsi_ss_driver_data {
int transfer_status;
struct k_sem sem;
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
uint32_t device_power_state;
u32_t device_power_state;
qm_ss_i2c_context_t i2c_ctx;
#endif
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void ss_i2c_qmsi_set_power_state(struct device *dev,
uint32_t power_state)
u32_t power_state)
{
struct i2c_qmsi_ss_driver_data *drv_data = GET_DRIVER_DATA(dev);
drv_data->device_power_state = power_state;
}
static uint32_t ss_i2c_qmsi_get_power_state(struct device *dev)
static u32_t ss_i2c_qmsi_get_power_state(struct device *dev)
{
struct i2c_qmsi_ss_driver_data *drv_data = GET_DRIVER_DATA(dev);
@ -84,17 +84,17 @@ static int ss_i2c_resume_device_from_suspend(struct device *dev)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int ss_i2c_device_ctrl(struct device *dev, uint32_t ctrl_command,
static int ss_i2c_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return ss_i2c_suspend_device(dev);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return ss_i2c_resume_device_from_suspend(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = ss_i2c_qmsi_get_power_state(dev);
*((u32_t *)context) = ss_i2c_qmsi_get_power_state(dev);
}
return 0;
@ -123,7 +123,7 @@ DEVICE_DEFINE(i2c_ss_0, CONFIG_I2C_SS_0_NAME, i2c_qmsi_ss_init,
static void i2c_qmsi_ss_config_irq_0(void)
{
uint32_t mask = 0;
u32_t mask = 0;
/* Need to unmask the interrupts in System Control Subsystem (SCSS)
* so the interrupt controller can route these interrupts to
@ -180,7 +180,7 @@ DEVICE_DEFINE(i2c_ss_1, CONFIG_I2C_SS_1_NAME, i2c_qmsi_ss_init,
static void i2c_qmsi_ss_config_irq_1(void)
{
uint32_t mask = 0;
u32_t mask = 0;
/* Need to unmask the interrupts in System Control Subsystem (SCSS)
* so the interrupt controller can route these interrupts to
@ -225,7 +225,7 @@ static int i2c_qmsi_ss_configure(struct device *dev, uint32_t config)
struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);
union dev_config cfg;
qm_ss_i2c_config_t qm_cfg;
uint32_t i2c_base = QM_SS_I2C_0_BASE;
u32_t i2c_base = QM_SS_I2C_0_BASE;
cfg.raw = config;
@ -281,7 +281,7 @@ static void transfer_complete(void *data, int rc, qm_ss_i2c_status_t status,
}
static int i2c_qmsi_ss_transfer(struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
u8_t num_msgs, u16_t addr)
{
struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);
qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
@ -295,9 +295,9 @@ static int i2c_qmsi_ss_transfer(struct device *dev, struct i2c_msg *msgs,
device_busy_set(dev);
for (int i = 0; i < num_msgs; i++) {
uint8_t *buf = msgs[i].buf;
uint32_t len = msgs[i].len;
uint8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
u8_t *buf = msgs[i].buf;
u32_t len = msgs[i].len;
u8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
bool stop = (msgs[i].flags & I2C_MSG_STOP) == I2C_MSG_STOP;
qm_ss_i2c_transfer_t xfer = { 0 };

38
drivers/i2c/i2c_stm32lx.c
View file

@ -28,15 +28,15 @@
#define I2C_STRUCT(dev) \
((volatile struct i2c_stm32lx *)(DEV_CFG(dev))->base)
static int i2c_stm32lx_runtime_configure(struct device *dev, uint32_t config)
static int i2c_stm32lx_runtime_configure(struct device *dev, u32_t config)
{
volatile struct i2c_stm32lx *i2c = I2C_STRUCT(dev);
struct i2c_stm32lx_data *data = DEV_DATA(dev);
const struct i2c_stm32lx_config *cfg = DEV_CFG(dev);
uint32_t clock;
uint32_t i2c_h_min_time, i2c_l_min_time;
uint32_t i2c_hold_time_min, i2c_setup_time_min;
uint32_t presc = 1;
u32_t clock;
u32_t i2c_h_min_time, i2c_l_min_time;
u32_t i2c_hold_time_min, i2c_setup_time_min;
u32_t presc = 1;
data->dev_config.raw = config;
@ -70,12 +70,12 @@ static int i2c_stm32lx_runtime_configure(struct device *dev, uint32_t config)
/* Calculate period until prescaler matches */
do {
uint32_t t_presc = clock / presc;
uint32_t ns_presc = NSEC_PER_SEC / t_presc;
uint32_t sclh = i2c_h_min_time / ns_presc;
uint32_t scll = i2c_l_min_time / ns_presc;
uint32_t sdadel = i2c_hold_time_min / ns_presc;
uint32_t scldel = i2c_setup_time_min / ns_presc;
u32_t t_presc = clock / presc;
u32_t ns_presc = NSEC_PER_SEC / t_presc;
u32_t sclh = i2c_h_min_time / ns_presc;
u32_t scll = i2c_l_min_time / ns_presc;
u32_t sdadel = i2c_hold_time_min / ns_presc;
u32_t scldel = i2c_setup_time_min / ns_presc;
if ((sclh - 1) > 255 ||
(scll - 1) > 255 ||
@ -163,7 +163,7 @@ static void i2c_stm32lx_er_isr(void *arg)
}
#endif
static inline void transfer_setup(struct device *dev, uint16_t slave_address,
static inline void transfer_setup(struct device *dev, u16_t slave_address,
unsigned int read_transfer)
{
volatile struct i2c_stm32lx *i2c = I2C_STRUCT(dev);
@ -186,7 +186,7 @@ static inline int msg_write(struct device *dev, struct i2c_msg *msg,
struct i2c_stm32lx_data *data = DEV_DATA(dev);
#endif
unsigned int len = msg->len;
uint8_t *buf = msg->buf;
u8_t *buf = msg->buf;
if (len > 255)
return -EINVAL;
@ -272,7 +272,7 @@ static inline int msg_read(struct device *dev, struct i2c_msg *msg,
struct i2c_stm32lx_data *data = DEV_DATA(dev);
#endif
unsigned int len = msg->len;
uint8_t *buf = msg->buf;
u8_t *buf = msg->buf;
if (len > 255)
return -EINVAL;
@ -336,12 +336,12 @@ static inline int msg_read(struct device *dev, struct i2c_msg *msg,
}
static int i2c_stm32lx_transfer(struct device *dev,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t slave_address)
struct i2c_msg *msgs, u8_t num_msgs,
u16_t slave_address)
{
volatile struct i2c_stm32lx *i2c = I2C_STRUCT(dev);
struct i2c_msg *cur_msg = msgs;
uint8_t msg_left = num_msgs;
u8_t msg_left = num_msgs;
int ret = 0;
/* Enable Peripheral */
@ -439,7 +439,7 @@ static void i2c_stm32lx_irq_config_func_1(struct device *port);
#endif
static const struct i2c_stm32lx_config i2c_stm32lx_cfg_1 = {
.base = (uint8_t *)I2C1_BASE,
.base = (u8_t *)I2C1_BASE,
.pclken = { .bus = STM32_CLOCK_BUS_APB1,
.enr = LL_APB1_GRP1_PERIPH_I2C1 },
#ifdef CONFIG_I2C_STM32LX_INTERRUPT
@ -483,7 +483,7 @@ static void i2c_stm32lx_irq_config_func_2(struct device *port);
#endif
static const struct i2c_stm32lx_config i2c_stm32lx_cfg_2 = {
.base = (uint8_t *)I2C2_BASE,
.base = (u8_t *)I2C2_BASE,
.pclken = { .bus = STM32_CLOCK_BUS_APB1,
.enr = LL_APB1_GRP1_PERIPH_I2C2 },
#ifdef CONFIG_I2C_STM32LX_INTERRUPT

210
drivers/i2c/i2c_stm32lx.h
View file

@ -9,156 +9,156 @@
/* 35.6.1 Control register 1 (I2C_CR1) */
union __cr1 {
uint32_t val;
u32_t val;
struct {
uint32_t pe :1 __packed;
uint32_t txie :1 __packed;
uint32_t rxie :1 __packed;
uint32_t addrie :1 __packed;
uint32_t nackie :1 __packed;
uint32_t stopie :1 __packed;
uint32_t tcie :1 __packed;
uint32_t errie :1 __packed;
uint32_t dnf :4 __packed;
uint32_t anfoff :1 __packed;
uint32_t rsvd__13 :1 __packed;
uint32_t txdmaen :1 __packed;
uint32_t rxdmaen :1 __packed;
uint32_t sbc :1 __packed;
uint32_t nostretch :1 __packed;
uint32_t wupen :1 __packed;
uint32_t gcen :1 __packed;
uint32_t smbhen :1 __packed;
uint32_t smbden :1 __packed;
uint32_t alerten :1 __packed;
uint32_t pecen :1 __packed;
uint32_t rsvd__24_31 :8 __packed;
u32_t pe :1 __packed;
u32_t txie :1 __packed;
u32_t rxie :1 __packed;
u32_t addrie :1 __packed;
u32_t nackie :1 __packed;
u32_t stopie :1 __packed;
u32_t tcie :1 __packed;
u32_t errie :1 __packed;
u32_t dnf :4 __packed;
u32_t anfoff :1 __packed;
u32_t rsvd__13 :1 __packed;
u32_t txdmaen :1 __packed;
u32_t rxdmaen :1 __packed;
u32_t sbc :1 __packed;
u32_t nostretch :1 __packed;
u32_t wupen :1 __packed;
u32_t gcen :1 __packed;
u32_t smbhen :1 __packed;
u32_t smbden :1 __packed;
u32_t alerten :1 __packed;
u32_t pecen :1 __packed;
u32_t rsvd__24_31 :8 __packed;
} bit;
};
/* 35.6.2 Control register 2 (I2C_CR2) */
union __cr2 {
uint32_t val;
u32_t val;
struct {
uint32_t sadd :10 __packed;
uint32_t rd_wrn :1 __packed;
uint32_t add10 :1 __packed;
uint32_t head10r :1 __packed;
uint32_t start :1 __packed;
uint32_t stop :1 __packed;
uint32_t nack :1 __packed;
uint32_t nbytes :8 __packed;
uint32_t reload :1 __packed;
uint32_t autoend :1 __packed;
uint32_t pecbyte :1 __packed;
uint32_t rsvd__27_31 :5 __packed;
u32_t sadd :10 __packed;
u32_t rd_wrn :1 __packed;
u32_t add10 :1 __packed;
u32_t head10r :1 __packed;
u32_t start :1 __packed;
u32_t stop :1 __packed;
u32_t nack :1 __packed;
u32_t nbytes :8 __packed;
u32_t reload :1 __packed;
u32_t autoend :1 __packed;
u32_t pecbyte :1 __packed;
u32_t rsvd__27_31 :5 __packed;
} bit;
};
union __oar1 {
uint32_t val;
u32_t val;
struct {
uint32_t oa1 :10 __packed;
uint32_t oa1mode :1 __packed;
uint32_t rsvd__11_14 :4 __packed;
uint32_t oa1en :1 __packed;
uint32_t rsvd__16_31 :16 __packed;
u32_t oa1 :10 __packed;
u32_t oa1mode :1 __packed;
u32_t rsvd__11_14 :4 __packed;
u32_t oa1en :1 __packed;
u32_t rsvd__16_31 :16 __packed;
} bit;
};
union __oar2 {
uint32_t val;
u32_t val;
struct {
uint32_t rsvd__0 :1 __packed;
uint32_t oa2 :7 __packed;
uint32_t oa2msk :3 __packed;
uint32_t rsvd__11_14 :4 __packed;
uint32_t oa2en :1 __packed;
uint32_t rsvd__16_31 :16 __packed;
u32_t rsvd__0 :1 __packed;
u32_t oa2 :7 __packed;
u32_t oa2msk :3 __packed;
u32_t rsvd__11_14 :4 __packed;
u32_t oa2en :1 __packed;
u32_t rsvd__16_31 :16 __packed;
} bit;
};
union __timingr {
uint32_t val;
u32_t val;
struct {
uint32_t scll :8 __packed;
uint32_t sclh :8 __packed;
uint32_t sdadel :4 __packed;
uint32_t scldel :4 __packed;
uint32_t rsvd__24_27 :4 __packed;
uint32_t presc :4 __packed;
u32_t scll :8 __packed;
u32_t sclh :8 __packed;
u32_t sdadel :4 __packed;
u32_t scldel :4 __packed;
u32_t rsvd__24_27 :4 __packed;
u32_t presc :4 __packed;
} bit;
};
union __timeoutr {
uint32_t val;
u32_t val;
struct {
uint32_t timeouta :12 __packed;
uint32_t tidle :1 __packed;
uint32_t rsvd__13_14 :1 __packed;
uint32_t timouten :1 __packed;
uint32_t timeoutb :12 __packed;
uint32_t rsvd__28_30 :1 __packed;
uint32_t texten :1 __packed;
u32_t timeouta :12 __packed;
u32_t tidle :1 __packed;
u32_t rsvd__13_14 :1 __packed;
u32_t timouten :1 __packed;
u32_t timeoutb :12 __packed;
u32_t rsvd__28_30 :1 __packed;
u32_t texten :1 __packed;
} bit;
};
union __isr {
uint32_t val;
u32_t val;
struct {
uint32_t txe :1 __packed;
uint32_t txis :1 __packed;
uint32_t rxne :1 __packed;
uint32_t addr :1 __packed;
uint32_t nackf :1 __packed;
uint32_t stopf :1 __packed;
uint32_t tc :1 __packed;
uint32_t tcr :1 __packed;
uint32_t berr :1 __packed;
uint32_t arlo :1 __packed;
uint32_t ovr :1 __packed;
uint32_t pecerr :1 __packed;
uint32_t timeout :1 __packed;
uint32_t alert :1 __packed;
uint32_t rsvd__14 :1 __packed;
uint32_t busy :1 __packed;
uint32_t dir :1 __packed;
uint32_t addcode :7 __packed;
uint32_t rsvd__24_31 :8 __packed;
u32_t txe :1 __packed;
u32_t txis :1 __packed;
u32_t rxne :1 __packed;
u32_t addr :1 __packed;
u32_t nackf :1 __packed;
u32_t stopf :1 __packed;
u32_t tc :1 __packed;
u32_t tcr :1 __packed;
u32_t berr :1 __packed;
u32_t arlo :1 __packed;
u32_t ovr :1 __packed;
u32_t pecerr :1 __packed;
u32_t timeout :1 __packed;
u32_t alert :1 __packed;
u32_t rsvd__14 :1 __packed;
u32_t busy :1 __packed;
u32_t dir :1 __packed;
u32_t addcode :7 __packed;
u32_t rsvd__24_31 :8 __packed;
} bit;
};
union __icr {
uint32_t val;
u32_t val;
struct {
uint32_t rsvd__0_2 :3 __packed;
uint32_t addr :1 __packed;
uint32_t nack :1 __packed;
uint32_t stop :1 __packed;
uint32_t rsvd__6_7 :2 __packed;
uint32_t berr :1 __packed;
uint32_t arlo :1 __packed;
uint32_t ovr :1 __packed;
uint32_t pec :1 __packed;
uint32_t timeout :1 __packed;
uint32_t alert :1 __packed;
uint32_t rsvd__14_31 :17 __packed;
u32_t rsvd__0_2 :3 __packed;
u32_t addr :1 __packed;
u32_t nack :1 __packed;
u32_t stop :1 __packed;
u32_t rsvd__6_7 :2 __packed;
u32_t berr :1 __packed;
u32_t arlo :1 __packed;
u32_t ovr :1 __packed;
u32_t pec :1 __packed;
u32_t timeout :1 __packed;
u32_t alert :1 __packed;
u32_t rsvd__14_31 :17 __packed;
} bit;
};
union __pecr {
uint32_t val;
u32_t val;
struct {
uint32_t pec:8 __packed;
uint32_t rsvd__9_31 :24 __packed;
u32_t pec:8 __packed;
u32_t rsvd__9_31 :24 __packed;
} bit;
};
union __dr {
uint32_t val;
u32_t val;
struct {
uint32_t data:8 __packed;
uint32_t rsvd__9_31 :24 __packed;
u32_t data:8 __packed;
u32_t rsvd__9_31 :24 __packed;
} bit;
};
@ -174,7 +174,7 @@ struct i2c_stm32lx {
union __icr icr;
union __pecr pecr;
union __dr rxdr;
uint32_t txdr;
u32_t txdr;
};
typedef void (*irq_config_func_t)(struct device *port);
@ -199,7 +199,7 @@ struct i2c_stm32lx_data {
struct {
struct i2c_msg *msg;
unsigned int len;
uint8_t *buf;
u8_t *buf;
unsigned int is_err;
unsigned int is_nack;
unsigned int is_write;

40
drivers/i2c/twihs_sam.c
View file

@ -32,23 +32,23 @@
struct twihs_sam_dev_cfg {
Twihs *regs;
void (*irq_config)(void);
uint8_t periph_id;
uint8_t irq_id;
u8_t periph_id;
u8_t irq_id;
const struct soc_gpio_pin *pin_list;
uint8_t pin_list_size;
u8_t pin_list_size;
};
struct twihs_msg {
/* Buffer containing data to read or write */
uint8_t *buf;
u8_t *buf;
/* Length of the buffer */
uint32_t len;
u32_t len;
/* Index of the next byte to be read/written from/to the buffer */
uint32_t idx;
u32_t idx;
/* Value of TWIHS_SR at the end of the message */
uint32_t twihs_sr;
u32_t twihs_sr;
/* Transfer flags as defined in the i2c.h file */
uint8_t flags;
u8_t flags;
};
/* Device run time data */
@ -63,11 +63,11 @@ struct twihs_sam_dev_data {
#define DEV_DATA(dev) \
((struct twihs_sam_dev_data *const)(dev)->driver_data)
static uint32_t clk_div_calc(uint32_t speed)
static u32_t clk_div_calc(u32_t speed)
{
uint32_t ck_div = 0;
uint32_t cl_div;
uint32_t div_completed = 0;
u32_t ck_div = 0;
u32_t cl_div;
u32_t div_completed = 0;
while (!div_completed) {
cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (2 * speed)) - 4)
@ -84,13 +84,13 @@ static uint32_t clk_div_calc(uint32_t speed)
return (ck_div << 16) | (cl_div << 8) | cl_div;
}
static int twihs_sam_configure(struct device *dev, uint32_t config)
static int twihs_sam_configure(struct device *dev, u32_t config)
{
const struct twihs_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
struct twihs_sam_dev_data *const dev_data = DEV_DATA(dev);
Twihs *const twihs = dev_cfg->regs;
uint32_t i2c_speed;
uint32_t clk;
u32_t i2c_speed;
u32_t clk;
if (!(config & (I2C_MODE_MASTER | I2C_MODE_SLAVE_READ))) {
SYS_LOG_ERR("Neither Master nor Slave I2C Mode is enabled");
@ -137,7 +137,7 @@ static int twihs_sam_configure(struct device *dev, uint32_t config)
}
static void write_msg_start(Twihs *const twihs, struct twihs_msg *msg,
uint8_t daddr)
u8_t daddr)
{
/* Set slave address and number of internal address bytes. */
twihs->TWIHS_MMR = TWIHS_MMR_DADR(daddr);
@ -151,9 +151,9 @@ static void write_msg_start(Twihs *const twihs, struct twihs_msg *msg,
}
static void read_msg_start(Twihs *const twihs, struct twihs_msg *msg,
uint8_t daddr)
u8_t daddr)
{
uint32_t twihs_cr_stop;
u32_t twihs_cr_stop;
/* Set slave address and number of internal address bytes */
twihs->TWIHS_MMR = TWIHS_MMR_MREAD | TWIHS_MMR_DADR(daddr);
@ -170,7 +170,7 @@ static void read_msg_start(Twihs *const twihs, struct twihs_msg *msg,
}
static int twihs_sam_transfer(struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
u8_t num_msgs, u16_t addr)
{
const struct twihs_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
struct twihs_sam_dev_data *const dev_data = DEV_DATA(dev);
@ -212,7 +212,7 @@ static void twihs_sam_isr(void *arg)
struct twihs_sam_dev_data *const dev_data = DEV_DATA(dev);
Twihs *const twihs = dev_cfg->regs;
struct twihs_msg *msg = &dev_data->msg;
uint32_t isr_status;
u32_t isr_status;
/* Retrieve interrupt status */
isr_status = twihs->TWIHS_SR & twihs->TWIHS_IMR;

24
drivers/interrupt_controller/arcv2_irq_unit.c
View file

@ -28,11 +28,11 @@ extern void *_VectorTable;
#include <kernel_structs.h>
#include <v2/irq.h>
static uint32_t _arc_v2_irq_unit_device_power_state = DEVICE_PM_ACTIVE_STATE;
uint32_t _saved_firq_stack;
static u32_t _arc_v2_irq_unit_device_power_state = DEVICE_PM_ACTIVE_STATE;
u32_t _saved_firq_stack;
struct arc_v2_irq_unit_ctx {
uint32_t irq_ctrl; /* Interrupt Context Saving Control Register. */
uint32_t irq_vect_base; /* Interrupt Vector Base. */
u32_t irq_ctrl; /* Interrupt Context Saving Control Register. */
u32_t irq_vect_base; /* Interrupt Vector Base. */
/*
* IRQ configuration:
@ -40,7 +40,7 @@ struct arc_v2_irq_unit_ctx {
* - IRQ Trigger:BIT(1)
* - IRQ Enable:BIT(0)
*/
uint8_t irq_config[CONFIG_NUM_IRQS - 16];
u8_t irq_config[CONFIG_NUM_IRQS - 16];
};
static struct arc_v2_irq_unit_ctx ctx;
#endif
@ -102,7 +102,7 @@ extern void _firq_stack_resume(void);
static int _arc_v2_irq_unit_suspend(struct device *dev)
{
uint8_t irq;
u8_t irq;
ARG_UNUSED(dev);
@ -132,8 +132,8 @@ static int _arc_v2_irq_unit_suspend(struct device *dev)
static int _arc_v2_irq_unit_resume(struct device *dev)
{
uint8_t irq;
uint32_t status32;
u8_t irq;
u32_t status32;
ARG_UNUSED(dev);
@ -178,16 +178,16 @@ static int _arc_v2_irq_unit_get_state(struct device *dev)
* the *context may include IN data or/and OUT data
*/
static int _arc_v2_irq_unit_device_ctrl(struct device *device,
uint32_t ctrl_command, void *context)
u32_t ctrl_command, void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return _arc_v2_irq_unit_suspend(device);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return _arc_v2_irq_unit_resume(device);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = _arc_v2_irq_unit_get_state(device);
*((u32_t *)context) = _arc_v2_irq_unit_get_state(device);
return 0;
}
return 0;

12
drivers/interrupt_controller/exti_stm32.c
View file

@ -38,17 +38,17 @@
/* 10.3.7 EXTI register map */
struct stm32_exti {
/* EXTI_IMR */
uint32_t imr;
u32_t imr;
/* EXTI_EMR */
uint32_t emr;
u32_t emr;
/* EXTI_RTSR */
uint32_t rtsr;
u32_t rtsr;
/* EXTI_FTSR */
uint32_t ftsr;
u32_t ftsr;
/* EXTI_SWIER */
uint32_t swier;
u32_t swier;
/* EXTI_PR */
uint32_t pr;
u32_t pr;
};
/* wrapper for user callback */

72
drivers/interrupt_controller/ioapic_intr.c
View file

@ -73,17 +73,17 @@
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
#include <power.h>
uint32_t ioapic_suspend_buf[SUSPEND_BITS_REQD / 32] = {0};
static uint32_t ioapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
u32_t ioapic_suspend_buf[SUSPEND_BITS_REQD / 32] = {0};
static u32_t ioapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
#endif
static uint32_t __IoApicGet(int32_t offset);
static void __IoApicSet(int32_t offset, uint32_t value);
static void ioApicRedSetHi(unsigned int irq, uint32_t upper32);
static void ioApicRedSetLo(unsigned int irq, uint32_t lower32);
static uint32_t ioApicRedGetLo(unsigned int irq);
static void _IoApicRedUpdateLo(unsigned int irq, uint32_t value,
uint32_t mask);
static u32_t __IoApicGet(s32_t offset);
static void __IoApicSet(s32_t offset, u32_t value);
static void ioApicRedSetHi(unsigned int irq, u32_t upper32);
static void ioApicRedSetLo(unsigned int irq, u32_t lower32);
static u32_t ioApicRedGetLo(unsigned int irq);
static void _IoApicRedUpdateLo(unsigned int irq, u32_t value,
u32_t mask);
/*
* The functions irq_enable() and irq_disable() are implemented in the
@ -103,8 +103,8 @@ int _ioapic_init(struct device *unused)
{
ARG_UNUSED(unused);
#ifdef CONFIG_IOAPIC_MASK_RTE
int32_t ix; /* redirection table index */
uint32_t rteValue; /* value to copy into redirection table entry */
s32_t ix; /* redirection table index */
u32_t rteValue; /* value to copy into redirection table entry */
/*
* The platform must set the Kconfig option IOAPIC_NUM_RTES to indicate
@ -157,7 +157,7 @@ void _ioapic_irq_disable(unsigned int irq)
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
void store_flags(unsigned int irq, uint32_t flags)
void store_flags(unsigned int irq, u32_t flags)
{
/* Currently only the following three flags are modified */
if (flags & IOAPIC_LOW) {
@ -176,9 +176,9 @@ void store_flags(unsigned int irq, uint32_t flags)
}
}
uint32_t restore_flags(unsigned int irq)
u32_t restore_flags(unsigned int irq)
{
uint32_t flags = 0;
u32_t flags = 0;
if (sys_bitfield_test_bit((mem_addr_t) ioapic_suspend_buf,
BIT_POS_FOR_IRQ_OPTION(irq, IOAPIC_BITFIELD_HI_LO))) {
@ -202,7 +202,7 @@ uint32_t restore_flags(unsigned int irq)
int ioapic_suspend(struct device *port)
{
int irq;
uint32_t rte_lo;
u32_t rte_lo;
ARG_UNUSED(port);
memset(ioapic_suspend_buf, 0, (SUSPEND_BITS_REQD >> 3));
@ -224,8 +224,8 @@ int ioapic_suspend(struct device *port)
int ioapic_resume_from_suspend(struct device *port)
{
int irq;
uint32_t flags;
uint32_t rteValue;
u32_t flags;
u32_t rteValue;
ARG_UNUSED(port);
@ -255,17 +255,17 @@ int ioapic_resume_from_suspend(struct device *port)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int ioapic_device_ctrl(struct device *device, uint32_t ctrl_command,
static int ioapic_device_ctrl(struct device *device, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return ioapic_suspend(device);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return ioapic_resume_from_suspend(device);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = ioapic_device_power_state;
*((u32_t *)context) = ioapic_device_power_state;
return 0;
}
return 0;
@ -285,9 +285,9 @@ static int ioapic_device_ctrl(struct device *device, uint32_t ctrl_command,
*
* @return N/A
*/
void _ioapic_irq_set(unsigned int irq, unsigned int vector, uint32_t flags)
void _ioapic_irq_set(unsigned int irq, unsigned int vector, u32_t flags)
{
uint32_t rteValue; /* value to copy into redirection table entry */
u32_t rteValue; /* value to copy into redirection table entry */
rteValue = IOAPIC_FIXED | IOAPIC_INT_MASK | IOAPIC_PHYSICAL |
(vector & IOAPIC_VEC_MASK) | flags;
@ -320,9 +320,9 @@ void _ioapic_int_vec_set(unsigned int irq, unsigned int vector)
*
* @return register value
*/
static uint32_t __IoApicGet(int32_t offset)
static u32_t __IoApicGet(s32_t offset)
{
uint32_t value; /* value */
u32_t value; /* value */
int key; /* interrupt lock level */
/* lock interrupts to ensure indirect addressing works "atomically" */
@ -331,7 +331,7 @@ static uint32_t __IoApicGet(int32_t offset)
*((volatile char *)
(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND)) = (char)offset;
value = *((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA));
value = *((volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA));
irq_unlock(key);
@ -348,7 +348,7 @@ static uint32_t __IoApicGet(int32_t offset)
* @param value Value to set the register
* @return N/A
*/
static void __IoApicSet(int32_t offset, uint32_t value)
static void __IoApicSet(s32_t offset, u32_t value)
{
int key; /* interrupt lock level */
@ -357,7 +357,7 @@ static void __IoApicSet(int32_t offset, uint32_t value)
key = irq_lock();
*(volatile char *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND) = (char)offset;
*((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value;
*((volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value;
irq_unlock(key);
}
@ -371,9 +371,9 @@ static void __IoApicSet(int32_t offset, uint32_t value)
* @param irq INTIN number
* @return 32 low-order bits
*/
static uint32_t ioApicRedGetLo(unsigned int irq)
static u32_t ioApicRedGetLo(unsigned int irq)
{
int32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
s32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
return __IoApicGet(offset);
}
@ -388,9 +388,9 @@ static uint32_t ioApicRedGetLo(unsigned int irq)
* @param lower32 Value to be written
* @return N/A
*/
static void ioApicRedSetLo(unsigned int irq, uint32_t lower32)
static void ioApicRedSetLo(unsigned int irq, u32_t lower32)
{
int32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
s32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
__IoApicSet(offset, lower32);
}
@ -405,9 +405,9 @@ static void ioApicRedSetLo(unsigned int irq, uint32_t lower32)
* @param upper32 Value to be written
* @return N/A
*/
static void ioApicRedSetHi(unsigned int irq, uint32_t upper32)
static void ioApicRedSetHi(unsigned int irq, u32_t upper32)
{
int32_t offset = IOAPIC_REDTBL + (irq << 1) + 1; /* register offset */
s32_t offset = IOAPIC_REDTBL + (irq << 1) + 1; /* register offset */
__IoApicSet(offset, upper32);
}
@ -425,8 +425,8 @@ static void ioApicRedSetHi(unsigned int irq, uint32_t upper32)
* @return N/A
*/
static void _IoApicRedUpdateLo(unsigned int irq,
uint32_t value,
uint32_t mask)
u32_t value,
u32_t mask)
{
ioApicRedSetLo(irq, (ioApicRedGetLo(irq) & ~mask) | (value & mask));
}

20
drivers/interrupt_controller/loapic_intr.c
View file

@ -184,8 +184,8 @@
#define LOPIC_SUSPEND_BITS_REQD (ROUND_UP((LOAPIC_IRQ_COUNT * LOPIC_SSPND_BITS_PER_IRQ), 32))
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
#include <power.h>
uint32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
static uint32_t loapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
u32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
static u32_t loapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
#endif
@ -202,7 +202,7 @@ static uint32_t loapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
static int _loapic_init(struct device *unused)
{
ARG_UNUSED(unused);
int32_t loApicMaxLvt; /* local APIC Max LVT */
s32_t loApicMaxLvt; /* local APIC Max LVT */
/* enable the Local APIC */
sys_write32(sys_read32(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR)
@ -282,7 +282,7 @@ void _loapic_int_vec_set(unsigned int irq, /* IRQ number of the interrupt */
)
{
volatile int *pLvt; /* pointer to local vector table */
int32_t oldLevel; /* previous interrupt lock level */
s32_t oldLevel; /* previous interrupt lock level */
/*
* The following mappings are used:
@ -321,7 +321,7 @@ void _loapic_int_vec_set(unsigned int irq, /* IRQ number of the interrupt */
void _loapic_irq_enable(unsigned int irq)
{
volatile int *pLvt; /* pointer to local vector table */
int32_t oldLevel; /* previous interrupt lock level */
s32_t oldLevel; /* previous interrupt lock level */
/*
* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
@ -352,7 +352,7 @@ void _loapic_irq_enable(unsigned int irq)
void _loapic_irq_disable(unsigned int irq)
{
volatile int *pLvt; /* pointer to local vector table */
int32_t oldLevel; /* previous interrupt lock level */
s32_t oldLevel; /* previous interrupt lock level */
/*
* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
@ -479,17 +479,17 @@ int loapic_resume(struct device *port)
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int loapic_device_ctrl(struct device *port, uint32_t ctrl_command,
static int loapic_device_ctrl(struct device *port, u32_t ctrl_command,
void *context)
{
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((uint32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
return loapic_suspend(port);
} else if (*((uint32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
return loapic_resume(port);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((uint32_t *)context) = loapic_device_power_state;
*((u32_t *)context) = loapic_device_power_state;
return 0;
}

12
drivers/interrupt_controller/mvic.c
View file

@ -40,7 +40,7 @@
#include <arch/x86/irq_controller.h>
#include <inttypes.h>
static inline uint32_t compute_ioregsel(unsigned int irq)
static inline u32_t compute_ioregsel(unsigned int irq)
{
unsigned int low_nibble;
unsigned int high_nibble;
@ -62,10 +62,10 @@ static inline uint32_t compute_ioregsel(unsigned int irq)
*
* @returns N/A
*/
static void _mvic_rte_set(unsigned int irq, uint32_t value)
static void _mvic_rte_set(unsigned int irq, u32_t value)
{
int key; /* interrupt lock level */
uint32_t regsel;
u32_t regsel;
__ASSERT(!(value & ~MVIC_IOWIN_SUPPORTED_BITS_MASK),
"invalid IRQ flags %" PRIx32 " for irq %d", value, irq);
@ -92,10 +92,10 @@ static void _mvic_rte_set(unsigned int irq, uint32_t value)
*
* @returns N/A
*/
static void _mvic_rte_update(unsigned int irq, uint32_t value, uint32_t mask)
static void _mvic_rte_update(unsigned int irq, u32_t value, u32_t mask)
{
int key;
uint32_t regsel, old_value, updated_value;
u32_t regsel, old_value, updated_value;
__ASSERT(!(value & ~MVIC_IOWIN_SUPPORTED_BITS_MASK),
"invalid IRQ flags %" PRIx32 " for irq %d", value, irq);
@ -177,7 +177,7 @@ void _arch_irq_disable(unsigned int irq)
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
uint32_t flags)
u32_t flags)
{
ARG_UNUSED(vector);

48
drivers/interrupt_controller/plic_fe310.c
View file

@ -19,8 +19,8 @@
#define PLIC_FE310_EN_SIZE ((PLIC_FE310_IRQS >> 5) + 1)
struct plic_fe310_regs_t {
uint32_t threshold_prio;
uint32_t claim_complete;
u32_t threshold_prio;
u32_t claim_complete;
};
static int save_irq;
@ -38,12 +38,12 @@ static int save_irq;
*
* @return N/A
*/
void riscv_plic_irq_enable(uint32_t irq)
void riscv_plic_irq_enable(u32_t irq)
{
uint32_t key;
uint32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile uint32_t *en =
(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
u32_t key;
u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
key = irq_lock();
en += (fe310_irq >> 5);
@ -64,12 +64,12 @@ void riscv_plic_irq_enable(uint32_t irq)
*
* @return N/A
*/
void riscv_plic_irq_disable(uint32_t irq)
void riscv_plic_irq_disable(u32_t irq)
{
uint32_t key;
uint32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile uint32_t *en =
(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
u32_t key;
u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
key = irq_lock();
en += (fe310_irq >> 5);
@ -86,11 +86,11 @@ void riscv_plic_irq_disable(uint32_t irq)
*
* @return 1 or 0
*/
int riscv_plic_irq_is_enabled(uint32_t irq)
int riscv_plic_irq_is_enabled(u32_t irq)
{
volatile uint32_t *en =
(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
uint32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
u32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
en += (fe310_irq >> 5);
return !!(*en & (1 << (fe310_irq & 31)));
@ -107,10 +107,10 @@ int riscv_plic_irq_is_enabled(uint32_t irq)
*
* @return N/A
*/
void riscv_plic_set_priority(uint32_t irq, uint32_t priority)
void riscv_plic_set_priority(u32_t irq, u32_t priority)
{
volatile uint32_t *prio =
(volatile uint32_t *)FE310_PLIC_PRIO_BASE_ADDR;
volatile u32_t *prio =
(volatile u32_t *)FE310_PLIC_PRIO_BASE_ADDR;
/* Can set priority only for PLIC-specific interrupt line */
if (irq <= RISCV_MAX_GENERIC_IRQ)
@ -143,7 +143,7 @@ static void plic_fe310_irq_handler(void *arg)
volatile struct plic_fe310_regs_t *regs =
(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
uint32_t irq;
u32_t irq;
struct _isr_table_entry *ite;
/* Get the IRQ number generating the interrupt */
@ -186,10 +186,10 @@ static int plic_fe310_init(struct device *dev)
{
ARG_UNUSED(dev);
volatile uint32_t *en =
(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
volatile uint32_t *prio =
(volatile uint32_t *)FE310_PLIC_PRIO_BASE_ADDR;
volatile u32_t *en =
(volatile u32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
volatile u32_t *prio =
(volatile u32_t *)FE310_PLIC_PRIO_BASE_ADDR;
volatile struct plic_fe310_regs_t *regs =
(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
int i;

2
drivers/interrupt_controller/system_apic.c
View file

@ -45,7 +45,7 @@
*
*/
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
uint32_t flags)
u32_t flags)
{
__ASSERT(irq >= 0 && irq <= HARDWARE_IRQ_LIMIT, "invalid irq line");

12
drivers/ipm/ipm_quark_se.c
View file

@ -24,9 +24,9 @@
* in incoming channel
*/
static struct device *device_by_channel[QUARK_SE_IPM_CHANNELS];
static uint32_t inbound_channels;
static u32_t inbound_channels;
static uint32_t quark_se_ipm_sts_get(void)
static u32_t quark_se_ipm_sts_get(void)
{
return sys_read32(QUARK_SE_IPM_CHALL_STS) & inbound_channels;
}
@ -87,12 +87,12 @@ void quark_se_ipm_isr(void *param)
}
static int quark_se_ipm_send(struct device *d, int wait, uint32_t id,
static int quark_se_ipm_send(struct device *d, int wait, u32_t id,
const void *data, int size)
{
const struct quark_se_ipm_config_info *config = d->config->config_info;
volatile struct quark_se_ipm *ipm = config->ipm;
const uint8_t *data8;
const u8_t *data8;
int i;
int flags;
@ -116,7 +116,7 @@ static int quark_se_ipm_send(struct device *d, int wait, uint32_t id,
}
/* Populate the data, memcpy doesn't take volatiles */
data8 = (const uint8_t *)data;
data8 = (const u8_t *)data;
for (i = 0; i < size; ++i) {
ipm->data[i] = data8[i];
@ -148,7 +148,7 @@ static int quark_se_ipm_max_data_size_get(struct device *d)
}
static uint32_t quark_se_ipm_max_id_val_get(struct device *d)
static u32_t quark_se_ipm_max_id_val_get(struct device *d)
{
ARG_UNUSED(d);

14
drivers/ipm/ipm_quark_se.h
View file

@ -42,24 +42,24 @@ extern "C" {
#endif
#define QUARK_SE_IPM_CHANNELS 8
#define QUARK_SE_IPM_DATA_BYTES (4 * sizeof(uint32_t))
#define QUARK_SE_IPM_DATA_BYTES (4 * sizeof(u32_t))
#define QUARK_SE_IPM_MAX_ID_VAL 0x7FFFFFFF
/* QUARK_SE EAS section 28.5.1.123 */
struct __packed quark_se_ipm_ch_ctrl {
uint32_t ctrl : 31;
uint32_t irq : 1;
u32_t ctrl : 31;
u32_t irq : 1;
};
struct __packed quark_se_ipm_ch_sts {
uint32_t sts : 1;
uint32_t irq : 1;
uint32_t reserved : 30;
u32_t sts : 1;
u32_t irq : 1;
u32_t reserved : 30;
};
struct __packed quark_se_ipm {
struct quark_se_ipm_ch_ctrl ctrl;
uint8_t data[QUARK_SE_IPM_DATA_BYTES]; /* contiguous 32-bit registers */
u8_t data[QUARK_SE_IPM_DATA_BYTES]; /* contiguous 32-bit registers */
struct quark_se_ipm_ch_sts sts;
};

42
drivers/pci/pci.c
View file

@ -105,12 +105,12 @@
struct lookup_data {
struct pci_dev_info info;
uint32_t bus:9;
uint32_t dev:6;
uint32_t func:4;
uint32_t baridx:3;
uint32_t barofs:3;
uint32_t unused:7;
u32_t bus:9;
u32_t dev:6;
u32_t func:4;
u32_t baridx:3;
u32_t barofs:3;
u32_t unused:7;
};
static struct lookup_data __noinit lookup;
@ -123,9 +123,9 @@ static struct lookup_data __noinit lookup;
*/
static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
uint32_t *config)
u32_t *config)
{
uint32_t old_value;
u32_t old_value;
/* save the current setting */
pci_read(DEFAULT_PCI_CONTROLLER,
@ -136,7 +136,7 @@ static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
/* write to the BAR to see how large it is */
pci_write(DEFAULT_PCI_CONTROLLER,
pci_ctrl_addr,
sizeof(uint32_t),
sizeof(u32_t),
0xffffffff);
pci_read(DEFAULT_PCI_CONTROLLER,
@ -172,11 +172,11 @@ static inline int pci_bar_params_get(union pci_addr_reg pci_ctrl_addr,
struct pci_dev_info *dev_info,
int max_bars)
{
uint32_t bar_value;
uint32_t bar_config;
uint32_t bar_hival;
uint32_t addr;
uint32_t mask;
u32_t bar_value;
u32_t bar_config;
u32_t bar_hival;
u32_t addr;
u32_t mask;
pci_ctrl_addr.field.reg = 4 + lookup.barofs;
@ -231,7 +231,7 @@ static inline int pci_dev_scan(union pci_addr_reg pci_ctrl_addr,
struct pci_dev_info *dev_info)
{
static union pci_dev pci_dev_header;
uint32_t pci_data;
u32_t pci_data;
int max_bars;
/* verify first if there is a valid device at this point */
@ -408,10 +408,10 @@ int pci_bus_scan(struct pci_dev_info *dev_info)
}
#endif /* CONFIG_PCI_ENUMERATION */
static void pci_set_command_bits(struct pci_dev_info *dev_info, uint32_t bits)
static void pci_set_command_bits(struct pci_dev_info *dev_info, u32_t bits)
{
union pci_addr_reg pci_ctrl_addr;
uint32_t pci_data;
u32_t pci_data;
pci_ctrl_addr.value = 0;
pci_ctrl_addr.field.func = dev_info->function;
@ -425,14 +425,14 @@ static void pci_set_command_bits(struct pci_dev_info *dev_info, uint32_t bits)
pci_read(DEFAULT_PCI_CONTROLLER,
pci_ctrl_addr,
sizeof(uint16_t),
sizeof(u16_t),
&pci_data);
pci_data = pci_data | bits;
pci_write(DEFAULT_PCI_CONTROLLER,
pci_ctrl_addr,
sizeof(uint16_t),
sizeof(u16_t),
pci_data);
}
@ -469,8 +469,8 @@ void pci_show(struct pci_dev_info *dev_info)
dev_info->function,
dev_info->bar,
(dev_info->mem_type == BAR_SPACE_MEM) ? "MEM" : "I/O",
(uint32_t)dev_info->addr,
(uint32_t)(dev_info->addr + dev_info->size - 1),
(u32_t)dev_info->addr,
(u32_t)(dev_info->addr + dev_info->size - 1),
dev_info->irq);
}
#endif /* CONFIG_PCI_DEBUG */

60
drivers/pci/pci_config.c
View file

@ -31,8 +31,8 @@
*
* @return N/A
*/
void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint32_t data)
void pci_config_out_long(u32_t bus_no, u32_t device_no, u32_t func_no,
u32_t offset, u32_t data)
{
union pci_addr_reg pci_addr;
@ -46,7 +46,7 @@ void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
/* write to the PCI controller */
pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint32_t), data);
pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(u32_t), data);
}
/**
@ -61,8 +61,8 @@ void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
*
* @return N/A
*/
void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint16_t data)
void pci_config_out_word(u32_t bus_no, u32_t device_no, u32_t func_no,
u32_t offset, u16_t data)
{
union pci_addr_reg pci_addr;
@ -76,7 +76,7 @@ void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
/* write to the PCI controller */
pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint16_t), data);
pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(u16_t), data);
}
/**
@ -91,8 +91,8 @@ void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
*
* @return N/A
*/
void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint8_t data)
void pci_config_out_byte(u32_t bus_no, u32_t device_no, u32_t func_no,
u32_t offset, u8_t data)
{
union pci_addr_reg pci_addr;
@ -106,7 +106,7 @@ void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
/* write to the PCI controller */
pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint8_t), data);
pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(u8_t), data);
}
/**
@ -122,8 +122,8 @@ void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
* @return N/A
*
*/
void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint32_t *data)
void pci_config_in_long(u32_t bus_no, u32_t device_no, u32_t func_no,
u32_t offset, u32_t *data)
{
union pci_addr_reg pci_addr;
@ -137,7 +137,7 @@ void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
/* read from the PCI controller */
pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint32_t), data);
pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(u32_t), data);
}
/**
@ -154,11 +154,11 @@ void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
*
*/
void pci_config_in_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint16_t *data)
void pci_config_in_word(u32_t bus_no, u32_t device_no, u32_t func_no,
u32_t offset, u16_t *data)
{
union pci_addr_reg pci_addr;
uint32_t pci_data;
u32_t pci_data;
/* create the PCI address we're going to access */
@ -170,11 +170,11 @@ void pci_config_in_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
/* read from the PCI controller */
pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint16_t), &pci_data);
pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(u16_t), &pci_data);
/* return the data */
*data = (uint16_t)pci_data;
*data = (u16_t)pci_data;
}
/**
@ -191,11 +191,11 @@ void pci_config_in_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
*
*/
void pci_config_in_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint8_t *data)
void pci_config_in_byte(u32_t bus_no, u32_t device_no, u32_t func_no,
u32_t offset, u8_t *data)
{
union pci_addr_reg pci_addr;
uint32_t pci_data;
u32_t pci_data;
/* create the PCI address we're going to access */
@ -207,11 +207,11 @@ void pci_config_in_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
/* read from the PCI controller */
pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint8_t), &pci_data);
pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(u8_t), &pci_data);
/* return the data */
*data = (uint8_t)pci_data;
*data = (u8_t)pci_data;
}
/**
@ -232,14 +232,14 @@ void pci_config_in_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
*
*/
int pci_config_ext_cap_ptr_find(uint8_t ext_cap_find_id, uint32_t bus,
uint32_t device, uint32_t function,
uint8_t *p_offset)
int pci_config_ext_cap_ptr_find(u8_t ext_cap_find_id, u32_t bus,
u32_t device, u32_t function,
u8_t *p_offset)
{
uint16_t tmp_stat;
uint8_t tmp_offset;
uint8_t cap_offset = 0x00;
uint8_t cap_id = 0x00;
u16_t tmp_stat;
u8_t tmp_offset;
u8_t cap_offset = 0x00;
u8_t cap_id = 0x00;
/* Check to see if the device has any extended capabilities */
@ -274,7 +274,7 @@ int pci_config_ext_cap_ptr_find(uint8_t ext_cap_find_id, uint32_t bus,
/* Get the offset to the next New Capabilities item */
tmp_offset = cap_offset + (uint8_t)0x01;
tmp_offset = cap_offset + (u8_t)0x01;
pci_config_in_byte(bus, device, function, (int)tmp_offset, &cap_offset);
}

46
drivers/pci/pci_interface.c
View file

@ -42,7 +42,7 @@
*
*/
static void pci_ctrl_read(uint32_t reg, uint32_t *data, uint32_t size)
static void pci_ctrl_read(u32_t reg, u32_t *data, u32_t size)
{
/* read based on the size requested */
@ -77,7 +77,7 @@ static void pci_ctrl_read(uint32_t reg, uint32_t *data, uint32_t size)
*
*/
static void pci_ctrl_write(uint32_t reg, uint32_t data, uint32_t size)
static void pci_ctrl_write(u32_t reg, u32_t data, u32_t size)
{
/* write based on the size requested */
@ -112,8 +112,8 @@ static void pci_ctrl_write(uint32_t reg, uint32_t data, uint32_t size)
*
*/
static int pci_ctrl_data_read(uint32_t controller, uint32_t offset,
uint32_t *data, uint32_t size)
static int pci_ctrl_data_read(u32_t controller, u32_t offset,
u32_t *data, u32_t size)
{
/* we only support one controller */
@ -142,8 +142,8 @@ static int pci_ctrl_data_read(uint32_t controller, uint32_t offset,
*
*/
static int pci_ctrl_data_write(uint32_t controller, uint32_t offset,
uint32_t data, uint32_t size)
static int pci_ctrl_data_write(u32_t controller, u32_t offset,
u32_t data, u32_t size)
{
/* we only support one controller */
@ -172,8 +172,8 @@ static int pci_ctrl_data_write(uint32_t controller, uint32_t offset,
*
*/
static int pci_ctrl_addr_write(uint32_t controller, uint32_t offset,
uint32_t data, uint32_t size)
static int pci_ctrl_addr_write(u32_t controller, u32_t offset,
u32_t data, u32_t size)
{
/* we only support one controller */
@ -213,7 +213,7 @@ static int pci_ctrl_addr_write(uint32_t controller, uint32_t offset,
* Example:
*
* union pci_addr_reg addr;
* uint32_t status;
* u32_t status;
*
* addr.field.bus = 0; /@ PCI bus zero @/
* addr.field.device = 1; /@ PCI device one @/
@ -221,7 +221,7 @@ static int pci_ctrl_addr_write(uint32_t controller, uint32_t offset,
* addr.field.reg = 4; /@ PCI register 4 @/
* addr.field.offset = 0; /@ PCI register offset @/
*
* pci_read (DEFAULT_PCI_CONTROLLER, addr, sizeof(uint16_t), &status);
* pci_read (DEFAULT_PCI_CONTROLLER, addr, sizeof(u16_t), &status);
*
*
* NOTE:
@ -237,11 +237,11 @@ static int pci_ctrl_addr_write(uint32_t controller, uint32_t offset,
*
*/
void pci_read(uint32_t controller, union pci_addr_reg addr,
uint32_t size, uint32_t *data)
void pci_read(u32_t controller, union pci_addr_reg addr,
u32_t size, u32_t *data)
{
uint32_t access_size;
uint32_t access_offset;
u32_t access_size;
u32_t access_offset;
/* validate the access size */
@ -305,7 +305,7 @@ void pci_read(uint32_t controller, union pci_addr_reg addr,
* Example:
*
* pci_addr_t addr;
* uint32_t bar0 = 0xE0000000;
* u32_t bar0 = 0xE0000000;
*
* addr.field.bus = 0; /@ PCI bus zero @/
* addr.field.device = 1; /@ PCI device one @/
@ -313,7 +313,7 @@ void pci_read(uint32_t controller, union pci_addr_reg addr,
* addr.field.reg = 16; /@ PCI register 16 @/
* addr.field.offset = 0; /@ PCI register offset @/
*
* pci_write (DEFAULT_PCI_CONTROLLER, addr, sizeof(uint32_t), bar0);
* pci_write (DEFAULT_PCI_CONTROLLER, addr, sizeof(u32_t), bar0);
*
* NOTE:
* Writing of PCI data must be performed as an atomic operation. It is up to
@ -328,11 +328,11 @@ void pci_read(uint32_t controller, union pci_addr_reg addr,
*
*/
void pci_write(uint32_t controller, union pci_addr_reg addr,
uint32_t size, uint32_t data)
void pci_write(u32_t controller, union pci_addr_reg addr,
u32_t size, u32_t data)
{
uint32_t access_size;
uint32_t access_offset;
u32_t access_size;
u32_t access_offset;
/* validate the access size */
@ -377,11 +377,11 @@ void pci_write(uint32_t controller, union pci_addr_reg addr,
* @return N/A
*/
void pci_header_get(uint32_t controller,
void pci_header_get(u32_t controller,
union pci_addr_reg pci_ctrl_addr,
union pci_dev *pci_dev_header)
{
uint32_t i;
u32_t i;
/* clear out the header */
@ -393,7 +393,7 @@ void pci_header_get(uint32_t controller,
pci_ctrl_addr.field.reg = i;
pci_read(controller,
pci_ctrl_addr,
sizeof(uint32_t),
sizeof(u32_t),
&pci_dev_header->words.word[i]);
}
}

16
drivers/pci/pci_legacy_bridge.c
View file

@ -41,9 +41,9 @@
*/
static int pci_rcba_mask_get(union pci_addr_reg pci_ctrl_addr,
uint32_t *mask)
u32_t *mask)
{
uint32_t old_value;
u32_t old_value;
/* save the current setting */
pci_read(DEFAULT_PCI_CONTROLLER,
@ -54,7 +54,7 @@ static int pci_rcba_mask_get(union pci_addr_reg pci_ctrl_addr,
/* write to the RCBA to see how large it is */
pci_write(DEFAULT_PCI_CONTROLLER,
pci_ctrl_addr,
sizeof(uint32_t),
sizeof(u32_t),
0xffffffff);
pci_read(DEFAULT_PCI_CONTROLLER,
@ -94,9 +94,9 @@ int pci_legacy_bridge_detect(struct pci_dev_info *dev_info)
{
union pci_addr_reg pci_ctrl_addr;
static union pci_dev pci_dev_header;
uint32_t pci_data; /* temporary data to read */
uint32_t rcba; /* root complex base address */
uint32_t rcba_mask; /* bits set for RCBA */
u32_t pci_data; /* temporary data to read */
u32_t rcba; /* root complex base address */
u32_t rcba_mask; /* bits set for RCBA */
/* initialise the PCI controller address register value */
pci_ctrl_addr.value = 0;
@ -176,7 +176,7 @@ void pci_legacy_bridge_configure(struct pci_dev_info *dev_info,
int pci_interrupt_pin,
int irq_number)
{
uint32_t addr = (io_block_num == 0) ? PCI_ADDR_IRQAGENT1 :
u32_t addr = (io_block_num == 0) ? PCI_ADDR_IRQAGENT1 :
PCI_ADDR_IRQAGENT3;
/*
* Each interrupt queue agent register in PCI legacy
@ -188,7 +188,7 @@ void pci_legacy_bridge_configure(struct pci_dev_info *dev_info,
* Bits 3:0 indicates which IRQ is used for INTA.
*/
int offset = (pci_interrupt_pin - 1) * 4;
uint16_t irq_routing = sys_read16(dev_info->addr + addr);
u16_t irq_routing = sys_read16(dev_info->addr + addr);
irq_routing &= ~(0x0f << offset);
irq_routing |= (irq_number - NUM_STD_IRQS) << offset;

4
drivers/pinmux/beetle/pinmux_board_v2m_beetle.c
View file

@ -94,8 +94,8 @@
*/
static void arm_v2m_beetle_pinmux_defaults(void)
{
uint32_t gpio_0 = 0;
uint32_t gpio_1 = 0;
u32_t gpio_0 = 0;
u32_t gpio_1 = 0;
/* Set GPIO Alternate Functions */

16
drivers/pinmux/dev/pinmux_dev_arm_beetle.c
View file

@ -22,9 +22,9 @@
#define CMSDK_AHB_GPIO1_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1)
static volatile struct gpio_cmsdk_ahb *_get_port(uint32_t pin)
static volatile struct gpio_cmsdk_ahb *_get_port(u32_t pin)
{
uint32_t port_num = pin / PINS_PER_PORT;
u32_t port_num = pin / PINS_PER_PORT;
/* Port 2 and 3 are reserved therefore not handled in this driver */
switch (port_num) {
@ -38,11 +38,11 @@ static volatile struct gpio_cmsdk_ahb *_get_port(uint32_t pin)
}
}
static int pinmux_set(struct device *dev, uint32_t pin, uint32_t func)
static int pinmux_set(struct device *dev, u32_t pin, u32_t func)
{
volatile struct gpio_cmsdk_ahb *port = _get_port(pin);
uint32_t tmp;
uint32_t key;
u32_t tmp;
u32_t key;
ARG_UNUSED(dev);
@ -79,7 +79,7 @@ static int pinmux_set(struct device *dev, uint32_t pin, uint32_t func)
return 0;
}
static int pinmux_get(struct device *dev, uint32_t pin, uint32_t *func)
static int pinmux_get(struct device *dev, u32_t pin, u32_t *func)
{
volatile struct gpio_cmsdk_ahb *port = _get_port(pin);
@ -94,7 +94,7 @@ static int pinmux_get(struct device *dev, uint32_t pin, uint32_t *func)
return 0;
}
static int pinmux_pullup(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_pullup(struct device *dev, u32_t pin, u8_t func)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);
@ -106,7 +106,7 @@ static int pinmux_pullup(struct device *dev, uint32_t pin, uint8_t func)
return 0;
}
static int pinmux_input(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_input(struct device *dev, u32_t pin, u8_t func)
{
volatile struct gpio_cmsdk_ahb *port = _get_port(pin);

14
drivers/pinmux/dev/pinmux_dev_atmel_sam3x.c
View file

@ -13,9 +13,9 @@
#include <soc.h>
#include <misc/util.h>
static volatile struct __pio *_get_port(uint32_t pin)
static volatile struct __pio *_get_port(u32_t pin)
{
uint32_t port_num = pin / 32;
u32_t port_num = pin / 32;
switch (port_num) {
case 0:
@ -32,10 +32,10 @@ static volatile struct __pio *_get_port(uint32_t pin)
}
}
static int pinmux_set(struct device *dev, uint32_t pin, uint32_t func)
static int pinmux_set(struct device *dev, u32_t pin, u32_t func)
{
volatile struct __pio *port = _get_port(pin);
uint32_t tmp;
u32_t tmp;
ARG_UNUSED(dev);
@ -54,7 +54,7 @@ static int pinmux_set(struct device *dev, uint32_t pin, uint32_t func)
return 0;
}
static int pinmux_get(struct device *dev, uint32_t pin, uint32_t *func)
static int pinmux_get(struct device *dev, u32_t pin, u32_t *func)
{
volatile struct __pio *port = _get_port(pin);
@ -69,7 +69,7 @@ static int pinmux_get(struct device *dev, uint32_t pin, uint32_t *func)
return 0;
}
static int pinmux_pullup(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_pullup(struct device *dev, u32_t pin, u8_t func)
{
volatile struct __pio *port = _get_port(pin);
@ -87,7 +87,7 @@ static int pinmux_pullup(struct device *dev, uint32_t pin, uint8_t func)
return 0;
}
static int pinmux_input(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_input(struct device *dev, u32_t pin, u8_t func)
{
volatile struct __pio *port = _get_port(pin);

8
drivers/pinmux/dev/pinmux_dev_k64.c
View file

@ -14,16 +14,16 @@
#include <sys_io.h>
#include <pinmux/k64/pinmux.h>
static int fsl_k64_dev_set(struct device *dev, uint32_t pin,
uint32_t func)
static int fsl_k64_dev_set(struct device *dev, u32_t pin,
u32_t func)
{
ARG_UNUSED(dev);
return _fsl_k64_set_pin(pin, func);
}
static int fsl_k64_dev_get(struct device *dev, uint32_t pin,
uint32_t *func)
static int fsl_k64_dev_get(struct device *dev, u32_t pin,
u32_t *func)
{
ARG_UNUSED(dev);

12
drivers/pinmux/dev/pinmux_dev_stm32.c
View file

@ -21,7 +21,7 @@
#include <pinmux/stm32/pinmux_stm32.h>
static int pinmux_stm32_set(struct device *dev,
uint32_t pin, uint32_t func)
u32_t pin, u32_t func)
{
ARG_UNUSED(dev);
@ -29,7 +29,7 @@ static int pinmux_stm32_set(struct device *dev,
}
static int pinmux_stm32_get(struct device *dev,
uint32_t pin, uint32_t *func)
u32_t pin, u32_t *func)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);
@ -39,8 +39,8 @@ static int pinmux_stm32_get(struct device *dev,
}
static int pinmux_stm32_input(struct device *dev,
uint32_t pin,
uint8_t func)
u32_t pin,
u8_t func)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);
@ -50,8 +50,8 @@ static int pinmux_stm32_input(struct device *dev,
}
static int pinmux_stm32_pullup(struct device *dev,
uint32_t pin,
uint8_t func)
u32_t pin,
u8_t func)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);

6
drivers/pinmux/pinmux.h
View file

@ -16,12 +16,12 @@ extern "C" {
#endif
struct pin_config {
uint8_t pin_num;
uint32_t mode;
u8_t pin_num;
u32_t mode;
};
struct pinmux_config {
uint32_t base_address;
u32_t base_address;
};
#ifdef __cplusplus

14
drivers/pinmux/pinmux_fe310.c
View file

@ -14,12 +14,12 @@
#include <soc.h>
struct pinmux_fe310_config {
uint32_t base;
u32_t base;
};
struct pinmux_fe310_regs_t {
uint32_t iof_en;
uint32_t iof_sel;
u32_t iof_en;
u32_t iof_sel;
};
#define DEV_CFG(dev) \
@ -29,7 +29,7 @@ struct pinmux_fe310_regs_t {
#define DEV_PINMUX(dev) \
((struct pinmux_fe310_regs_t *)(DEV_CFG(dev))->base)
static int pinmux_fe310_set(struct device *dev, uint32_t pin, uint32_t func)
static int pinmux_fe310_set(struct device *dev, u32_t pin, u32_t func)
{
volatile struct pinmux_fe310_regs_t *pinmux = DEV_PINMUX(dev);
@ -48,7 +48,7 @@ static int pinmux_fe310_set(struct device *dev, uint32_t pin, uint32_t func)
return 0;
}
static int pinmux_fe310_get(struct device *dev, uint32_t pin, uint32_t *func)
static int pinmux_fe310_get(struct device *dev, u32_t pin, u32_t *func)
{
volatile struct pinmux_fe310_regs_t *pinmux = DEV_PINMUX(dev);
@ -62,12 +62,12 @@ static int pinmux_fe310_get(struct device *dev, uint32_t pin, uint32_t *func)
return 0;
}
static int pinmux_fe310_pullup(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_fe310_pullup(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}
static int pinmux_fe310_input(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_fe310_input(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}

8
drivers/pinmux/pinmux_mcux.c
View file

@ -15,7 +15,7 @@ struct pinmux_mcux_config {
PORT_Type *base;
};
static int pinmux_mcux_set(struct device *dev, uint32_t pin, uint32_t func)
static int pinmux_mcux_set(struct device *dev, u32_t pin, u32_t func)
{
const struct pinmux_mcux_config *config = dev->config->config_info;
PORT_Type *base = config->base;
@ -25,7 +25,7 @@ static int pinmux_mcux_set(struct device *dev, uint32_t pin, uint32_t func)
return 0;
}
static int pinmux_mcux_get(struct device *dev, uint32_t pin, uint32_t *func)
static int pinmux_mcux_get(struct device *dev, u32_t pin, u32_t *func)
{
const struct pinmux_mcux_config *config = dev->config->config_info;
PORT_Type *base = config->base;
@ -35,12 +35,12 @@ static int pinmux_mcux_get(struct device *dev, uint32_t pin, uint32_t *func)
return 0;
}
static int pinmux_mcux_pullup(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_mcux_pullup(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}
static int pinmux_mcux_input(struct device *dev, uint32_t pin, uint8_t func)
static int pinmux_mcux_input(struct device *dev, u32_t pin, u8_t func)
{
return -ENOTSUP;
}

28
drivers/pinmux/pinmux_qmsi.c
View file

@ -13,16 +13,16 @@
#define MASK_2_BITS 0x3
static int pinmux_set(struct device *dev, uint32_t pin,
uint32_t func)
static int pinmux_set(struct device *dev, u32_t pin,
u32_t func)
{
ARG_UNUSED(dev);
return qm_pmux_select(pin, func) == 0 ? 0 : -EIO;
}
static int pinmux_get(struct device *dev, uint32_t pin,
uint32_t *func)
static int pinmux_get(struct device *dev, u32_t pin,
u32_t *func)
{
ARG_UNUSED(dev);
@ -31,40 +31,40 @@ static int pinmux_get(struct device *dev, uint32_t pin,
* 2 bits to set the mode (A, B, C, or D). As such we only get 16
* pins per register.
*/
uint32_t reg_offset = pin >> 4;
u32_t reg_offset = pin >> 4;
/* The pin offset within the register */
uint32_t pin_no = pin % 16;
u32_t pin_no = pin % 16;
/*
* Now figure out what is the full address for the register
* we are looking for.
*/
volatile uint32_t *mux_register = &QM_SCSS_PMUX->pmux_sel[reg_offset];
volatile u32_t *mux_register = &QM_SCSS_PMUX->pmux_sel[reg_offset];
/*
* MASK_2_BITS (the value of which is 3) is used because there are
* 2 bits for the mode of each pin.
*/
uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
uint32_t mode_mask = *mux_register & pin_mask;
uint32_t mode = mode_mask >> (pin_no << 1);
u32_t pin_mask = MASK_2_BITS << (pin_no << 1);
u32_t mode_mask = *mux_register & pin_mask;
u32_t mode = mode_mask >> (pin_no << 1);
*func = mode;
return 0;
}
static int pinmux_pullup(struct device *dev, uint32_t pin,
uint8_t func)
static int pinmux_pullup(struct device *dev, u32_t pin,
u8_t func)
{
ARG_UNUSED(dev);
return qm_pmux_pullup_en(pin, func) == 0 ? 0 : -EIO;
}
static int pinmux_input(struct device *dev, uint32_t pin,
uint8_t func)
static int pinmux_input(struct device *dev, u32_t pin,
u8_t func)
{
ARG_UNUSED(dev);

10
drivers/pinmux/pinmux_quark_mcu.h
View file

@ -20,7 +20,7 @@
* Each pinmux register rperesents a bank of 16 pins, 2 bits per pin for a total
* of four possible settings per pin.
*
* The first argument to the macro is name of the uint32_t's that is being used
* The first argument to the macro is name of the u32_t's that is being used
* to contain the bit patterns for all the configuration registers. The pin
* number divided by 16 selects the correct register bank based on the pin
* number.
@ -34,23 +34,23 @@
#define PIN_CONFIG(A, _pin, _func) \
(A[((_pin) / 16)] |= ((0x3 & (_func)) << (((_pin) % 16) * 2)))
static inline int _quark_mcu_set_mux(uint32_t base, uint32_t pin, uint8_t func)
static inline int _quark_mcu_set_mux(u32_t base, u32_t pin, u8_t func)
{
/*
* the registers are 32-bit wide, but each pin requires 1 bit
* to set the input enable bit.
*/
uint32_t register_offset = (pin / 32) * 4;
u32_t register_offset = (pin / 32) * 4;
/*
* Now figure out what is the full address for the register
* we are looking for. Add the base register to the register_mask
*/
volatile uint32_t *mux_register = (uint32_t *)(base + register_offset);
volatile u32_t *mux_register = (u32_t *)(base + register_offset);
/*
* Finally grab the pin offset within the register
*/
uint32_t pin_offset = pin % 32;
u32_t pin_offset = pin % 32;
/*
* MAGIC NUMBER: 0x1 is used as the pullup is a single bit in a

14
drivers/pinmux/stm32/pinmux_stm32.c
View file

@ -24,7 +24,7 @@
#include "pinmux.h"
#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE)
static const uint32_t ports_enable[STM32_PORTS_MAX] = {
static const u32_t ports_enable[STM32_PORTS_MAX] = {
STM32_PERIPH_GPIOA,
STM32_PERIPH_GPIOB,
STM32_PERIPH_GPIOC,
@ -43,7 +43,7 @@ static const uint32_t ports_enable[STM32_PORTS_MAX] = {
#endif
};
#elif defined(CONFIG_SOC_SERIES_STM32F4X)
static const uint32_t ports_enable[STM32_PORTS_MAX] = {
static const u32_t ports_enable[STM32_PORTS_MAX] = {
STM32F4X_CLOCK_ENABLE_GPIOA,
STM32F4X_CLOCK_ENABLE_GPIOB,
STM32F4X_CLOCK_ENABLE_GPIOC,
@ -63,7 +63,7 @@ static const uint32_t ports_enable[STM32_PORTS_MAX] = {
*
* @return 0 on success, error otherwise
*/
static int enable_port(uint32_t port, struct device *clk)
static int enable_port(u32_t port, struct device *clk)
{
/* enable port clock */
if (!clk) {
@ -97,13 +97,13 @@ static int enable_port(uint32_t port, struct device *clk)
static int stm32_pin_configure(int pin, int func, int altf)
{
/* determine IO port registers location */
uint32_t offset = STM32_PORT(pin) * GPIO_REG_SIZE;
uint8_t *port_base = (uint8_t *)(GPIO_PORTS_BASE + offset);
u32_t offset = STM32_PORT(pin) * GPIO_REG_SIZE;
u8_t *port_base = (u8_t *)(GPIO_PORTS_BASE + offset);
/* not much here, on STM32F10x the alternate function is
* controller by setting up GPIO pins in specific mode.
*/
return stm32_gpio_configure((uint32_t *)port_base,
return stm32_gpio_configure((u32_t *)port_base,
STM32_PIN(pin), func, altf);
}
@ -116,7 +116,7 @@ static int stm32_pin_configure(int pin, int func, int altf)
*
* @return 0 on success, error otherwise
*/
int _pinmux_stm32_set(uint32_t pin, uint32_t func,
int _pinmux_stm32_set(u32_t pin, u32_t func,
struct device *clk)
{
int config;

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