uart: ns16550: support Apollo Lake PRV_CLOCK_PARAMS (PCP) register
The UARTs on the Apollo Lake SoCs have PLLs that feed the baud rate generators. This patch allows a user to specify custom M/N values for those PLLs when custom/high-speed baud rates are required. I'm not entirely satisfied with the way the PCP values are configured, because it requires tweaking data in both Kconfig and DeviceTree. For the time being I've merely taken my cue from another similar feature (the DLF register support) and have punted on figuring out the "right way" to expose UART configuration to the application. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse
Andrew Boie
parent
b5578d8de3
commit
5dd1bf15fc
2 changed files with 111 additions and 12 deletions
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@ -25,6 +25,16 @@ config UART_NS16550_DLF
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Says n if you are not sure if hardware supports this.
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config UART_NS16550_PCP
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bool "Enable Apollo Lake PRV_CLOCK_PARAMS (PCP) support"
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depends on SOC_APOLLO_LAKE && UART_NS16550
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help
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This enables configuration of the clock blocks that feed
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the UARTs on Apollo Lake SoCs, allowing the generation of
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custom baud rates.
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Say n unless you know you need this feature.
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config UART_NS16550_LINE_CTRL
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bool "Enable Serial Line Control for Apps"
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depends on UART_LINE_CTRL && UART_NS16550
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@ -99,6 +109,16 @@ config UART_NS16550_PORT_0_DLF
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help
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Value for DLF register.
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config UART_NS16550_PORT_0_PCP
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hex "Port 0 PCP value"
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default 0
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depends on UART_NS16550_PORT_0 && UART_NS16550_PCP
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help
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Value for PRV_CLOCK_PARAMS register. If left at its default
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value (0), then the kernel will not attempt to set the PCP
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for this UART; otherwise be sure the device tree for this
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port has sys_clk_freq set accordingly.
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config UART_NS16550_PORT_0_PCI
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bool "Port 0 is PCI-based"
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depends on UART_NS16550_PCI && UART_NS16550_PORT_0
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@ -156,6 +176,16 @@ config UART_NS16550_PORT_1_DLF
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help
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Value for DLF register.
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config UART_NS16550_PORT_1_PCP
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hex "Port 1 PCP value"
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default 0
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depends on UART_NS16550_PORT_1 && UART_NS16550_PCP
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help
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Value for PRV_CLOCK_PARAMS register. If left at its default
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value (0), then the kernel will not attempt to set the PCP
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for this UART; otherwise be sure the device tree for this
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port has sys_clk_freq set accordingly.
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config UART_NS16550_PORT_1_PCI
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bool "Port 1 is PCI-based"
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depends on UART_NS16550_PCI && UART_NS16550_PORT_1
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@ -186,6 +216,16 @@ config UART_NS16550_PORT_2_DLF
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help
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Value for DLF register.
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config UART_NS16550_PORT_2_PCP
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hex "Port 2 PCP value"
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default 0
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depends on UART_NS16550_PORT_2 && UART_NS16550_PCP
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help
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Value for PRV_CLOCK_PARAMS register. If left at its default
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value (0), then the kernel will not attempt to set the PCP
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for this UART; otherwise be sure the device tree for this
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port has sys_clk_freq set accordingly.
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config UART_NS16550_PORT_2_PCI
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bool "Port 2 is PCI-based"
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depends on UART_NS16550_PCI && UART_NS16550_PORT_2
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@ -215,6 +255,16 @@ config UART_NS16550_PORT_3_DLF
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help
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Value for DLF register.
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config UART_NS16550_PORT_3_PCP
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hex "Port 3 PCP value"
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default 0
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depends on UART_NS16550_PORT_3 && UART_NS16550_PCP
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help
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Value for PRV_CLOCK_PARAMS register. If left at its default
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value (0), then the kernel will not attempt to set the PCP
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for this UART; otherwise be sure the device tree for this
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port has sys_clk_freq set accordingly.
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config UART_NS16550_PORT_3_PCI
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bool "Port 3 is PCI-based"
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depends on UART_NS16550_PCI && UART_NS16550_PORT_3
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@ -42,18 +42,19 @@
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/* register definitions */
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#define REG_THR 0x00 /* Transmitter holding reg. */
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#define REG_RDR 0x00 /* Receiver data reg. */
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#define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define REG_IER 0x01 /* Interrupt enable reg. */
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#define REG_IIR 0x02 /* Interrupt ID reg. */
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#define REG_FCR 0x02 /* FIFO control reg. */
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#define REG_LCR 0x03 /* Line control reg. */
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#define REG_MDC 0x04 /* Modem control reg. */
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#define REG_LSR 0x05 /* Line status reg. */
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#define REG_MSR 0x06 /* Modem status reg. */
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#define REG_DLF 0xC0 /* Divisor Latch Fraction */
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#define REG_THR 0x00 /* Transmitter holding reg. */
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#define REG_RDR 0x00 /* Receiver data reg. */
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#define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define REG_IER 0x01 /* Interrupt enable reg. */
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#define REG_IIR 0x02 /* Interrupt ID reg. */
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#define REG_FCR 0x02 /* FIFO control reg. */
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#define REG_LCR 0x03 /* Line control reg. */
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#define REG_MDC 0x04 /* Modem control reg. */
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#define REG_LSR 0x05 /* Line status reg. */
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#define REG_MSR 0x06 /* Modem status reg. */
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#define REG_DLF 0xC0 /* Divisor Latch Fraction */
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#define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
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/* equates for interrupt enable register */
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@ -78,6 +79,11 @@
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#define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
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#define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
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/* equates for Apollo Lake clock control register (PRV_CLOCK_PARAMS) */
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#define PCP_UPDATE 0x80000000 /* update clock */
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#define PCP_EN 0x00000001 /* enable clock output */
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/*
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* Per PC16550D (Literature Number: SNLS378B):
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*
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@ -187,6 +193,7 @@
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#define LSR(dev) (DEV_DATA(dev)->port + REG_LSR * UART_REG_ADDR_INTERVAL)
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#define MSR(dev) (DEV_DATA(dev)->port + REG_MSR * UART_REG_ADDR_INTERVAL)
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#define DLF(dev) (DEV_DATA(dev)->port + REG_DLF)
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#define PCP(dev) (DEV_DATA(dev)->port + REG_PCP)
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#define IIRC(dev) (DEV_DATA(dev)->iir_cache)
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@ -196,13 +203,17 @@
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#ifdef UART_NS16550_ACCESS_IOPORT
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#define INBYTE(x) sys_in8(x)
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#define INWORD(x) sys_in32(x)
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#define OUTBYTE(x, d) sys_out8(d, x)
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#define OUTWORD(x, d) sys_out32(d, x)
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#ifndef UART_REG_ADDR_INTERVAL
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#define UART_REG_ADDR_INTERVAL 1 /* address diff of adjacent regs. */
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#endif /* UART_REG_ADDR_INTERVAL */
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#else
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#define INBYTE(x) sys_read8(x)
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#define INWORD(x) sys_read32(x)
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#define OUTBYTE(x, d) sys_write8(d, x)
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#define OUTWORD(x, d) sys_write32(d, x)
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#ifndef UART_REG_ADDR_INTERVAL
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#define UART_REG_ADDR_INTERVAL 4 /* address diff of adjacent regs. */
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#endif
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@ -215,6 +226,10 @@ struct uart_ns16550_device_config {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif
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#ifdef CONFIG_UART_NS16550_PCP
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u32_t pcp;
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#endif
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};
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/** Device data structure */
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@ -250,6 +265,20 @@ static inline void set_dlf(struct device *dev, u32_t val)
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}
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#endif
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#ifdef CONFIG_UART_NS16550_PCP
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static inline void set_pcp(struct device *dev)
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{
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const struct uart_ns16550_device_config * const dev_cfg = DEV_CFG(dev);
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u32_t pcp = dev_cfg->pcp;
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if (pcp) {
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pcp |= PCP_EN;
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OUTWORD(PCP(dev), pcp & ~PCP_UPDATE);
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OUTWORD(PCP(dev), pcp | PCP_UPDATE);
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}
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}
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#endif
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static void set_baud_rate(struct device *dev, u32_t baud_rate)
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{
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const struct uart_ns16550_device_config * const dev_cfg = DEV_CFG(dev);
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@ -339,6 +368,10 @@ static int uart_ns16550_init(struct device *dev)
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set_dlf(dev, dev_data->dlf);
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#endif
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#ifdef CONFIG_UART_NS16550_PCP
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set_pcp(dev);
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#endif
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set_baud_rate(dev, dev_data->baud_rate);
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/* 8 data bits, 1 stop bit, no parity, clear DLAB */
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@ -765,6 +798,10 @@ static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_0 = {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = irq_config_func_0,
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_0_PCP
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.pcp = CONFIG_UART_NS16550_PORT_0_PCP
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#endif
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};
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static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_0 = {
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@ -819,6 +856,10 @@ static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_1 = {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = irq_config_func_1,
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_1_PCP
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.pcp = CONFIG_UART_NS16550_PORT_1_PCP
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#endif
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};
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static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_1 = {
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@ -873,6 +914,10 @@ static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_2 = {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = irq_config_func_2,
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_2_PCP
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.pcp = CONFIG_UART_NS16550_PORT_2_PCP
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#endif
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};
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static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_2 = {
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@ -927,6 +972,10 @@ static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_3 = {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = irq_config_func_3,
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_3_PCP
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.pcp = CONFIG_UART_NS16550_PORT_3_PCP
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#endif
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};
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static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_3 = {
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