Commit graph

250 commits

Author SHA1 Message Date
Mulin Chao
b3188f1c32 drivers: npcx: replace type of register base address with uintptr_t
Replace npcx register base address type, uint32_t, with uintptr_t.
It is easier to know what type of base address and for linear
addresses treated as integral values.

This CL also modified IS_BIT_SET() macro function to fit MISRA code
guidelines.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-01 13:35:25 +02:00
Mulin Chao
1eca7ab46a drivers: npcx: remove suffix '_t' of device register structure.
Remove the '_t' suffix of device register structure since it is used
mainly with typedefs.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-09-01 13:35:25 +02:00
Krzysztof Chruscinski
17d7ad482a drivers: clock_control: Rename nrf_power_clock to clock_control_nrf
Renamed nrf clock control driver file since it does no long control
POWER peripheral.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-08-31 12:40:47 +02:00
Krzysztof Chruscinski
701e9befe4 drivers: clock_control: nrf: Move USB part to the USB driver
Removed all nrf_power/USB related stuff from clock control
driver to USB driver.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-08-31 12:40:47 +02:00
Krzysztof Chruscinski
d8da2e59c8 drivers: clock_control: nrf: Make use of related nrfx drivers
Update the driver implementation to use nrfx_clock and nrfx_power
drivers. Update also revisions of the hal_nordic and nrf_hw_models
modules, so that it is actually possible to use those drivers.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-08-31 12:40:47 +02:00
Manivannan Sadhasivam
1118428abb drivers: clock_control: Add support for MCUX CCM IUART clock
Add support for controlling the MCUX CCM IUART clock.

Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
2020-08-14 14:51:50 -05:00
Mulin Chao
0245a27bc5 driver: clock: Add clock controller support in NPCX series.
Add clock controller support for Nuvoton NPCX series. This CL includes:

1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
2020-08-13 16:42:20 +02:00
Tomasz Bursztyka
98d9b01322 device: Apply driver_api/data attributes rename everywhere
Via coccinelle:

@r_device_driver_api_and_data_1@
struct device *D;
@@
(
D->
-	driver_api
+	api
|
D->
-	driver_data
+	data
)

@r_device_driver_api_and_data_2@
expression E;
@@
(
net_if_get_device(E)->
-	driver_api
+	api
|
net_if_get_device(E)->
-	driver_data
+	data
)

And grep/sed rules for macros:

git grep -rlz 'dev)->driver_data' |
	xargs -0 sed -i 's/dev)->driver_data/dev)->data/g'

git grep -rlz 'dev->driver_data' |
	xargs -0 sed -i 's/dev->driver_data/dev->data/g'

git grep -rlz 'device->driver_data' |
	xargs -0 sed -i 's/device->driver_data/device->data/g'

Fixes #27397

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-08-11 19:30:53 +02:00
Tomasz Bursztyka
af6140cc0d device: Apply config_info rename everywhere
Via coccinelle:

@r_device_config@
struct device *D;
@@

D->
-	config_info
+	config

And 2 grep/sed rules for macros:

git grep -rlz 'dev)->config_info' |
	xargs -0 sed -i 's/dev)->config_info/dev)->config/g'

git grep -rlz 'dev->config_info' |
	xargs -0 sed -i 's/dev->config_info/dev->config/g'

Fixes #27397

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-08-11 19:30:53 +02:00
Jeremy LOCHE
0fe6707199 drivers: clock_control: stm32h7 add HSI divisor support
Add HSI divisor support for clock tree configuration.
Removed HSI calibration trimming to comply with
common STM32 implementation and use reset default
configuration instead.

Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-08-05 16:22:53 +02:00
Jeremy LOCHE
ea6580cdcd drivers: clock_control: stm32h7 change set flash latency
Updated flash latency setting to comply with
common stm32 implementation and datasheet.

Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-08-05 16:22:53 +02:00
Jeremy LOCHE
f3bdf8ae91 drivers: clock_control: stm32h7 add preprocessor clock check
Adds preprocessor clock feasibility check to avoid setting
too high clocks to SYSCLK,AHB,APBx buses.

Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
matches with the desired clock configuration by
the M7 core.

Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-08-05 16:22:53 +02:00
Jeremy LOCHE
63611264c4 drivers: clock_control: stm32h7 fixed inverted assertion
Fixed wrong usage of assertions.
Assertions should check that the value is in range and
not out of range.

Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-08-05 16:22:53 +02:00
Jeremy LOCHE
a686576348 drivers: clock_control: stm32h7 fix high frequency setting
Fixes #27212 by setting the AHB/APBx dividers
prior to configuring the PLL as clock source.

Prevents going over the limits of APBx clocks when
choosing the PLL as system clock source for
high frequencies (close to 480MHz)

Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-08-05 16:22:53 +02:00
Maxime Bittan
ed4511ea8c drivers: clock_control: lpc11u6x: Add support for clock controller
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.

Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
2020-07-29 20:12:24 +02:00
Jeremy LOCHE
33abbbfd85 drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt.
Add HSE,HSI,CSI,PLL as system clock options.
Also add correct configuration of the PLL.

New sysclk options:
- HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y
- HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y
- CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y
Existing sysclk options:
- PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

PLL clock options:
- More PLL source clocks:
Existing:
	1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
New:
	2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
	3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y
- PLL vco input range is auto-calculated based on PLL DIVM1

-> Example for sysclock 96MHz generated with PLL from HSI
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2

Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h
instead to setup the correct latency.

Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-27 13:24:27 +02:00
Krzysztof Chruscinski
04e770b20c drivers: clock_control: nrf: Add clock status shell command
Added shell command to clock driver to get clock status.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-07-20 16:22:21 +02:00
Krzysztof Chruscinski
6f01c0bc79 drivers: clock_control: nrf: Add onoff service support
Updated nrf clock control driver to use onoff service for managing
multiple users.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-07-20 16:22:21 +02:00
Alexandre Bourdiol
c8ceca2d53 drivers: STM32 dualcore concurrent register access protection with HSEM
In case of dualcore, STM32H7, STM32W and STM32MP1,
protect concurrent register write access with HSEM.
Done for following drivers:
clock_control, counter, flash, gpio, interrupt_controller

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-07-09 11:27:56 +02:00
Ilya Tagunov
301208329b drivers: clock_control: stm32f0/f3: streamline PREDIV handling
We should not set PLLSRC bits here. It is done by
LL_PLL_ConfigSystemClock_* functions which are called later.
Also, PREDIV1 setting should not be restricted to HSE only.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2020-07-05 07:56:21 -04:00
Ilya Tagunov
907c545837 drivers: clock_control: stm32f0/f3: fix PREDIV options
Allow CLOCK_STM32_PLL_PREDIV1 option for STM32F3 series;
correct and extend option descriptions.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2020-07-05 07:56:21 -04:00
Erwan Gouriou
6b72fbae7c drivers/clock_control: Remove useless CLOCK_STM32_PLL_XTPRE config
CLOCK_STM32_PLL_XTPRE Kconfig symbols was made to differentiate
code between F1 soc variants with XTRE and others.
It appears that specific XTRE code handling is already in place in
LL_PLL_ConfigSystemClock_* functions that are called afterwards.
Since this piece of code is not required anymore, let's remove
the symbol.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-07-02 08:14:45 -05:00
Giancarlo Stasi
82a08a7678 drivers: clock: stm32: fix Flash latency & clock settings for MSI & HSE
According to RM, when increasing the CPU frequency, the new number of
wait states to the Flash latency bits must be written and verified
before modifying the CPU clock source and/or the CPU clock prescaler,
to prevent NMI to occur; when decreasing the CPU frequency, after.
Tested with STM32L462 SOC and MSI with several frequencies, both
increasing and decreasing. HSE built, not tested.

Signed-off-by: Giancarlo Stasi <giancarlo.stasi@nexxiot.com>
2020-06-23 17:32:38 +02:00
Krzysztof Chruscinski
b8781e27b0 sys: util: Deprecate GET_ARGS_LESS_1 macro
GET_ARGS_LESS_N must be used instead.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-06-22 15:18:07 +02:00
Krzysztof Chruscinski
0afb3445a5 sys: util: Deprecate GET_ARG1 macro
GET_ARG_N(1,...) can be used instead.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-06-22 15:18:07 +02:00
Mohamed ElShahawi
4acac3e9ef drivers: esp32/clock_control: Add Clock Driver
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).

- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node

Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
2020-06-16 09:00:51 -05:00
Hake Huang
6bb555ce83 clock_control: add EDMA clock support
add clock rate for RT series from ipg
Kinetis does not need additional clock added

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-06-12 13:03:28 -05:00
Andreas Sandberg
f1d80b3f02 drivers: clock_control: stm32: Enable SYSCFG on STM32L0
The entropy driver needs to use the SYSCFG block to control VREF on
the STM32L0. Clock the block if the entropy driver has been enabled.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
2020-06-09 14:44:25 +02:00
Kumar Gala
a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Krzysztof Chruscinski
dc9d373eab drivers: clock_control: nrf: Allow calibration disabling
Allow to disable calibration even though RC is used.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-06-04 11:20:01 +02:00
Krzysztof Chruscinski
d8560f698b drivers: clock_control: nrf: Fix error during initialization
Prevent usage of system work queue before it is ready by delaying
initialization of temperature device. Work queue is not used until
application stage.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-05-27 14:49:54 +02:00
Andrzej Głąbek
f766a3e18b sensor: temp_nrf5: Allow use only when the TEMP peripheral is present
Correct dependency of the TEMP_NRF5 Kconfig option so that it can be
enabled only on nRF SoCs that feature the TEMP peripheral.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-05-25 16:03:02 +02:00
Martí Bolívar
6e8775ff84 devicetree: remove DT_HAS_NODE_STATUS_OKAY
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:

- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
  for macros which are equivalent to
  DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name

Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.

This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-13 18:24:42 +02:00
Martí Bolívar
7e0eed9235 devicetree: allow access to all nodes
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.

Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.

To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:

- emit macros for all existing nodes in gen_defines.py, regardless
  of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-08 19:37:18 -05:00
Tomasz Bursztyka
97326c0445 device: Fix structure attributes access
Since struct devconfig was merged earlier into struct device, let's fix
accessing config_info, name, ... attributes everywhere via:

grep -rlZ 'dev->config->' | xargs -0 sed -i 's/dev->config->/dev->/g'

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-05-08 23:07:44 +02:00
Erwan Gouriou
c4d9de1850 drivers/clock_control: stm32: msi: Enable MSI range config in PLL mode
When MSI clock is used a source of PLL, it should be possible to
select its frequency range. Fix this.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
f258199595 drivers/clock_control: Add clock_control on STM32L5 series
Add clock_control driver for STM32L5.
It's based on L4/WB driver since it is similar IP.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Kumar Gala
0a7d4e2135 devicetree: Change DT_FOREACH_IMPL_ to not insert semicolon
Remove semicolon between instance invocations of DT_FOREACH_IMPL_ and
thus DT_INST_FOREACH.  This provides more flexibility to the user.  This
requires we fixup in tree users to add semicolon where needed.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 20:03:56 -05:00
Martí Bolívar
87e1743ae0 devicetree: replace DT_HAS_DRV_INST with DT_INST_FOREACH
Make drivers multi-instance wherever possible using DT_INST_FOREACH.
This allows removing DT_HAS_DRV_INST in favor of making drivers just
do the right thing regardless of how many instances there are.

There are a few exceptions:

- SoC drivers which use CMake input files (like i2c_dw.c) or otherwise
  would require more time to convert than I have at the moment. For the
  sake of expediency, just inline the DT_HAS_DRV_INST expansion for
  now in these cases.

- SoC drivers which are explicitly single-instance (like the nRF SAADC
  driver). Again for the sake of expediency, drop a BUILD_ASSERT in
  those cases to make sure the assumption that all supported SoCs have
  at most one available instance is valid, failing fast otherwise.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-06 17:35:08 -05:00
Kumar Gala
fdd85d5ad7 dts: Rename DT_HAS_NODE macro to DT_HAS_NODE_STATUS_OKAY
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear.  As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-06 05:25:41 -05:00
Alexandre Bourdiol
0c8c6d2bb2 drivers/clock_control: stm32H7 AHB clock computation depends on core
On cortex M4, AHB clock is equal to SystemCoreClock
On Cortex M7, AHB clock is equal to SystemCoreClock/HPRE
By the way, D1CPRE is of no use when starting from SystemCoreColck.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-04-29 15:18:18 -05:00
Martí Bolívar
b9fff2cee0 clock_control: nordic: move to new DT API
Use the new devicetree API to access dts data.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-04-14 06:32:25 -05:00
Kumar Gala
ff1eb62864 drivers: arm_cmsdk/arm: Convert drivers to new DT_INST macros
Convert older DT_INST_ macro use in arm_cmsdk/arm drivers to the new
include/devicetree.h DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-31 19:28:47 -05:00
Andy Ross
32bb2395c2 timeout: Fix up API usage
Kernel timeouts have always been a 32 bit integer despite the
existence of generation macros, and existing code has been
inconsistent about using them.  Upcoming commits are going to make the
timeout arguments opaque, so fix things up to be rigorously correct.
Changes include:

+ Adding a K_TIMEOUT_EQ() macro for code that needs to compare timeout
  values for equality (e.g. with K_FOREVER or K_NO_WAIT).

+ Adding a k_msleep() synonym for k_sleep() which can continue to take
  integral arguments as k_sleep() moves away to timeout arguments.

+ Pervasively using the K_MSEC(), K_SECONDS(), et. al. macros to
  generate timeout arguments.

+ Removing the usage of K_NO_WAIT as the final argument to
  K_THREAD_DEFINE().  This is just a count of milliseconds and we need
  to use a zero.

This patch include no logic changes and should not affect generated
code at all.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-03-31 19:40:47 -04:00
Tomasz Bursztyka
697b63ea0f drivers/clock_gate: Support on/off operationf in mcux's SIM driver
Logic to enable/disable the relevant clock was fully missing.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-03-27 14:48:30 +02:00
Kumar Gala
63ccb98eee drivers: openisa: Convert openisa drivers to new DT_INST macros
Convert older DT_INST_ macro use in openisa drivers to the new
include/devicetree.h DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-27 05:28:37 -05:00
Kumar Gala
4b9fe8a24e drivers: mcux: Convert MCUX drivers to new DT_INST macros
Convert older DT_INST_ macro use in MCUX drivers to the new
include/devicetree.h DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 03:40:09 -05:00
Krzysztof Chruscinski
a36a478954 drivers: clock_control: nrf: Reworked calibration to use k_timer
Reworked calibration to not use HW platform which is not available on
some platforms (nrf53) and does not bring any value compared to using
system timer. Switched to use k_timer. Additionally, improved
calibration algorithm to request also LF clock before starting
calibration. This simplifies the algorithm because it does not need
to support disabling low frequency clock which in calibration.

Tests has been updated and simplified. Former tests relied on HW timer
event.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-03-19 15:15:23 +01:00
Kumar Gala
0241ad8482 drivers: clock_control: beetle: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-12 04:53:30 -06:00
Kumar Gala
c998b12652 drivers: clock_control: rv32m1_pcc: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00