drivers/clock_control: Remove useless CLOCK_STM32_PLL_XTPRE config
CLOCK_STM32_PLL_XTPRE Kconfig symbols was made to differentiate code between F1 soc variants with XTRE and others. It appears that specific XTRE code handling is already in place in LL_PLL_ConfigSystemClock_* functions that are called afterwards. Since this piece of code is not required anymore, let's remove the symbol. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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6 changed files with 1 additions and 36 deletions
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@ -28,7 +28,6 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# the 8MHz clock signal coming from integrated STLink
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CONFIG_CLOCK_STM32_HSE_BYPASS=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_XTPRE=n
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# APB1 clock must not to exceed 36MHz limit
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@ -29,7 +29,6 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_XTPRE=n
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# APB1 clock must not to exceed 36MHz limit
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@ -35,7 +35,6 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_XTPRE=n
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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@ -30,7 +30,6 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_XTPRE=n
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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@ -5,12 +5,6 @@
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if SOC_SERIES_STM32F1X
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config CLOCK_STM32_PLL_XTPRE
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bool "HSE to PLL /2 prescaler"
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depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
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help
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Enable this option to enable /2 prescaler on HSE to PLL clock signal
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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@ -24,7 +18,7 @@ config CLOCK_STM32_PLL_MULTIPLIER
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config CLOCK_STM32_PLL_PREDIV1
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int "PREDIV1 Prescaler"
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depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 16
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help
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@ -33,40 +33,16 @@
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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/*
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* PLLMUL on SOC_STM32F10X_DENSITY_DEVICE
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*
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* PLLMUL on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 9 -> LL_RCC_PLL_MUL_9 -> 0x001C0000
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* 13 -> LL_RCC_PLL_MUL_6_5 -> 0x00340000
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*/
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pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
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<< RCC_CFGR_PLLMULL_Pos);
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#ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
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/* PLL prediv */
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#ifdef CONFIG_CLOCK_STM32_PLL_XTPRE
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/*
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* SOC_STM32F10X_DENSITY_DEVICE:
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* PLLXPTRE (depends on PLL source HSE)
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* HSE/2 used as PLL source
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*/
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pllinit->Prediv = LL_RCC_PREDIV_DIV_2;
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#else
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/*
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* SOC_STM32F10X_DENSITY_DEVICE:
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* PLLXPTRE (depends on PLL source HSE)
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* HSE used as direct PLL source
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*/
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pllinit->Prediv = LL_RCC_PREDIV_DIV_1;
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#endif /* CONFIG_CLOCK_STM32_PLL_XTPRE */
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#else
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/*
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* SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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@ -76,7 +52,6 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1;
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#endif /* CONFIG_SOC_STM32F10X_DENSITY_DEVICE */
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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