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drivers/clock_control: Remove useless CLOCK_STM32_PLL_XTPRE config

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CLOCK_STM32_PLL_XTPRE Kconfig symbols was made to differentiate
code between F1 soc variants with XTRE and others.
It appears that specific XTRE code handling is already in place in
LL_PLL_ConfigSystemClock_* functions that are called afterwards.
Since this piece of code is not required anymore, let's remove
the symbol.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-06-26 10:10:28 +02:00 • committed by Maureen Helm
commit 6b72fbae7c
6 changed files with 1 additions and 36 deletions
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1
boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig
View file

@ -28,7 +28,6 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# the 8MHz clock signal coming from integrated STLink
CONFIG_CLOCK_STM32_HSE_BYPASS=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_XTPRE=n
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not to exceed 36MHz limit

1
boards/arm/olimexino_stm32/olimexino_stm32_defconfig
View file

@ -29,7 +29,6 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_XTPRE=n
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not to exceed 36MHz limit

1
boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig
View file

@ -35,7 +35,6 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_XTPRE=n
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1

1
boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig
View file

@ -30,7 +30,6 @@ CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_XTPRE=n
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1

8
drivers/clock_control/Kconfig.stm32f1
View file

@ -5,12 +5,6 @@
if SOC_SERIES_STM32F1X
config CLOCK_STM32_PLL_XTPRE
bool "HSE to PLL /2 prescaler"
depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
help
Enable this option to enable /2 prescaler on HSE to PLL clock signal
config CLOCK_STM32_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
@ -24,7 +18,7 @@ config CLOCK_STM32_PLL_MULTIPLIER
config CLOCK_STM32_PLL_PREDIV1
int "PREDIV1 Prescaler"
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 1
range 1 16
help

25
drivers/clock_control/clock_stm32f1.c
View file

@ -33,40 +33,16 @@
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
{
/*
* PLLMUL on SOC_STM32F10X_DENSITY_DEVICE
* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
* ...
* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
*
* PLLMUL on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
* ...
* 9 -> LL_RCC_PLL_MUL_9 -> 0x001C0000
* 13 -> LL_RCC_PLL_MUL_6_5 -> 0x00340000
*/
pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
<< RCC_CFGR_PLLMULL_Pos);
#ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
/* PLL prediv */
#ifdef CONFIG_CLOCK_STM32_PLL_XTPRE
/*
* SOC_STM32F10X_DENSITY_DEVICE:
* PLLXPTRE (depends on PLL source HSE)
* HSE/2 used as PLL source
*/
pllinit->Prediv = LL_RCC_PREDIV_DIV_2;
#else
/*
* SOC_STM32F10X_DENSITY_DEVICE:
* PLLXPTRE (depends on PLL source HSE)
* HSE used as direct PLL source
*/
pllinit->Prediv = LL_RCC_PREDIV_DIV_1;
#endif /* CONFIG_CLOCK_STM32_PLL_XTPRE */
#else
/*
* SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
@ -76,7 +52,6 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
*/
pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1;
#endif /* CONFIG_SOC_STM32F10X_DENSITY_DEVICE */
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */