drivers: openisa: Convert openisa drivers to new DT_INST macros
Convert older DT_INST_ macro use in openisa drivers to the new include/devicetree.h DT_INST macro APIs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
15d3c3bb40
commit
63ccb98eee
4 changed files with 34 additions and 26 deletions
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@ -3,6 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT openisa_rv32m1_pcc
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#include <errno.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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@ -58,24 +60,24 @@ static const struct clock_control_driver_api rv32m1_pcc_api = {
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.get_rate = rv32m1_pcc_get_rate,
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};
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#if defined(DT_INST_0_OPENISA_RV32M1_PCC)
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#if DT_HAS_DRV_INST(0)
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static struct rv32m1_pcc_config rv32m1_pcc0_config = {
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.base_address = DT_INST_0_OPENISA_RV32M1_PCC_BASE_ADDRESS
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.base_address = DT_INST_REG_ADDR(0)
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};
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DEVICE_AND_API_INIT(rv32m1_pcc0, DT_INST_0_OPENISA_RV32M1_PCC_LABEL,
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DEVICE_AND_API_INIT(rv32m1_pcc0, DT_INST_LABEL(0),
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&rv32m1_pcc_init,
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NULL, &rv32m1_pcc0_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
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&rv32m1_pcc_api);
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#endif
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#if defined(DT_INST_1_OPENISA_RV32M1_PCC)
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#if DT_HAS_DRV_INST(1)
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static struct rv32m1_pcc_config rv32m1_pcc1_config = {
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.base_address = DT_INST_1_OPENISA_RV32M1_PCC_BASE_ADDRESS
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.base_address = DT_INST_REG_ADDR(1)
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};
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DEVICE_AND_API_INIT(rv32m1_pcc1, DT_INST_1_OPENISA_RV32M1_PCC_LABEL,
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DEVICE_AND_API_INIT(rv32m1_pcc1, DT_INST_LABEL(1),
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&rv32m1_pcc_init,
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NULL, &rv32m1_pcc1_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT soc_nv_flash
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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@ -116,8 +118,8 @@ static int flash_mcux_write_protection(struct device *dev, bool enable)
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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static const struct flash_pages_layout dev_layout = {
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.pages_count = KB(CONFIG_FLASH_SIZE) /
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DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
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.pages_size = DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
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DT_INST_PROP(0, erase_block_size),
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.pages_size = DT_INST_PROP(0, erase_block_size),
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};
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static void flash_mcux_pages_layout(
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@ -6,6 +6,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT openisa_rv32m1_gpio
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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@ -321,7 +323,7 @@ static int gpio_rv32m1_porta_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_porta_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_0_OPENISA_RV32M1_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(0, ngpios)),
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},
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_A_BASE_ADDRESS,
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.port_base = PORTA,
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@ -369,7 +371,7 @@ static int gpio_rv32m1_portb_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_portb_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_1_OPENISA_RV32M1_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(1, ngpios)),
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},
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_B_BASE_ADDRESS,
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.port_base = PORTB,
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@ -417,7 +419,7 @@ static int gpio_rv32m1_portc_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_portc_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_2_OPENISA_RV32M1_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(2, ngpios)),
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},
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_C_BASE_ADDRESS,
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.port_base = PORTC,
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@ -466,7 +468,7 @@ static int gpio_rv32m1_portd_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_portd_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_3_OPENISA_RV32M1_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(3, ngpios)),
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},
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_D_BASE_ADDRESS,
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.port_base = PORTD,
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@ -514,7 +516,7 @@ static int gpio_rv32m1_porte_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_porte_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_4_OPENISA_RV32M1_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(4, ngpios)),
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},
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_E_BASE_ADDRESS,
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.port_base = PORTE,
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@ -7,6 +7,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT openisa_rv32m1_tpm
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#include <drivers/clock_control.h>
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#include <errno.h>
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#include <drivers/pwm.h>
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@ -179,37 +181,37 @@ static const struct pwm_driver_api rv32m1_tpm_driver_api = {
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#define TPM_DEVICE(n) \
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static const struct rv32m1_tpm_config rv32m1_tpm_config_##n = { \
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.base = (TPM_Type *) \
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DT_INST_##n##_OPENISA_RV32M1_TPM_BASE_ADDRESS, \
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DT_INST_REG_ADDR(n), \
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.clock_name = \
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DT_INST_##n##_OPENISA_RV32M1_TPM_CLOCK_CONTROLLER, \
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DT_INST_CLOCKS_LABEL(n), \
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.clock_subsys = (clock_control_subsys_t) \
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DT_INST_##n##_OPENISA_RV32M1_TPM_CLOCK_NAME, \
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DT_INST_CLOCKS_CELL(n, name), \
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.tpm_clock_source = kTPM_SystemClock, \
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.prescale = kTPM_Prescale_Divide_16, \
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.channel_count = FSL_FEATURE_TPM_CHANNEL_COUNTn((TPM_Type *) \
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DT_INST_##n##_OPENISA_RV32M1_TPM_BASE_ADDRESS), \
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DT_INST_REG_ADDR(n)), \
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.mode = kTPM_EdgeAlignedPwm, \
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}; \
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static struct rv32m1_tpm_data rv32m1_tpm_data_##n; \
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DEVICE_AND_API_INIT(rv32m1_tpm_##n, \
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DT_INST_##n##_OPENISA_RV32M1_TPM_LABEL, \
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DT_INST_LABEL(n), \
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&rv32m1_tpm_init, &rv32m1_tpm_data_##n, \
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&rv32m1_tpm_config_##n, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&rv32m1_tpm_driver_api)
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#if DT_INST_0_OPENISA_RV32M1_TPM
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#if DT_HAS_DRV_INST(0)
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TPM_DEVICE(0);
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#endif /* DT_INST_0_OPENISA_RV32M1_TPM */
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#endif /* DT_HAS_DRV_INST(0) */
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#if DT_INST_1_OPENISA_RV32M1_TPM
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#if DT_HAS_DRV_INST(1)
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TPM_DEVICE(1);
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#endif /* DT_INST_1_OPENISA_RV32M1_TPM */
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#endif /* DT_HAS_DRV_INST(1) */
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#if DT_INST_2_OPENISA_RV32M1_TPM
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#if DT_HAS_DRV_INST(2)
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TPM_DEVICE(2);
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#endif /* DT_INST_2_OPENISA_RV32M1_TPM */
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#endif /* DT_HAS_DRV_INST(2) */
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#if DT_INST_3_OPENISA_RV32M1_TPM
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#if DT_HAS_DRV_INST(3)
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TPM_DEVICE(3);
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#endif /* DT_INST_3_OPENISA_RV32M1_TPM */
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#endif /* DT_HAS_DRV_INST(3) */
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