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devicetree: replace DT_HAS_DRV_INST with DT_INST_FOREACH

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Make drivers multi-instance wherever possible using DT_INST_FOREACH.
This allows removing DT_HAS_DRV_INST in favor of making drivers just
do the right thing regardless of how many instances there are.

There are a few exceptions:

- SoC drivers which use CMake input files (like i2c_dw.c) or otherwise
  would require more time to convert than I have at the moment. For the
  sake of expediency, just inline the DT_HAS_DRV_INST expansion for
  now in these cases.

- SoC drivers which are explicitly single-instance (like the nRF SAADC
  driver). Again for the sake of expediency, drop a BUILD_ASSERT in
  those cases to make sure the assumption that all supported SoCs have
  at most one available instance is valid, failing fast otherwise.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit is contained in:
Martí Bolívar 2020-05-05 16:06:32 -07:00 • committed by Kumar Gala
commit 87e1743ae0
46 changed files with 571 additions and 1301 deletions
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25
drivers/adc/adc_nrfx_adc.c
View file

@ -278,9 +278,22 @@ static const struct adc_driver_api adc_nrfx_driver_api = {
.ref_internal = 1200,
};
#if DT_HAS_DRV_INST(0)
DEVICE_AND_API_INIT(adc_0, DT_INST_LABEL(0),
init_adc, NULL, NULL,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&adc_nrfx_driver_api);
#endif
/*
* There is only one instance on supported SoCs, so inst is guaranteed
* to be 0 if any instance is okay. (We use adc_0 above, so the driver
* is relying on the numeric instance value in a way that happens to
* be safe.)
*
* Just in case that assumption becomes invalid in the future, we use
* a BUILD_ASSERT().
*/
#define ADC_INIT(inst) \
BUILD_ASSERT((inst) == 0, \
"multiple instances not supported"); \
DEVICE_AND_API_INIT(adc_0, DT_INST_LABEL(0), \
init_adc, NULL, NULL, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&adc_nrfx_driver_api)
DT_INST_FOREACH(ADC_INIT)

28
drivers/adc/adc_nrfx_saadc.c
View file

@ -418,9 +418,25 @@ static const struct adc_driver_api adc_nrfx_driver_api = {
.ref_internal = 600,
};
#if DT_HAS_DRV_INST(0)
DEVICE_AND_API_INIT(adc_0, DT_INST_LABEL(0),
init_saadc, NULL, NULL,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&adc_nrfx_driver_api);
#endif
/*
* There is only one instance on supported SoCs, so inst is guaranteed
* to be 0 if any instance is okay. (We use adc_0 above, so the driver
* is relying on the numeric instance value in a way that happens to
* be safe.)
*
* Just in case that assumption becomes invalid in the future, we use
* a BUILD_ASSERT().
*/
#define SAADC_INIT(inst) \
BUILD_ASSERT((inst) == 0, \
"multiple instances not supported"); \
DEVICE_AND_API_INIT(adc_0, \
DT_INST_LABEL(0), \
init_saadc, \
NULL, \
NULL, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&adc_nrfx_driver_api)
DT_INST_FOREACH(SAADC_INIT)

78
drivers/adc/adc_shell.c
View file

@ -40,42 +40,31 @@ struct adc_hdl {
u8_t resolution;
};
#define ADC_HDL_LIST_ENTRY(inst) \
{ \
.device_name = DT_INST_LABEL(inst), \
.channel_config = { \
.gain = ADC_GAIN_1, \
.reference = ADC_REF_INTERNAL, \
.acquisition_time = ADC_ACQ_TIME_DEFAULT, \
.channel_id = 0, \
}, \
.resolution = 0, \
}
/*
* TODO generalize with a more flexible for-each macro that doesn't
* assume a semicolon separator.
*/
struct adc_hdl adc_list[] = {
#if DT_HAS_DRV_INST(0)
{
.device_name = DT_INST_LABEL(0),
.channel_config = {
.gain = ADC_GAIN_1,
.reference = ADC_REF_INTERNAL,
.acquisition_time = ADC_ACQ_TIME_DEFAULT,
.channel_id = 0,
},
.resolution = 0,
},
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
ADC_HDL_LIST_ENTRY(0),
#endif
#if DT_HAS_DRV_INST(1)
{
.device_name = DT_INST_LABEL(1),
.channel_config = {
.gain = ADC_GAIN_1,
.reference = ADC_REF_INTERNAL,
.acquisition_time = ADC_ACQ_TIME_DEFAULT,
.channel_id = 0,
},
.resolution = 0,
},
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
ADC_HDL_LIST_ENTRY(1),
#endif
#if DT_HAS_DRV_INST(2)
{
.device_name = DT_INST_LABEL(2),
.channel_config = {
.gain = ADC_GAIN_1,
.reference = ADC_REF_INTERNAL,
.acquisition_time = ADC_ACQ_TIME_DEFAULT,
.channel_id = 0,
},
.resolution = 0,
},
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(2))
ADC_HDL_LIST_ENTRY(2),
#endif
};
@ -475,18 +464,25 @@ SHELL_STATIC_SUBCMD_SET_CREATE(sub_adc_cmds,
SHELL_SUBCMD_SET_END /* Array terminated. */
);
SHELL_STATIC_SUBCMD_SET_CREATE(sub_adc,
#if DT_HAS_DRV_INST(0)
SHELL_CMD(ADC_0, &sub_adc_cmds, "ADC_0", NULL),
#define ADC_SHELL_COMMAND(inst) \
SHELL_CMD(ADC_##inst, &sub_adc_cmds, "ADC_" #inst, NULL),
/*
* TODO generalize with a more flexible for-each macro that doesn't
* assume a semicolon separator.
*/
SHELL_STATIC_SUBCMD_SET_CREATE(
sub_adc,
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
ADC_SHELL_COMMAND(0),
#endif
#if DT_HAS_DRV_INST(1)
SHELL_CMD(ADC_1, &sub_adc_cmds, "ADC_1", NULL),
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
ADC_SHELL_COMMAND(1),
#endif
#if DT_HAS_DRV_INST(2)
SHELL_CMD(ADC_2, &sub_adc_cmds, "ADC_2", NULL),
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(2))
ADC_SHELL_COMMAND(2),
#endif
SHELL_SUBCMD_SET_END /* Array terminated. */
);
SHELL_CMD_REGISTER(adc, &sub_adc, "ADC commands", NULL);

4
drivers/adc/adc_stm32.c
View file

@ -682,6 +682,4 @@ static void adc_stm32_cfg_func_##index(void) \
irq_enable(DT_INST_IRQN(index)); \
}
#if DT_HAS_DRV_INST(0)
STM32_ADC_INIT(0);
#endif /* DT_HAS_DRV_INST(0) */
DT_INST_FOREACH(STM32_ADC_INIT)

22
drivers/clock_control/clock_control_mcux_pcc.c
View file

@ -67,14 +67,16 @@ static const struct clock_control_driver_api mcux_pcc_api = {
.get_rate = mcux_pcc_get_rate,
};
#if DT_HAS_DRV_INST(0)
static const struct mcux_pcc_config mcux_pcc0_config = {
.base_address = DT_INST_REG_ADDR(0)
};
#define MCUX_PCC_INIT(inst) \
static const struct mcux_pcc_config mcux_pcc##inst##_config = { \
.base_address = DT_INST_REG_ADDR(inst) \
}; \
\
DEVICE_AND_API_INIT(mcux_pcc##inst, DT_INST_LABEL(inst), \
&mcux_pcc_init, \
NULL, &mcux_pcc##inst##_config, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \
&mcux_pcc_api)
DEVICE_AND_API_INIT(mcux_pcc0, DT_INST_LABEL(0),
&mcux_pcc_init,
NULL, &mcux_pcc0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
&mcux_pcc_api);
#endif
DT_INST_FOREACH(MCUX_PCC_INIT)

34
drivers/clock_control/clock_control_rv32m1_pcc.c
View file

@ -60,26 +60,16 @@ static const struct clock_control_driver_api rv32m1_pcc_api = {
.get_rate = rv32m1_pcc_get_rate,
};
#if DT_HAS_DRV_INST(0)
static struct rv32m1_pcc_config rv32m1_pcc0_config = {
.base_address = DT_INST_REG_ADDR(0)
};
#define RV32M1_PCC_INIT(inst) \
static struct rv32m1_pcc_config rv32m1_pcc##inst##_config = { \
.base_address = DT_INST_REG_ADDR(inst) \
}; \
\
DEVICE_AND_API_INIT(rv32m1_pcc##inst, DT_INST_LABEL(inst), \
&rv32m1_pcc_init, \
NULL, &rv32m1_pcc##inst##_config, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \
&rv32m1_pcc_api)
DEVICE_AND_API_INIT(rv32m1_pcc0, DT_INST_LABEL(0),
&rv32m1_pcc_init,
NULL, &rv32m1_pcc0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
&rv32m1_pcc_api);
#endif
#if DT_HAS_DRV_INST(1)
static struct rv32m1_pcc_config rv32m1_pcc1_config = {
.base_address = DT_INST_REG_ADDR(1)
};
DEVICE_AND_API_INIT(rv32m1_pcc1, DT_INST_LABEL(1),
&rv32m1_pcc_init,
NULL, &rv32m1_pcc1_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
&rv32m1_pcc_api);
#endif
DT_INST_FOREACH(RV32M1_PCC_INIT)

150
drivers/counter/counter_mchp_xec.c
View file

@ -309,116 +309,42 @@ static int counter_xec_init(struct device *dev)
return 0;
}
#if DT_HAS_DRV_INST(0)
#define COUNTER_XEC_INIT(inst) \
static void counter_xec_irq_config_##inst(void); \
\
static struct counter_xec_data counter_xec_dev_data_##inst; \
\
static struct counter_xec_config counter_xec_dev_config_##inst = { \
.info = { \
.max_top_value = DT_INST_PROP(inst, max_value), \
.freq = DT_INST_PROP(inst, clock_frequency) / \
(1 << DT_INST_PROP(inst, prescaler)), \
.flags = 0, \
.channels = 1, \
}, \
\
.config_func = counter_xec_irq_config_##inst, \
.base_address = DT_INST_REG_ADDR(inst), \
.prescaler = DT_INST_PROP(inst, prescaler), \
.girq_id = DT_INST_PROP(inst, girq), \
.girq_bit = DT_INST_PROP(inst, girq_bit), \
}; \
\
DEVICE_AND_API_INIT(counter_xec_##inst, DT_INST_LABEL(inst), \
counter_xec_init, \
&counter_xec_dev_data_##inst, \
&counter_xec_dev_config_##inst, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&counter_xec_api); \
\
static void counter_xec_irq_config_##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
counter_xec_isr, \
DEVICE_GET(counter_xec_##inst), 0); \
irq_enable(DT_INST_IRQN(inst)); \
}
static void counder_xec_irq_config_0(void);
static struct counter_xec_data counter_xec_dev_data_0;
static struct counter_xec_config counter_xec_dev_config_0 = {
.info = {
.max_top_value = DT_INST_PROP(0, max_value),
.freq = DT_INST_PROP(0, clock_frequency) /
(1 << DT_INST_PROP(0, prescaler)),
.flags = 0,
.channels = 1,
},
.config_func = counder_xec_irq_config_0,
.base_address = DT_INST_REG_ADDR(0),
.prescaler = DT_INST_PROP(0, prescaler),
.girq_id = DT_INST_PROP(0, girq),
.girq_bit = DT_INST_PROP(0, girq_bit),
};
DEVICE_AND_API_INIT(counter_xec_0, DT_INST_LABEL(0),
counter_xec_init, &counter_xec_dev_data_0,
&counter_xec_dev_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&counter_xec_api);
static void counder_xec_irq_config_0(void)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
counter_xec_isr, DEVICE_GET(counter_xec_0), 0);
irq_enable(DT_INST_IRQN(0));
}
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
static void counder_xec_irq_config_1(void);
static struct counter_xec_data counter_xec_dev_data_1;
static struct counter_xec_config counter_xec_dev_config_1 = {
.info = {
.max_top_value = DT_INST_PROP(1, max_value),
.freq = DT_INST_PROP(1, clock_frequency) /
(1 << DT_INST_PROP(1, prescaler)),
.flags = 0,
.channels = 1,
},
.config_func = counder_xec_irq_config_1,
.base_address = DT_INST_REG_ADDR(1),
.prescaler = DT_INST_PROP(1, prescaler),
.girq_id = DT_INST_PROP(1, girq),
.girq_bit = DT_INST_PROP(1, girq_bit),
};
DEVICE_AND_API_INIT(counter_xec_1, DT_INST_LABEL(1),
counter_xec_init, &counter_xec_dev_data_1,
&counter_xec_dev_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&counter_xec_api);
static void counder_xec_irq_config_1(void)
{
IRQ_CONNECT(DT_INST_IRQN(1),
DT_INST_IRQ(1, priority),
counter_xec_isr, DEVICE_GET(counter_xec_1), 0);
irq_enable(DT_INST_IRQN(1));
}
#endif /* DT_HAS_DRV_INST(1) */
#if DT_HAS_DRV_INST(2)
static void counder_xec_irq_config_2(void);
static struct counter_xec_data counter_xec_dev_data_2;
static struct counter_xec_config counter_xec_dev_config_2 = {
.info = {
.max_top_value = DT_INST_PROP(2, max_value),
.freq = DT_INST_PROP(2, clock_frequency) /
(1 << DT_INST_PROP(2, prescaler)),
.flags = 0,
.channels = 1,
},
.config_func = counder_xec_irq_config_2,
.base_address = DT_INST_REG_ADDR(2),
.prescaler = DT_INST_PROP(2, prescaler),
.girq_id = DT_INST_PROP(2, girq),
.girq_bit = DT_INST_PROP(2, girq_bit),
};
DEVICE_AND_API_INIT(counter_xec_2, DT_INST_LABEL(2),
counter_xec_init, &counter_xec_dev_data_2,
&counter_xec_dev_config_2,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&counter_xec_api);
static void counder_xec_irq_config_2(void)
{
IRQ_CONNECT(DT_INST_PROP(2, irq),
DT_INST_IRQ_BY_NAME(2, priority, irq),
counter_xec_isr, DEVICE_GET(counter_xec_2), 0);
irq_enable(DT_INST_PROP(2, irq));
}
#endif /* DT_HAS_DRV_INST(2) */
DT_INST_FOREACH(COUNTER_XEC_INIT)

71
drivers/counter/counter_mcux_gpt.c
View file

@ -201,42 +201,37 @@ static const struct counter_driver_api mcux_gpt_driver_api = {
.get_max_relative_alarm = mcux_gpt_get_max_relative_alarm,
};
#define GPT_DEVICE_INIT_MCUX(n) \
static struct mcux_gpt_data mcux_gpt_data_ ## n; \
\
static const struct mcux_gpt_config mcux_gpt_config_ ## n = { \
.base = (void *)DT_INST_REG_ADDR(n), \
.clock_source = kCLOCK_PerClk, \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = 25000000, \
.channels = 1, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
}, \
}; \
\
static int mcux_gpt_## n ##_init(struct device *dev); \
DEVICE_AND_API_INIT(mcux_gpt ## n, \
DT_INST_LABEL(n), \
mcux_gpt_## n ##_init, \
&mcux_gpt_data_ ## n, \
&mcux_gpt_config_ ## n, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&mcux_gpt_driver_api); \
\
static int mcux_gpt_## n ##_init(struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
mcux_gpt_isr, DEVICE_GET(mcux_gpt ## n), 0); \
irq_enable(DT_INST_IRQN(n)); \
return mcux_gpt_init(dev); \
} \
#define GPT_DEVICE_INIT_MCUX(n) \
static struct mcux_gpt_data mcux_gpt_data_ ## n; \
\
static const struct mcux_gpt_config mcux_gpt_config_ ## n = { \
.base = (void *)DT_INST_REG_ADDR(n), \
.clock_source = kCLOCK_PerClk, \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = 25000000, \
.channels = 1, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
}, \
}; \
\
static int mcux_gpt_## n ##_init(struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
mcux_gpt_isr, \
DEVICE_GET(mcux_gpt ## n), 0); \
irq_enable(DT_INST_IRQN(n)); \
return mcux_gpt_init(dev); \
} \
\
DEVICE_AND_API_INIT(mcux_gpt ## n, \
DT_INST_LABEL(n), \
mcux_gpt_## n ##_init, \
&mcux_gpt_data_ ## n, \
&mcux_gpt_config_ ## n, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&mcux_gpt_driver_api)
#if DT_HAS_DRV_INST(0)
GPT_DEVICE_INIT_MCUX(0)
#endif
#if DT_HAS_DRV_INST(1)
GPT_DEVICE_INIT_MCUX(1)
#endif
DT_INST_FOREACH(GPT_DEVICE_INIT_MCUX)

11
drivers/counter/counter_mcux_lptmr.c
View file

@ -200,7 +200,14 @@ static const struct counter_driver_api mcux_lptmr_driver_api = {
#define LPTMR_GLITCH_32768 kLPTMR_Prescale_Glitch_15
#define TO_LPTMR_GLITCH(val) _DO_CONCAT(LPTMR_GLITCH_, val)
#if DT_HAS_DRV_INST(0)
/*
* This driver is single-instance. If the devicetree contains multiple
* instances, this will fail and the driver needs to be revisited.
*/
BUILD_ASSERT(DT_NUM_INST(DT_DRV_COMPAT) <= 1,
"unsupported lptmr instance");
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
static struct mcux_lptmr_data mcux_lptmr_data_0;
static void mcux_lptmr_irq_config_0(struct device *dev);
@ -247,4 +254,4 @@ static void mcux_lptmr_irq_config_0(struct device *dev)
mcux_lptmr_isr, DEVICE_GET(mcux_lptmr_0), 0);
irq_enable(DT_INST_IRQN(0));
}
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */

89
drivers/counter/timer_dtmr_cmsdk_apb.c
View file

@ -167,45 +167,54 @@ static int dtmr_cmsdk_apb_init(struct device *dev)
return 0;
}
/* TIMER 0 */
#if DT_HAS_DRV_INST(0)
static void dtimer_cmsdk_apb_config_0(struct device *dev);
#define DTIMER_CMSDK_REG(inst) \
((volatile struct dualtimer_cmsdk_apb *)DT_INST_REG_ADDR(inst))
static const struct dtmr_cmsdk_apb_cfg dtmr_cmsdk_apb_cfg_0 = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 24000000U,
.flags = 0,
.channels = 0U,
},
.dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_INST_REG_ADDR(0)),
.dtimer_config_func = dtimer_cmsdk_apb_config_0,
.dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_INST_REG_ADDR(0),},
.dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_INST_REG_ADDR(0),},
.dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_INST_REG_ADDR(0),},
};
#define DTIMER_CMSDK_INIT(inst) \
static void dtimer_cmsdk_apb_config_##inst(struct device *dev); \
\
static const struct dtmr_cmsdk_apb_cfg \
dtmr_cmsdk_apb_cfg_##inst = { \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = 24000000U, \
.flags = 0, \
.channels = 0U, \
}, \
.dtimer = DTIMER_CMSDK_REG(inst), \
.dtimer_config_func = dtimer_cmsdk_apb_config_##inst, \
.dtimer_cc_as = {.bus = CMSDK_APB, \
.state = SOC_ACTIVE, \
.device = DT_INST_REG_ADDR(inst),}, \
.dtimer_cc_ss = {.bus = CMSDK_APB, \
.state = SOC_SLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
.dtimer_cc_dss = {.bus = CMSDK_APB, \
.state = SOC_DEEPSLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
}; \
\
static struct dtmr_cmsdk_apb_dev_data \
dtmr_cmsdk_apb_dev_data_##inst = { \
.load = UINT_MAX, \
}; \
\
DEVICE_AND_API_INIT(dtmr_cmsdk_apb_##inst, \
DT_INST_LABEL(inst), \
dtmr_cmsdk_apb_init, \
&dtmr_cmsdk_apb_dev_data_##inst, \
&dtmr_cmsdk_apb_cfg_##inst, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&dtmr_cmsdk_apb_api); \
\
static void dtimer_cmsdk_apb_config_##inst(struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
dtmr_cmsdk_apb_isr, \
DEVICE_GET(dtmr_cmsdk_apb_##inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
}
static struct dtmr_cmsdk_apb_dev_data dtmr_cmsdk_apb_dev_data_0 = {
.load = UINT_MAX,
};
DEVICE_AND_API_INIT(dtmr_cmsdk_apb_0,
DT_INST_LABEL(0),
dtmr_cmsdk_apb_init,
&dtmr_cmsdk_apb_dev_data_0,
&dtmr_cmsdk_apb_cfg_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&dtmr_cmsdk_apb_api);
static void dtimer_cmsdk_apb_config_0(struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
dtmr_cmsdk_apb_isr,
DEVICE_GET(dtmr_cmsdk_apb_0), 0);
irq_enable(DT_INST_IRQN(0));
}
#endif /* DT_HAS_DRV_INST(0) */
DT_INST_FOREACH(DTIMER_CMSDK_INIT)

122
drivers/counter/timer_tmr_cmsdk_apb.c
View file

@ -162,84 +162,46 @@ static int tmr_cmsdk_apb_init(struct device *dev)
return 0;
}
/* TIMER 0 */
#if DT_HAS_DRV_INST(0)
static void timer_cmsdk_apb_config_0(struct device *dev);
#define TIMER_CMSDK_INIT(inst) \
static void timer_cmsdk_apb_config_##inst(struct device *dev); \
\
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_##inst = { \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = 24000000U, \
.flags = 0, \
.channels = 0U, \
}, \
.timer = ((volatile struct timer_cmsdk_apb *)DT_INST_REG_ADDR(inst)), \
.timer_config_func = timer_cmsdk_apb_config_##inst, \
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, \
.device = DT_INST_REG_ADDR(inst),}, \
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
}; \
\
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_##inst = { \
.load = UINT32_MAX, \
}; \
\
DEVICE_AND_API_INIT(tmr_cmsdk_apb_##inst, \
DT_INST_LABEL(inst), \
tmr_cmsdk_apb_init, \
&tmr_cmsdk_apb_dev_data_##inst, \
&tmr_cmsdk_apb_cfg_##inst, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&tmr_cmsdk_apb_api); \
\
static void timer_cmsdk_apb_config_##inst(struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
tmr_cmsdk_apb_isr, \
DEVICE_GET(tmr_cmsdk_apb_##inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
}
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_0 = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 24000000U,
.flags = 0,
.channels = 0U,
},
.timer = ((volatile struct timer_cmsdk_apb *)DT_INST_REG_ADDR(0)),
.timer_config_func = timer_cmsdk_apb_config_0,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_INST_REG_ADDR(0),},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_INST_REG_ADDR(0),},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_INST_REG_ADDR(0),},
};
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_0 = {
.load = UINT32_MAX,
};
DEVICE_AND_API_INIT(tmr_cmsdk_apb_0,
DT_INST_LABEL(0),
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_0,
&tmr_cmsdk_apb_cfg_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&tmr_cmsdk_apb_api);
static void timer_cmsdk_apb_config_0(struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
tmr_cmsdk_apb_isr,
DEVICE_GET(tmr_cmsdk_apb_0), 0);
irq_enable(DT_INST_IRQN(0));
}
#endif /* DT_HAS_DRV_INST(0) */
/* TIMER 1 */
#if DT_HAS_DRV_INST(1)
static void timer_cmsdk_apb_config_1(struct device *dev);
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_1 = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 24000000U,
.flags = 0,
.channels = 0U,
},
.timer = ((volatile struct timer_cmsdk_apb *)DT_INST_REG_ADDR(1)),
.timer_config_func = timer_cmsdk_apb_config_1,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_INST_REG_ADDR(1),},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_INST_REG_ADDR(1),},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_INST_REG_ADDR(1),},
};
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_1 = {
.load = UINT32_MAX,
};
DEVICE_AND_API_INIT(tmr_cmsdk_apb_1,
DT_INST_LABEL(1),
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_1,
&tmr_cmsdk_apb_cfg_1, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&tmr_cmsdk_apb_api);
static void timer_cmsdk_apb_config_1(struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(1), DT_INST_IRQ(1, priority),
tmr_cmsdk_apb_isr,
DEVICE_GET(tmr_cmsdk_apb_1), 0);
irq_enable(DT_INST_IRQN(1));
}
#endif /* DT_HAS_DRV_INST(1) */
DT_INST_FOREACH(TIMER_CMSDK_INIT)

20
drivers/dac/dac_stm32.c
View file

@ -146,22 +146,6 @@ DEVICE_AND_API_INIT(dac_##index, DT_INST_LABEL(index), \
&dac_stm32_init, &dac_stm32_data_##index, \
&dac_stm32_cfg_##index, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&api_stm32_driver_api)
&api_stm32_driver_api);
/* DT instance numbering starts from 0, STM DAC from 1 */
#if DT_HAS_DRV_INST(0)
STM32_DAC_INIT(0);
#endif
#if DT_HAS_DRV_INST(1)
STM32_DAC_INIT(1);
#endif
#if DT_HAS_DRV_INST(2)
STM32_DAC_INIT(2);
#endif
#if DT_HAS_DRV_INST(3)
STM32_DAC_INIT(3);
#endif
DT_INST_FOREACH(STM32_DAC_INIT)

251
drivers/dma/dma_dw.c
View file

@ -359,189 +359,70 @@ static const struct dma_driver_api dw_dma_driver_api = {
.stop = dw_dma_transfer_stop,
};
#if DT_HAS_DRV_INST(0)
#define DW_DMAC_INIT(inst) \
\
static struct device DEVICE_NAME_GET(dw_dma##inst); \
\
static struct dw_drv_plat_data dmac##inst = { \
.chan[0] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[1] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[2] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[3] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[4] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[5] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[6] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[7] = { \
.class = 6, \
.weight = 0, \
}, \
}; \
\
static void dw_dma##inst##_irq_config(void); \
\
static const struct dw_dma_dev_cfg dw_dma##inst##_config = { \
.base = DT_INST_REG_ADDR(inst), \
.irq_config = dw_dma##inst##_irq_config \
}; \
\
static struct dw_dma_dev_data dw_dma##inst##_data = { \
.channel_data = &dmac##inst, \
}; \
\
DEVICE_AND_API_INIT(dw_dma##inst, DT_INST_LABEL(inst), \
&dw_dma_init, \
&dw_dma##inst##_data, \
&dw_dma##inst##_config, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&dw_dma_driver_api); \
\
static void dw_dma##inst##_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), dw_dma_isr, \
DEVICE_GET(dw_dma##inst), \
DT_INST_IRQ(inst, sense)); \
irq_enable(DT_INST_IRQN(inst)); \
}
static struct device DEVICE_NAME_GET(dw_dma0);
static void dw_dma0_irq_config(void)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority), dw_dma_isr,
DEVICE_GET(dw_dma0),
DT_INST_IRQ(0, sense));
irq_enable(DT_INST_IRQN(0));
}
static struct dw_drv_plat_data dmac0 = {
.chan[0] = {
.class = 6,
.weight = 0,
},
.chan[1] = {
.class = 6,
.weight = 0,
},
.chan[2] = {
.class = 6,
.weight = 0,
},
.chan[3] = {
.class = 6,
.weight = 0,
},
.chan[4] = {
.class = 6,
.weight = 0,
},
.chan[5] = {
.class = 6,
.weight = 0,
},
.chan[6] = {
.class = 6,
.weight = 0,
},
.chan[7] = {
.class = 6,
.weight = 0,
},
};
static const struct dw_dma_dev_cfg dw_dma0_config = {
.base = DT_INST_REG_ADDR(0),
.irq_config = dw_dma0_irq_config
};
static struct dw_dma_dev_data dw_dma0_data = {
.channel_data = &dmac0,
};
DEVICE_AND_API_INIT(dw_dma0, DT_INST_LABEL(0), &dw_dma_init,
&dw_dma0_data, &dw_dma0_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &dw_dma_driver_api);
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
static struct device DEVICE_NAME_GET(dw_dma2);
static void dw_dma1_irq_config(void)
{
IRQ_CONNECT(DT_INST_IRQN(1),
DT_INST_IRQ(1, priority), dw_dma_isr,
DEVICE_GET(dw_dma0),
DT_INST_IRQ(1, sense));
irq_enable(DT_INST_IRQN(1));
}
static struct dw_drv_plat_data dmac1 = {
.chan[0] = {
.class = 6,
.weight = 0,
},
.chan[1] = {
.class = 6,
.weight = 0,
},
.chan[2] = {
.class = 6,
.weight = 0,
},
.chan[3] = {
.class = 6,
.weight = 0,
},
.chan[4] = {
.class = 6,
.weight = 0,
},
.chan[5] = {
.class = 6,
.weight = 0,
},
.chan[6] = {
.class = 6,
.weight = 0,
},
.chan[7] = {
.class = 6,
.weight = 0,
},
};
static const struct dw_dma_dev_cfg dw_dma1_config = {
.base = DT_INST_REG_ADDR(1),
.irq_config = dw_dma1_irq_config
};
static struct dw_dma_dev_data dw_dma1_data = {
.channel_data = &dmac1,
};
DEVICE_AND_API_INIT(dw_dma1, DT_INST_LABEL(1), &dw_dma_init,
&dw_dma1_data, &dw_dma1_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &dw_dma_driver_api);
#endif /* DT_HAS_DRV_INST(1) */
#if DT_HAS_DRV_INST(2)
static struct device DEVICE_NAME_GET(dw_dma2);
static void dw_dma2_irq_config(void)
{
IRQ_CONNECT(DT_INST_IRQN(2),
DT_INST_IRQ(2, priority), dw_dma_isr,
DEVICE_GET(dw_dma0),
DT_INST_IRQ(2, sense));
irq_enable(DT_INST_IRQN(2));
}
static struct dw_drv_plat_data dmac2 = {
.chan[0] = {
.class = 6,
.weight = 0,
},
.chan[1] = {
.class = 6,
.weight = 0,
},
.chan[2] = {
.class = 6,
.weight = 0,
},
.chan[3] = {
.class = 6,
.weight = 0,
},
.chan[4] = {
.class = 6,
.weight = 0,
},
.chan[5] = {
.class = 6,
.weight = 0,
},
.chan[6] = {
.class = 6,
.weight = 0,
},
.chan[7] = {
.class = 6,
.weight = 0,
},
};
static const struct dw_dma_dev_cfg dw_dma2_config = {
.base = DT_INST_REG_ADDR(2),
.irq_config = dw_dma2_irq_config
};
static struct dw_dma_dev_data dw_dma2_data = {
.channel_data = &dmac2,
};
DEVICE_AND_API_INIT(dw_dma2, DT_INST_LABEL(2), &dw_dma_init,
&dw_dma2_data, &dw_dma2_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &dw_dma_driver_api);
#endif /* DT_HAS_DRV_INST(2) */
DT_INST_FOREACH(DW_DMAC_INIT)

8
drivers/dma/dma_stm32.c
View file

@ -666,7 +666,7 @@ do { \
data->max_streams++; \
} while (0)
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
DMA_INIT(0);
static void dma_stm32_config_irq_0(struct device *dev)
@ -689,10 +689,10 @@ static void dma_stm32_config_irq_0(struct device *dev)
#endif /* DT_INST_IRQ_HAS_IDX(0, 7) */
/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
}
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
DMA_INIT(1);
static void dma_stm32_config_irq_1(struct device *dev)
@ -715,4 +715,4 @@ static void dma_stm32_config_irq_1(struct device *dev)
#endif /* DT_INST_IRQ_HAS_IDX(1, 7) */
/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
}
#endif /* DT_HAS_DRV_INST(1) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1)) */

6
drivers/dma/dmamux_stm32.c
View file

@ -210,8 +210,6 @@ DEVICE_AND_API_INIT(dmamux_##index, DT_INST_LABEL(index), \
&dmamux_stm32_init, \
&dmamux_stm32_data_##index, &dmamux_stm32_config_##index,\
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,\
&dma_funcs)
&dma_funcs);
#if DT_HAS_DRV_INST(0)
DMAMUX_INIT(0);
#endif /* DT_HAS_DRV_INST(0) */
DT_INST_FOREACH(DMAMUX_INIT)

98
drivers/gpio/gpio_ht16k33.c
View file

@ -217,100 +217,4 @@ static const struct gpio_driver_api gpio_ht16k33_api = {
CONFIG_GPIO_HT16K33_INIT_PRIORITY, \
&gpio_ht16k33_api)
/* Support up to eight HT16K33 devices, each with three keyscan devices */
#if DT_HAS_DRV_INST(0)
GPIO_HT16K33_DEVICE(0);
#endif
#if DT_HAS_DRV_INST(1)
GPIO_HT16K33_DEVICE(1);
#endif
#if DT_HAS_DRV_INST(2)
GPIO_HT16K33_DEVICE(2);
#endif
#if DT_HAS_DRV_INST(3)
GPIO_HT16K33_DEVICE(3);
#endif
#if DT_HAS_DRV_INST(4)
GPIO_HT16K33_DEVICE(4);
#endif
#if DT_HAS_DRV_INST(5)
GPIO_HT16K33_DEVICE(5);
#endif
#if DT_HAS_DRV_INST(6)
GPIO_HT16K33_DEVICE(6);
#endif
#if DT_HAS_DRV_INST(7)
GPIO_HT16K33_DEVICE(7);
#endif
#if DT_HAS_DRV_INST(8)
GPIO_HT16K33_DEVICE(8);
#endif
#if DT_HAS_DRV_INST(9)
GPIO_HT16K33_DEVICE(9);
#endif
#if DT_HAS_DRV_INST(10)
GPIO_HT16K33_DEVICE(10);
#endif
#if DT_HAS_DRV_INST(11)
GPIO_HT16K33_DEVICE(11);
#endif
#if DT_HAS_DRV_INST(12)
GPIO_HT16K33_DEVICE(12);
#endif
#if DT_HAS_DRV_INST(13)
GPIO_HT16K33_DEVICE(13);
#endif
#if DT_HAS_DRV_INST(14)
GPIO_HT16K33_DEVICE(14);
#endif
#if DT_HAS_DRV_INST(15)
GPIO_HT16K33_DEVICE(15);
#endif
#if DT_HAS_DRV_INST(16)
GPIO_HT16K33_DEVICE(16);
#endif
#if DT_HAS_DRV_INST(17)
GPIO_HT16K33_DEVICE(17);
#endif
#if DT_HAS_DRV_INST(18)
GPIO_HT16K33_DEVICE(18);
#endif
#if DT_HAS_DRV_INST(19)
GPIO_HT16K33_DEVICE(19);
#endif
#if DT_HAS_DRV_INST(20)
GPIO_HT16K33_DEVICE(20);
#endif
#if DT_HAS_DRV_INST(21)
GPIO_HT16K33_DEVICE(21);
#endif
#if DT_HAS_DRV_INST(22)
GPIO_HT16K33_DEVICE(22);
#endif
#if DT_HAS_DRV_INST(23)
GPIO_HT16K33_DEVICE(23);
#endif
DT_INST_FOREACH(GPIO_HT16K33_DEVICE)

4
drivers/gpio/gpio_lmp90xxx.c
View file

@ -185,6 +185,4 @@ BUILD_ASSERT(CONFIG_GPIO_LMP90XXX_INIT_PRIORITY >
CONFIG_GPIO_LMP90XXX_INIT_PRIORITY, \
&gpio_lmp90xxx_api)
#if DT_HAS_DRV_INST(0)
GPIO_LMP90XXX_DEVICE(0);
#endif
DT_INST_FOREACH(GPIO_LMP90XXX_DEVICE)

117
drivers/gpio/gpio_mcp23s17.c
View file

@ -399,80 +399,45 @@ static int mcp23s17_init(struct device *dev)
return 0;
}
/* Initialization for MCP23S17_0 */
#if DT_HAS_DRV_INST(0)
static struct mcp23s17_config mcp23s17_0_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
},
.spi_dev_name = DT_INST_BUS_LABEL(0),
.slave = DT_INST_REG_ADDR(0),
.freq = DT_INST_PROP(0, spi_max_frequency),
#if DT_INST_SPI_DEV_HAS_CS_GPIOS(0)
.cs_dev = DT_INST_SPI_DEV_CS_GPIOS_LABEL(0),
#endif
#if DT_INST_SPI_DEV_HAS_CS_GPIOS(0)
.cs_pin = DT_INST_SPI_DEV_CS_GPIOS_PIN(0),
#endif
};
#define MCP23S17_INIT(inst) \
static struct mcp23s17_config mcp23s17_##inst##_config = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
}, \
.spi_dev_name = DT_INST_BUS_LABEL(inst), \
.slave = DT_INST_REG_ADDR(inst), \
.freq = DT_INST_PROP(inst, spi_max_frequency), \
\
IF_ENABLED(DT_INST_SPI_DEV_HAS_CS_GPIOS(inst), \
(.cs_dev = \
DT_INST_SPI_DEV_CS_GPIOS_LABEL(inst),)) \
IF_ENABLED(DT_INST_SPI_DEV_HAS_CS_GPIOS(inst), \
(.cs_pin = \
DT_INST_SPI_DEV_CS_GPIOS_PIN(inst),)) \
}; \
\
static struct mcp23s17_drv_data mcp23s17_##inst##_drvdata = { \
/* Default for registers according to datasheet */ \
.reg_cache.iodir = 0xFFFF, \
.reg_cache.ipol = 0x0, \
.reg_cache.gpinten = 0x0, \
.reg_cache.defval = 0x0, \
.reg_cache.intcon = 0x0, \
.reg_cache.iocon = 0x0, \
.reg_cache.gppu = 0x0, \
.reg_cache.intf = 0x0, \
.reg_cache.intcap = 0x0, \
.reg_cache.gpio = 0x0, \
.reg_cache.olat = 0x0, \
}; \
\
/* This has to init after SPI master */ \
DEVICE_AND_API_INIT(mcp23s17_##inst, DT_INST_LABEL(inst), \
mcp23s17_init, &mcp23s17_##inst##_drvdata, \
&mcp23s17_##inst##_config, \
POST_KERNEL, \
CONFIG_GPIO_MCP23S17_INIT_PRIORITY, \
&api_table)
static struct mcp23s17_drv_data mcp23s17_0_drvdata = {
/* Default for registers according to datasheet */
.reg_cache.iodir = 0xFFFF,
.reg_cache.ipol = 0x0,
.reg_cache.gpinten = 0x0,
.reg_cache.defval = 0x0,
.reg_cache.intcon = 0x0,
.reg_cache.iocon = 0x0,
.reg_cache.gppu = 0x0,
.reg_cache.intf = 0x0,
.reg_cache.intcap = 0x0,
.reg_cache.gpio = 0x0,
.reg_cache.olat = 0x0,
};
/* This has to init after SPI master */
DEVICE_AND_API_INIT(mcp23s17_0, DT_INST_LABEL(0),
mcp23s17_init, &mcp23s17_0_drvdata, &mcp23s17_0_config,
POST_KERNEL, CONFIG_GPIO_MCP23S17_INIT_PRIORITY,
&api_table);
#endif /* DT_HAS_DRV_INST(0) */
/* Initialization for MCP23S17_1 */
#if DT_HAS_DRV_INST(1)
static struct mcp23s17_config mcp23s17_1_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(1),
},
.spi_dev_name = DT_INST_BUS_LABEL(1),
.slave = DT_INST_REG_ADDR(1),
.freq = DT_INST_PROP(1, spi_max_frequency),
#if DT_INST_SPI_DEV_HAS_CS_GPIOS(1)
.cs_dev = DT_INST_SPI_DEV_CS_GPIOS_LABEL(1),
#endif
#if DT_INST_SPI_DEV_HAS_CS_GPIOS(1)
.cs_pin = DT_INST_SPI_DEV_CS_GPIOS_PIN(1),
#endif
};
static struct mcp23s17_drv_data mcp23s17_1_drvdata = {
/* Default for registers according to datasheet */
.reg_cache.iodir = 0xFFFF,
.reg_cache.ipol = 0x0,
.reg_cache.gpinten = 0x0,
.reg_cache.defval = 0x0,
.reg_cache.intcon = 0x0,
.reg_cache.iocon = 0x0,
.reg_cache.gppu = 0x0,
.reg_cache.intf = 0x0,
.reg_cache.intcap = 0x0,
.reg_cache.gpio = 0x0,
.reg_cache.olat = 0x0,
};
/* This has to init after SPI master */
DEVICE_AND_API_INIT(mcp23s17_1, DT_INST_LABEL(1),
mcp23s17_init, &mcp23s17_1_drvdata, &mcp23s17_1_config,
POST_KERNEL, CONFIG_GPIO_MCP23S17_INIT_PRIORITY,
&api_table);
#endif /* DT_HAS_DRV_INST(0) */
DT_INST_FOREACH(MCP23S17_INIT)

19
drivers/gpio/gpio_pca95xx.c
View file

@ -514,21 +514,6 @@ DEVICE_AND_API_INIT(gpio_pca95xx_##inst, \
&gpio_pca95xx_##inst##_drvdata, \
&gpio_pca95xx_##inst##_cfg, \
POST_KERNEL, CONFIG_GPIO_PCA95XX_INIT_PRIORITY, \
&gpio_pca95xx_drv_api_funcs)
&gpio_pca95xx_drv_api_funcs);
#if DT_HAS_DRV_INST(0)
GPIO_PCA95XX_DEVICE_INSTANCE(0);
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
GPIO_PCA95XX_DEVICE_INSTANCE(1);
#endif /* DT_HAS_DRV_INST(1) */
#if DT_HAS_DRV_INST(2)
GPIO_PCA95XX_DEVICE_INSTANCE(2);
#endif /* DT_HAS_DRV_INST(2) */
#if DT_HAS_DRV_INST(3)
GPIO_PCA95XX_DEVICE_INSTANCE(3);
#endif /* DT_HAS_DRV_INST(3) */
DT_INST_FOREACH(GPIO_PCA95XX_DEVICE_INSTANCE)

16
drivers/i2c/i2c_dw.c
View file

@ -654,34 +654,34 @@ static int i2c_dw_initialize(struct device *dev)
return 0;
}
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
#include <i2c_dw_port_0.h>
#endif
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
#include <i2c_dw_port_1.h>
#endif
#if DT_HAS_DRV_INST(2)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(2))
#include <i2c_dw_port_2.h>
#endif
#if DT_HAS_DRV_INST(3)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(3))
#include <i2c_dw_port_3.h>
#endif
#if DT_HAS_DRV_INST(4)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(4))
#include <i2c_dw_port_4.h>
#endif
#if DT_HAS_DRV_INST(5)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(5))
#include <i2c_dw_port_5.h>
#endif
#if DT_HAS_DRV_INST(6)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(6))
#include <i2c_dw_port_6.h>
#endif
#if DT_HAS_DRV_INST(7)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(7))
#include <i2c_dw_port_7.h>
#endif

8
drivers/i2c/i2c_esp32.c
View file

@ -566,7 +566,7 @@ static const struct i2c_driver_api i2c_esp32_driver_api = {
.transfer = i2c_esp32_transfer,
};
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
DEVICE_DECLARE(i2c_esp32_0);
static void i2c_esp32_connect_irq_0(void)
@ -612,9 +612,9 @@ DEVICE_AND_API_INIT(i2c_esp32_0, DT_INST_LABEL(0), &i2c_esp32_init,
&i2c_esp32_data_0, &i2c_esp32_config_0,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_esp32_driver_api);
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
DEVICE_DECLARE(i2c_esp32_1);
static void i2c_esp32_connect_irq_1(void)
@ -660,7 +660,7 @@ DEVICE_AND_API_INIT(i2c_esp32_1, DT_INST_LABEL(1), &i2c_esp32_init,
&i2c_esp32_data_1, &i2c_esp32_config_1,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_esp32_driver_api);
#endif /* DT_HAS_DRV_INST(1) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1)) */
static int i2c_esp32_init(struct device *dev)
{

8
drivers/i2c/i2c_gecko.c
View file

@ -188,7 +188,7 @@ static const struct i2c_driver_api i2c_gecko_driver_api = {
.transfer = i2c_gecko_transfer,
};
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
#define PIN_I2C_0_SDA {DT_INST_PROP_BY_IDX(0, location_sda, 1), \
DT_INST_PROP_BY_IDX(0, location_sda, 2), gpioModeWiredAnd, 1}
@ -220,9 +220,9 @@ DEVICE_AND_API_INIT(i2c_gecko_0, DT_INST_LABEL(0),
&i2c_gecko_init, &i2c_gecko_data_0, &i2c_gecko_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_gecko_driver_api);
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
#define PIN_I2C_1_SDA {DT_INST_PROP_BY_IDX(1, location_sda, 1), \
DT_INST_PROP_BY_IDX(1, location_sda, 2), gpioModeWiredAnd, 1}
@ -254,4 +254,4 @@ DEVICE_AND_API_INIT(i2c_gecko_1, DT_INST_LABEL(1),
&i2c_gecko_init, &i2c_gecko_data_1, &i2c_gecko_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_gecko_driver_api);
#endif /* DT_HAS_DRV_INST(1) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1)) */

22
drivers/i2c/i2c_mchp_xec.c
View file

@ -427,24 +427,6 @@ static int i2c_xec_init(struct device *dev)
DT_INST_LABEL(n), \
&i2c_xec_init, &i2c_xec_data_##n, &i2c_xec_config_##n, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_xec_driver_api)
&i2c_xec_driver_api);
#if DT_HAS_DRV_INST(0)
I2C_XEC_DEVICE(0);
#endif
#if DT_HAS_DRV_INST(1)
I2C_XEC_DEVICE(1);
#endif
#if DT_HAS_DRV_INST(2)
I2C_XEC_DEVICE(2);
#endif
#if DT_HAS_DRV_INST(3)
I2C_XEC_DEVICE(3);
#endif
#if DT_HAS_DRV_INST(4)
I2C_XEC_DEVICE(4);
#endif
DT_INST_FOREACH(I2C_XEC_DEVICE)

16
drivers/i2c/i2c_sbcon.c
View file

@ -122,18 +122,4 @@ DEVICE_AND_API_INIT(i2c_sbcon_##_num, DT_INST_LABEL(_num), \
&i2c_sbcon_dev_cfg_##_num, \
PRE_KERNEL_2, CONFIG_I2C_INIT_PRIORITY, &api)
#if DT_HAS_DRV_INST(0)
DEFINE_I2C_SBCON(0);
#endif
#if DT_HAS_DRV_INST(1)
DEFINE_I2C_SBCON(1);
#endif
#if DT_HAS_DRV_INST(2)
DEFINE_I2C_SBCON(2);
#endif
#if DT_HAS_DRV_INST(3)
DEFINE_I2C_SBCON(3);
#endif
DT_INST_FOREACH(DEFINE_I2C_SBCON)

4
drivers/i2c/i2c_sifive.c
View file

@ -347,6 +347,4 @@ static struct i2c_driver_api i2c_sifive_api = {
CONFIG_I2C_INIT_PRIORITY, \
&i2c_sifive_api)
#if DT_HAS_DRV_INST(0)
I2C_SIFIVE_INIT(0);
#endif
DT_INST_FOREACH(I2C_SIFIVE_INIT)

64
drivers/i2c/slave/eeprom_slave.c
View file

@ -205,44 +205,28 @@ static int i2c_eeprom_slave_init(struct device *dev)
return 0;
}
#if DT_HAS_DRV_INST(0)
#define I2C_EEPROM_INIT(inst) \
static struct i2c_eeprom_slave_data \
i2c_eeprom_slave_##inst##_dev_data; \
\
static u8_t \
i2c_eeprom_slave_##inst##_buffer[(DT_INST_PROP(inst, size))]; \
\
static const struct i2c_eeprom_slave_config \
i2c_eeprom_slave_##inst##_cfg = { \
.controller_dev_name = DT_INST_BUS_LABEL(inst), \
.address = DT_INST_REG_ADDR(inst), \
.buffer_size = DT_INST_PROP(inst, size), \
.buffer = i2c_eeprom_slave_##inst##_buffer \
}; \
\
DEVICE_AND_API_INIT(i2c_eeprom_slave_##inst, \
DT_INST_LABEL(inst), \
&i2c_eeprom_slave_init, \
&i2c_eeprom_slave_##inst##_dev_data, \
&i2c_eeprom_slave_##inst##_cfg, \
POST_KERNEL, \
CONFIG_I2C_SLAVE_INIT_PRIORITY, \
&api_funcs)
static struct i2c_eeprom_slave_data i2c_eeprom_slave_0_dev_data;
static u8_t i2c_eeprom_slave_0_buffer[(DT_INST_PROP(0, size))];
static const struct i2c_eeprom_slave_config i2c_eeprom_slave_0_cfg = {
.controller_dev_name = DT_INST_BUS_LABEL(0),
.address = DT_INST_REG_ADDR(0),
.buffer_size = DT_INST_PROP(0, size),
.buffer = i2c_eeprom_slave_0_buffer
};
DEVICE_AND_API_INIT(i2c_eeprom_slave_0, DT_INST_LABEL(0),
&i2c_eeprom_slave_init,
&i2c_eeprom_slave_0_dev_data, &i2c_eeprom_slave_0_cfg,
POST_KERNEL, CONFIG_I2C_SLAVE_INIT_PRIORITY,
&api_funcs);
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
static struct i2c_eeprom_slave_data i2c_eeprom_slave_1_dev_data;
static u8_t i2c_eeprom_slave_1_buffer[(DT_INST_PROP(1, size))];
static const struct i2c_eeprom_slave_config i2c_eeprom_slave_1_cfg = {
.controller_dev_name = DT_INST_BUS_LABEL(1),
.address = DT_INST_REG_ADDR(1),
.buffer_size = DT_INST_PROP(1, size),
.buffer = i2c_eeprom_slave_1_buffer
};
DEVICE_AND_API_INIT(i2c_eeprom_slave_1, DT_INST_LABEL(1),
&i2c_eeprom_slave_init,
&i2c_eeprom_slave_1_dev_data, &i2c_eeprom_slave_1_cfg,
POST_KERNEL, CONFIG_I2C_SLAVE_INIT_PRIORITY,
&api_funcs);
#endif /* DT_HAS_DRV_INST(1) */
DT_INST_FOREACH(I2C_EEPROM_INIT)

28
drivers/ieee802154/ieee802154_rf2xx.c
View file

@ -922,24 +922,12 @@ static struct ieee802154_radio_api rf2xx_radio_api = {
L2_CTX_TYPE, \
MTU)
#if DT_HAS_DRV_INST(0)
IEEE802154_RF2XX_DEVICE_CONFIG(0);
IEEE802154_RF2XX_DEVICE_DATA(0);
#define IEEE802154_RF2XX_INIT(inst) \
IEEE802154_RF2XX_DEVICE_CONFIG(inst); \
IEEE802154_RF2XX_DEVICE_DATA(inst); \
\
COND_CODE_1(CONFIG_IEEE802154_RAW_MODE, \
(IEEE802154_RF2XX_RAW_DEVICE_INIT(inst);), \
(IEEE802154_RF2XX_NET_DEVICE_INIT(inst);))
#if defined(CONFIG_IEEE802154_RAW_MODE)
IEEE802154_RF2XX_RAW_DEVICE_INIT(0);
#else
IEEE802154_RF2XX_NET_DEVICE_INIT(0);
#endif /* CONFIG_IEEE802154_RAW_MODE */
#endif
#if DT_HAS_DRV_INST(1)
IEEE802154_RF2XX_DEVICE_CONFIG(1);
IEEE802154_RF2XX_DEVICE_DATA(1);
#if defined(CONFIG_IEEE802154_RAW_MODE)
IEEE802154_RF2XX_RAW_DEVICE_INIT(1);
#else
IEEE802154_RF2XX_NET_DEVICE_INIT(1);
#endif /* CONFIG_IEEE802154_RAW_MODE */
#endif
DT_INST_FOREACH(IEEE802154_RF2XX_INIT)

101
drivers/led/ht16k33.c
View file

@ -463,103 +463,44 @@ static const struct led_driver_api ht16k33_leds_api = {
#define HT16K33_DEVICE(id) \
static const struct ht16k33_cfg ht16k33_##id##_cfg = { \
.i2c_dev_name = DT_INST_BUS_LABEL(id), \
.i2c_addr = DT_INST_REG_ADDR(id), \
.i2c_dev_name = DT_INST_BUS_LABEL(id), \
.i2c_addr = DT_INST_REG_ADDR(id), \
.irq_enabled = false, \
}; \
\
static struct ht16k33_data ht16k33_##id##_data; \
static struct ht16k33_data ht16k33_##id##_data; \
\
DEVICE_AND_API_INIT(ht16k33_##id, DT_INST_LABEL(id), \
&ht16k33_init, &ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
DEVICE_AND_API_INIT(ht16k33_##id, DT_INST_LABEL(id), \
&ht16k33_init, &ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
#ifdef CONFIG_HT16K33_KEYSCAN
#define HT16K33_DEVICE_WITH_IRQ(id) \
static const struct ht16k33_cfg ht16k33_##id##_cfg = { \
.i2c_dev_name = DT_INST_BUS_LABEL(id), \
.i2c_addr = DT_INST_REG_ADDR(id), \
.i2c_dev_name = DT_INST_BUS_LABEL(id), \
.i2c_addr = DT_INST_REG_ADDR(id), \
.irq_enabled = true, \
.irq_dev_name = \
DT_INST_GPIO_LABEL(id, irq_gpios), \
DT_INST_GPIO_LABEL(id, irq_gpios), \
.irq_pin = DT_INST_GPIO_PIN(id, irq_gpios), \
.irq_flags = \
DT_INST_GPIO_FLAGS(id, irq_gpios), \
DT_INST_GPIO_FLAGS(id, irq_gpios), \
}; \
\
static struct ht16k33_data ht16k33_##id##_data; \
static struct ht16k33_data ht16k33_##id##_data; \
\
DEVICE_AND_API_INIT(ht16k33_##id, DT_INST_LABEL(id), \
&ht16k33_init, &ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
DEVICE_AND_API_INIT(ht16k33_##id, DT_INST_LABEL(id), \
&ht16k33_init, &ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
#else /* ! CONFIG_HT16K33_KEYSCAN */
#define HT16K33_DEVICE_WITH_IRQ(id) HT16K33_DEVICE(id)
#endif /* ! CONFIG_HT16K33_KEYSCAN */
/* Support up to eight HT16K33 devices */
#define HT16K33_INSTANTIATE(id) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(id, irq_gpios), \
(HT16K33_DEVICE_WITH_IRQ(id)), \
(HT16K33_DEVICE(id)))
#if DT_HAS_DRV_INST(0)
#if DT_INST_NODE_HAS_PROP(0, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(0);
#else
HT16K33_DEVICE(0);
#endif
#endif
#if DT_HAS_DRV_INST(1)
#if DT_INST_NODE_HAS_PROP(1, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(1);
#else
HT16K33_DEVICE(1);
#endif
#endif
#if DT_HAS_DRV_INST(2)
#if DT_INST_NODE_HAS_PROP(2, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(2);
#else
HT16K33_DEVICE(2);
#endif
#endif
#if DT_HAS_DRV_INST(3)
#if DT_INST_NODE_HAS_PROP(3, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(3);
#else
HT16K33_DEVICE(3);
#endif
#endif
#if DT_HAS_DRV_INST(4)
#if DT_INST_NODE_HAS_PROP(4, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(4);
#else
HT16K33_DEVICE(4);
#endif
#endif
#if DT_HAS_DRV_INST(5)
#if DT_INST_NODE_HAS_PROP(5, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(5);
#else
HT16K33_DEVICE(5);
#endif
#endif
#if DT_HAS_DRV_INST(6)
#if DT_INST_NODE_HAS_PROP(6, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(6);
#else
HT16K33_DEVICE(6);
#endif
#endif
#if DT_HAS_DRV_INST(7)
#if DT_INST_NODE_HAS_PROP(7, irq_gpios)
HT16K33_DEVICE_WITH_IRQ(7);
#else
HT16K33_DEVICE(7);
#endif
#endif
DT_INST_FOREACH(HT16K33_INSTANTIATE);

129
drivers/pwm/pwm_mchp_xec.c
View file

@ -382,119 +382,18 @@ static struct pwm_driver_api pwm_xec_api = {
.get_cycles_per_sec = pwm_xec_get_cycles_per_sec
};
#if DT_HAS_DRV_INST(0)
#define XEC_INST_INIT(inst) \
static struct pwm_xec_config pwm_xec_dev_config_##inst = { \
.base_address = DT_INST_REG_ADDR(inst) \
}; \
\
DEVICE_AND_API_INIT(pwm_xec_##inst, \
DT_INST_LABEL(inst), \
pwm_xec_init, \
NULL, \
&pwm_xec_dev_config_##inst, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&pwm_xec_api)
static struct pwm_xec_config pwm_xec_dev_config_0 = {
.base_address = DT_INST_REG_ADDR(0)
};
DEVICE_AND_API_INIT(pwm_xec_0, DT_INST_LABEL(0),
pwm_xec_init, NULL, &pwm_xec_dev_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
static struct pwm_xec_config pwm_xec_dev_config_1 = {
.base_address = DT_INST_REG_ADDR(1)
};
DEVICE_AND_API_INIT(pwm_xec_1, DT_INST_LABEL(1),
pwm_xec_init, NULL, &pwm_xec_dev_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(1) */
#if DT_HAS_DRV_INST(2)
static struct pwm_xec_config pwm_xec_dev_config_2 = {
.base_address = DT_INST_REG_ADDR(2)
};
DEVICE_AND_API_INIT(pwm_xec_2, DT_INST_LABEL(2),
pwm_xec_init, NULL, &pwm_xec_dev_config_2,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(2) */
#if DT_HAS_DRV_INST(3)
static struct pwm_xec_config pwm_xec_dev_config_3 = {
.base_address = DT_INST_REG_ADDR(3)
};
DEVICE_AND_API_INIT(pwm_xec_3, DT_INST_LABEL(3),
pwm_xec_init, NULL, &pwm_xec_dev_config_3,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(3) */
#if DT_HAS_DRV_INST(4)
static struct pwm_xec_config pwm_xec_dev_config_4 = {
.base_address = DT_INST_REG_ADDR(4)
};
DEVICE_AND_API_INIT(pwm_xec_4, DT_INST_LABEL(4),
pwm_xec_init, NULL, &pwm_xec_dev_config_4,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(4) */
#if DT_HAS_DRV_INST(5)
static struct pwm_xec_config pwm_xec_dev_config_5 = {
.base_address = DT_INST_REG_ADDR(5)
};
DEVICE_AND_API_INIT(pwm_xec_5, DT_INST_LABEL(5),
pwm_xec_init, NULL, &pwm_xec_dev_config_5,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(5) */
#if DT_HAS_DRV_INST(6)
static struct pwm_xec_config pwm_xec_dev_config_6 = {
.base_address = DT_INST_REG_ADDR(6)
};
DEVICE_AND_API_INIT(pwm_xec_6, DT_INST_LABEL(6),
pwm_xec_init, NULL, &pwm_xec_dev_config_6,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(6) */
#if DT_HAS_DRV_INST(7)
static struct pwm_xec_config pwm_xec_dev_config_7 = {
.base_address = DT_INST_REG_ADDR(7)
};
DEVICE_AND_API_INIT(pwm_xec_7, DT_INST_LABEL(7),
pwm_xec_init, NULL, &pwm_xec_dev_config_7,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(7) */
#if DT_HAS_DRV_INST(8)
static struct pwm_xec_config pwm_xec_dev_config_8 = {
.base_address = DT_INST_REG_ADDR(8)
};
DEVICE_AND_API_INIT(pwm_xec_8, DT_INST_LABEL(8),
pwm_xec_init, NULL, &pwm_xec_dev_config_8,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&pwm_xec_api);
#endif /* DT_HAS_DRV_INST(8) */
DT_INST_FOREACH(XEC_INST_INIT)

16
drivers/pwm/pwm_mcux_ftm.c
View file

@ -172,18 +172,4 @@ static const struct pwm_driver_api mcux_ftm_driver_api = {
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&mcux_ftm_driver_api)
#if DT_HAS_DRV_INST(0)
FTM_DEVICE(0);
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
FTM_DEVICE(1);
#endif /* DT_HAS_DRV_INST(1) */
#if DT_HAS_DRV_INST(2)
FTM_DEVICE(2);
#endif /* DT_HAS_DRV_INST(2) */
#if DT_HAS_DRV_INST(3)
FTM_DEVICE(3);
#endif /* DT_HAS_DRV_INST(3) */
DT_INST_FOREACH(FTM_DEVICE);

41
drivers/pwm/pwm_sam.c
View file

@ -98,30 +98,19 @@ static const struct pwm_driver_api sam_pwm_driver_api = {
.get_cycles_per_sec = sam_pwm_get_cycles_per_sec,
};
#if DT_HAS_DRV_INST(0)
static const struct sam_pwm_config sam_pwm_config_0 = {
.regs = (Pwm *)DT_INST_REG_ADDR(0),
.id = DT_INST_PROP(0, peripheral_id),
.prescaler = DT_INST_PROP(0, prescaler),
.divider = DT_INST_PROP(0, divider),
};
#define SAM_INST_INIT(inst) \
static const struct sam_pwm_config sam_pwm_config_##inst = { \
.regs = (Pwm *)DT_INST_REG_ADDR(inst), \
.id = DT_INST_PROP(inst, peripheral_id), \
.prescaler = DT_INST_PROP(inst, prescaler), \
.divider = DT_INST_PROP(inst, divider), \
}; \
\
DEVICE_AND_API_INIT(sam_pwm_##inst, DT_INST_LABEL(inst), \
&sam_pwm_init, \
NULL, &sam_pwm_config_##inst, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&sam_pwm_driver_api)
DEVICE_AND_API_INIT(sam_pwm_0, DT_INST_LABEL(0), &sam_pwm_init,
NULL, &sam_pwm_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&sam_pwm_driver_api);
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
static const struct sam_pwm_config sam_pwm_config_1 = {
.regs = (Pwm *)DT_INST_REG_ADDR(1),
.id = DT_INST_PROP(1, peripheral_id),
.prescaler = DT_INST_PROP(1, prescaler),
.divider = DT_INST_PROP(1, divider),
};
DEVICE_AND_API_INIT(sam_pwm_1, DT_INST_LABEL(1), &sam_pwm_init,
NULL, &sam_pwm_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&sam_pwm_driver_api);
#endif /* DT_HAS_DRV_INST(1) */
DT_INST_FOREACH(SAM_INST_INIT)

7
drivers/sensor/nxp_kinetis_temp/temp_kinetis.c
View file

@ -180,7 +180,10 @@ static int temp_kinetis_init(struct device *dev)
return 0;
}
#if DT_HAS_DRV_INST(0)
BUILD_ASSERT(DT_NUM_INST(DT_DRV_COMPAT) <= 1,
"unsupported temp instance");
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
BUILD_ASSERT(DT_INST_IO_CHANNELS_INPUT_BY_NAME(0, sensor) <
DT_INST_IO_CHANNELS_INPUT_BY_NAME(0, bandgap),
"This driver assumes sensor ADC channel to come before "
@ -218,4 +221,4 @@ DEVICE_AND_API_INIT(temp_kinetis, DT_INST_LABEL(0),
CONFIG_SENSOR_INIT_PRIORITY,
&temp_kinetis_driver_api);
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */

8
drivers/serial/leuart_gecko.c
View file

@ -317,7 +317,7 @@ static const struct uart_driver_api leuart_gecko_driver_api = {
#endif
};
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
#define PIN_LEUART_0_RXD {DT_INST_PROP_BY_IDX(0, location_rx, 1), \
DT_INST_PROP_BY_IDX(0, location_rx, 2), gpioModeInput, 1}
@ -368,9 +368,9 @@ static void leuart_gecko_config_func_0(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
#define PIN_LEUART_1_RXD {DT_INST_PROP_BY_IDX(1, location_rx, 1), \
DT_INST_PROP_BY_IDX(1, location_rx, 2), gpioModeInput, 1}
@ -421,4 +421,4 @@ static void leuart_gecko_config_func_1(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(1) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1)) */

20
drivers/serial/uart_cmsdk_apb.c
View file

@ -458,7 +458,7 @@ static const struct uart_driver_api uart_cmsdk_apb_driver_api = {
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_cmsdk_apb_irq_config_func_0(struct device *dev);
@ -521,9 +521,9 @@ static void uart_cmsdk_apb_irq_config_func_0(struct device *dev)
#endif
#endif
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_cmsdk_apb_irq_config_func_1(struct device *dev);
@ -586,9 +586,9 @@ static void uart_cmsdk_apb_irq_config_func_1(struct device *dev)
#endif
#endif
#endif /* DT_HAS_DRV_INST(1) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1)) */
#if DT_HAS_DRV_INST(2)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(2))
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_cmsdk_apb_irq_config_func_2(struct device *dev);
@ -651,9 +651,9 @@ static void uart_cmsdk_apb_irq_config_func_2(struct device *dev)
#endif
#endif
#endif /* DT_HAS_DRV_INST(2) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(2)) */
#if DT_HAS_DRV_INST(3)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(3))
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_cmsdk_apb_irq_config_func_3(struct device *dev);
@ -716,9 +716,9 @@ static void uart_cmsdk_apb_irq_config_func_3(struct device *dev)
#endif
#endif
#endif /* DT_HAS_DRV_INST(3) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(3)) */
#if DT_HAS_DRV_INST(4)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(4))
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_cmsdk_apb_irq_config_func_4(struct device *dev);
@ -781,4 +781,4 @@ static void uart_cmsdk_apb_irq_config_func_4(struct device *dev)
#endif
#endif
#endif /* DT_HAS_DRV_INST(4) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(4)) */

12
drivers/serial/uart_esp32.c
View file

@ -539,14 +539,4 @@ DEVICE_AND_API_INIT(uart_esp32_##idx, \
\
ESP32_UART_IRQ_HANDLER(idx)
#if DT_HAS_DRV_INST(0)
ESP32_UART_INIT(0);
#endif
#if DT_HAS_DRV_INST(1)
ESP32_UART_INIT(1);
#endif
#if DT_HAS_DRV_INST(2)
ESP32_UART_INIT(2);
#endif
DT_INST_FOREACH(ESP32_UART_INIT)

32
drivers/serial/uart_gecko.c
View file

@ -303,7 +303,7 @@ static const struct uart_driver_api uart_gecko_driver_api = {
#define DT_DRV_COMPAT silabs_gecko_uart
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
#define PIN_UART0_RXD {DT_INST_PROP_BY_IDX(0, location_rx, 1), \
DT_INST_PROP_BY_IDX(0, location_rx, 2), gpioModeInput, 1}
@ -356,9 +356,9 @@ static void uart_gecko_config_func_0(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
#define PIN_UART1_RXD {DT_INST_PROP_BY_IDX(1, location_rx, 1), \
DT_INST_PROP_BY_IDX(1, location_rx, 2), gpioModeInput, 1}
@ -411,12 +411,12 @@ static void uart_gecko_config_func_1(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(1) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1)) */
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT silabs_gecko_usart
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
#define PIN_USART0_RXD {DT_INST_PROP_BY_IDX(0, location_rx, 1), \
DT_INST_PROP_BY_IDX(0, location_rx, 2), gpioModeInput, 1}
@ -470,9 +470,9 @@ static void usart_gecko_config_func_0(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1))
#define PIN_USART1_RXD {DT_INST_PROP_BY_IDX(1, location_rx, 1), \
DT_INST_PROP_BY_IDX(1, location_rx, 2), gpioModeInput, 1}
@ -526,9 +526,9 @@ static void usart_gecko_config_func_1(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(1) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(1)) */
#if DT_HAS_DRV_INST(2)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(2))
#define PIN_USART2_RXD {DT_INST_PROP_BY_IDX(2, location_rx, 1), \
DT_INST_PROP_BY_IDX(2, location_rx, 2), gpioModeInput, 1}
@ -582,9 +582,9 @@ static void usart_gecko_config_func_2(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(2) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(2)) */
#if DT_HAS_DRV_INST(3)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(3))
#define PIN_USART3_RXD {DT_INST_PROP_BY_IDX(3, location_rx, 1), \
DT_INST_PROP_BY_IDX(3, location_rx, 2), gpioModeInput, 1}
@ -638,9 +638,9 @@ static void usart_gecko_config_func_3(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(3) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(3)) */
#if DT_HAS_DRV_INST(4)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(4))
#define PIN_USART4_RXD {DT_INST_PROP_BY_IDX(4, location_rx, 1), \
DT_INST_PROP_BY_IDX(4, location_rx, 2), gpioModeInput, 1}
@ -694,9 +694,9 @@ static void usart_gecko_config_func_4(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(4) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(4)) */
#if DT_HAS_DRV_INST(5)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(5))
#define PIN_USART5_RXD {DT_INST_PROP_BY_IDX(5, location_rx, 1), \
DT_INST_PROP_BY_IDX(5, location_rx, 2), gpioModeInput, 1}
@ -750,4 +750,4 @@ static void usart_gecko_config_func_5(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(5) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(5)) */

8
drivers/serial/uart_miv.c
View file

@ -381,7 +381,11 @@ static const struct uart_driver_api uart_miv_driver_api = {
#endif
};
#if DT_HAS_DRV_INST(0)
/* This driver is single-instance. */
BUILD_ASSERT(DT_NUM_INST(DT_DRV_COMPAT) <= 1,
"unsupported uart_miv instance");
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0))
static struct uart_miv_data uart_miv_data_0;
@ -414,4 +418,4 @@ static void uart_miv_irq_cfg_func_0(struct device *dev)
}
#endif
#endif /* DT_HAS_DRV_INST(0) */
#endif /* DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(0)) */

2
drivers/serial/uart_ns16550_port_x.h
View file

@ -7,7 +7,7 @@
* This file is a template for cmake and is not meant to be used directly!
*/
#if DT_HAS_DRV_INST(@NUM@)
#if DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(@NUM@))
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void irq_config_func_@NUM@(struct device *port);

44
drivers/serial/uart_stm32.c
View file

@ -779,46 +779,4 @@ DEVICE_AND_API_INIT(uart_stm32_##index, DT_INST_LABEL(index),\
\
STM32_UART_IRQ_HANDLER(index)
#if DT_HAS_DRV_INST(0)
STM32_UART_INIT(0)
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
STM32_UART_INIT(1)
#endif /* DT_HAS_DRV_INST(1) */
#if DT_HAS_DRV_INST(2)
STM32_UART_INIT(2)
#endif /* DT_HAS_DRV_INST(2) */
#if DT_HAS_DRV_INST(3)
STM32_UART_INIT(3)
#endif /* DT_HAS_DRV_INST(3) */
#if DT_HAS_DRV_INST(4)
STM32_UART_INIT(4)
#endif /* DT_HAS_DRV_INST(4) */
#if DT_HAS_DRV_INST(5)
STM32_UART_INIT(5)
#endif /* DT_HAS_DRV_INST(5) */
#if DT_HAS_DRV_INST(6)
STM32_UART_INIT(6)
#endif /* DT_HAS_DRV_INST(6) */
#if DT_HAS_DRV_INST(7)
STM32_UART_INIT(7)
#endif /* DT_HAS_DRV_INST(7) */
#if DT_HAS_DRV_INST(8)
STM32_UART_INIT(8)
#endif /* DT_HAS_DRV_INST(8) */
#if DT_HAS_DRV_INST(9)
STM32_UART_INIT(9)
#endif /* DT_HAS_DRV_INST(9) */
#if DT_HAS_DRV_INST(10)
STM32_UART_INIT(10)
#endif /* DT_HAS_DRV_INST(10) */
DT_INST_FOREACH(STM32_UART_INIT)

18
drivers/serial/uart_xlnx_ps.c
View file

@ -1213,16 +1213,10 @@ DEVICE_AND_API_INIT(uart_xlnx_ps_##port, DT_INST_LABEL(port), \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&uart_xlnx_ps_driver_api)
#if DT_HAS_DRV_INST(0)
UART_XLNX_PS_IRQ_CONF_FUNC(0);
UART_XLNX_PS_DEV_DATA(0);
UART_XLNX_PS_DEV_CFG(0);
UART_XLNX_PS_INIT(0);
#endif
#define UART_XLNX_INSTANTIATE(inst) \
UART_XLNX_PS_IRQ_CONF_FUNC(inst); \
UART_XLNX_PS_DEV_DATA(inst); \
UART_XLNX_PS_DEV_CFG(inst); \
UART_XLNX_PS_INIT(inst)
#if DT_HAS_DRV_INST(1)
UART_XLNX_PS_IRQ_CONF_FUNC(1);
UART_XLNX_PS_DEV_DATA(1);
UART_XLNX_PS_DEV_CFG(1);
UART_XLNX_PS_INIT(1);
#endif
DT_INST_FOREACH(UART_XLNX_INSTANTIATE)

24
drivers/spi/spi_ll_stm32.c
View file

@ -898,26 +898,4 @@ DEVICE_AND_API_INIT(spi_stm32_##id, DT_INST_LABEL(id), \
\
STM32_SPI_IRQ_HANDLER(id)
#if DT_HAS_DRV_INST(0)
STM32_SPI_INIT(0)
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
STM32_SPI_INIT(1)
#endif /* DT_HAS_DRV_INST(1) */
#if DT_HAS_DRV_INST(2)
STM32_SPI_INIT(2)
#endif /* DT_HAS_DRV_INST(2) */
#if DT_HAS_DRV_INST(3)
STM32_SPI_INIT(3)
#endif /* DT_HAS_DRV_INST(3) */
#if DT_HAS_DRV_INST(4)
STM32_SPI_INIT(4)
#endif /* DT_HAS_DRV_INST(4) */
#if DT_HAS_DRV_INST(5)
STM32_SPI_INIT(5)
#endif /* DT_HAS_DRV_INST(5) */
DT_INST_FOREACH(STM32_SPI_INIT)

57
drivers/spi/spi_oc_simple.c
View file

@ -203,42 +203,23 @@ int spi_oc_simple_init(struct device *dev)
return 0;
}
#if DT_HAS_DRV_INST(0)
static struct spi_oc_simple_cfg spi_oc_simple_cfg_0 = {
.base = DT_INST_REG_ADDR_BY_NAME(0, control),
};
#define SPI_OC_INIT(inst) \
static struct spi_oc_simple_cfg spi_oc_simple_cfg_##inst = { \
.base = DT_INST_REG_ADDR_BY_NAME(inst, control), \
}; \
\
static struct spi_oc_simple_data spi_oc_simple_data_##inst = { \
SPI_CONTEXT_INIT_LOCK(spi_oc_simple_data_##inst, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_oc_simple_data_##inst, ctx), \
}; \
\
DEVICE_AND_API_INIT(spi_oc_simple_##inst, \
DT_INST_LABEL(inst), \
spi_oc_simple_init, \
&spi_oc_simple_data_##inst, \
&spi_oc_simple_cfg_##inst, \
POST_KERNEL, \
CONFIG_SPI_INIT_PRIORITY, \
&spi_oc_simple_api)
static struct spi_oc_simple_data spi_oc_simple_data_0 = {
SPI_CONTEXT_INIT_LOCK(spi_oc_simple_data_0, ctx),
SPI_CONTEXT_INIT_SYNC(spi_oc_simple_data_0, ctx),
};
DEVICE_AND_API_INIT(spi_oc_simple_0,
DT_INST_LABEL(0),
spi_oc_simple_init,
&spi_oc_simple_data_0,
&spi_oc_simple_cfg_0,
POST_KERNEL,
CONFIG_SPI_INIT_PRIORITY,
&spi_oc_simple_api);
#endif
#if DT_HAS_DRV_INST(1)
static struct spi_oc_simple_cfg spi_oc_simple_cfg_1 = {
.base = DT_INST_REG_ADDR_BY_NAME(1, control),
};
static struct spi_oc_simple_data spi_oc_simple_data_1 = {
SPI_CONTEXT_INIT_LOCK(spi_oc_simple_data_1, ctx),
SPI_CONTEXT_INIT_SYNC(spi_oc_simple_data_1, ctx),
};
DEVICE_AND_API_INIT(spi_oc_simple_1,
DT_INST_LABEL(1),
spi_oc_simple_init,
&spi_oc_simple_data_1,
&spi_oc_simple_cfg_1,
POST_KERNEL,
CONFIG_SPI_INIT_PRIORITY,
&spi_oc_simple_api);
#endif
DT_INST_FOREACH(SPI_OC_INIT)

4
drivers/watchdog/wdt_esp32.c
View file

@ -270,10 +270,10 @@ static void wdt_esp32_isr(struct device *dev)
}
#if DT_HAS_DRV_INST(0)
#if DT_HAS_NODE_STATUS_OKAY(DT_NODELABEL(wdt0))
ESP32_WDT_INIT(0);
#endif
#if DT_HAS_DRV_INST(1)
#if DT_HAS_NODE_STATUS_OKAY(DT_NODELABEL(wdt1))
ESP32_WDT_INIT(1);
#endif

8
drivers/watchdog/wdt_gecko.c
View file

@ -295,10 +295,4 @@ static const struct wdt_driver_api wdt_gecko_driver_api = {
irq_enable(DT_INST_IRQN(index)); \
}
#if DT_HAS_DRV_INST(0)
GECKO_WDT_INIT(0)
#endif /* DT_HAS_DRV_INST(0) */
#if DT_HAS_DRV_INST(1)
GECKO_WDT_INIT(1)
#endif /* DT_HAS_DRV_INST(1) */
DT_INST_FOREACH(GECKO_WDT_INIT)

10
include/devicetree.h
View file

@ -1390,16 +1390,6 @@
*/
#define DT_INST_BUS_LABEL(inst) DT_BUS_LABEL(DT_DRV_INST(inst))
/**
* @brief Does the devicetree have a particular instance number?
*
* This is equivalent to DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(inst)).
* @param inst instance number
* @return 1 if the devicetree has that numbered instance,
* 0 otherwise.
*/
#define DT_HAS_DRV_INST(inst) DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(inst))
/**
* @brief Test if a DT_DRV_COMPAT's bus type is a given type
* This is equivalent to DT_ON_BUS(DT_DRV_INST(inst), bus).

8
tests/lib/devicetree/src/main.c
View file

@ -269,9 +269,7 @@ static void test_bus(void)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT vnd_spi_device
zassert_equal(DT_HAS_DRV_INST(0), 1, "missing spi inst 0");
zassert_equal(DT_HAS_DRV_INST(1), 1, "missing spi inst 1");
zassert_equal(DT_HAS_DRV_INST(2), 0, "unexpected spi inst 2");
zassert_equal(DT_NUM_INST(DT_DRV_COMPAT), 2, "spi device count");
zassert_equal(DT_INST_ON_BUS(0, spi), 1, "spi inst 0 not on spi");
zassert_equal(DT_INST_ON_BUS(0, i2c), 0, "spi inst 0 on i2c");
@ -286,9 +284,7 @@ static void test_bus(void)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT vnd_i2c_device
zassert_equal(DT_HAS_DRV_INST(0), 1, "missing i2c inst 0");
zassert_equal(DT_HAS_DRV_INST(1), 1, "missing i2c inst 1");
zassert_equal(DT_HAS_DRV_INST(2), 0, "unexpected i2c inst 2");
zassert_equal(DT_NUM_INST(DT_DRV_COMPAT), 2, "i2c device count");
zassert_equal(DT_INST_ON_BUS(0, i2c), 1, "i2c inst 0 not on i2c");
zassert_equal(DT_INST_ON_BUS(0, spi), 0, "i2c inst 0 on spi");