drivers: clock_control: stm32f0/f3: streamline PREDIV handling
We should not set PLLSRC bits here. It is done by LL_PLL_ConfigSystemClock_* functions which are called later. Also, PREDIV1 setting should not be restricted to HSE only. Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
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1 changed files with 10 additions and 23 deletions
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@ -30,37 +30,24 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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*/
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pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
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<< RCC_CFGR_PLLMUL_Pos);
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#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
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/* PREDIV support is a specific RCC configuration present on */
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/* following SoCs: STM32F070x6, STM32F070xB and STM32F030xC */
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/* cf Reference manual for more details */
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#if defined(CONFIG_CLOCK_STM32_PLL_SRC_HSI)
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pllinit->PLLDiv = LL_RCC_PLLSOURCE_HSI;
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#else
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#if defined(CONFIG_CLOCK_STM32_PLL_PREDIV1)
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/*
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* PLL DIV
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* 1 -> LL_RCC_PLLSOURCE_HSE_DIV_1 -> 0x00010000
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* 2 -> LL_RCC_PLLSOURCE_HSE_DIV_2 -> 0x00010001
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* 3 -> LL_RCC_PLLSOURCE_HSE_DIV_3 -> 0x00010002
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* ...
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* 16 -> LL_RCC_PLLSOURCE_HSE_DIV_16 -> 0x0001000F
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*/
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pllinit->PLLDiv = (RCC_CFGR_PLLSRC_HSE_PREDIV |
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(CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1));
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#endif /* CONFIG_CLOCK_STM32_PLL_PREDIV1 */
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#endif /* CONFIG_CLOCK_STM32_PLL_SRC_HSI */
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#else
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/*
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* PLL Prediv
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* PLL PREDIV
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
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/*
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* PREDIV1 support is a specific RCC configuration present on
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* following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
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* STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
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* cf Reference manual for more details
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*/
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pllinit->PLLDiv = CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1;
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#else
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pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV - 1;
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#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
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}
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