Commit graph

116360 commits

Author SHA1 Message Date
Marcio Ribeiro
77c350c149 soc: esp32: virtual e-fuses support
Adds support for virtual e-fuses on esp32 socs

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-06-04 17:00:20 +02:00
Tien Nguyen
85f5bd9520 tests: drivers: gpio: Add support for RZ/V2H-EVK M33 core
Add support for RZ/V2H-EVK M33 core

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Tien Nguyen
5f69dd15a5 drivers: gpio: Add support for RZ/V2H
Add support for RZ/V2H

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Tien Nguyen
645acc5e9d drivers: serial: Add support for Renesas RZ/V2H
Add support for Renesas RZ/V2H

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Tien Nguyen
9a03938015 drivers: pinctrl: Add support for Renesas RZ/V2H
Add support for Renesas RZ/V2H

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Tien Nguyen
9db4953bf8 boards: renesas: Add minimal support for Renesas RZ/V2H-EVK M33 core
Add minimal support for Renesas RZ/V2H-EVK M33 core

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Tien Nguyen
58e58a819d dts: arm: renesas: Add support for Renesas RZ/V2H M33 core
Add devicetree to support for Renesas RZ/V2H M33 core

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Tien Nguyen
9970d21348 soc: renesas: Add initial support for Renesas RZ/V2H
Add initial support for Renesas RZ/V2H

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
2025-06-04 17:00:01 +02:00
Tien Nguyen
769ae5c263 manifest: Update commit id for hal_renesas
Update commit id for hal_renesas

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2025-06-04 17:00:01 +02:00
Jiafei Pan
e624cffd9b soc: imx: disable dcache until mmu is enabled during booting
Enable CONFIG_ARM64_BOOT_DISABLE_DCACHE for i.MX Cortex-A platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-04 16:59:43 +02:00
Jiafei Pan
d1b9b06b54 arm64: reset: flush D-Cache before it is disabled
In the commit 573a712bed patch "arm64:
reset: disable cache and MMU for safety", it disables D-Cache and MMU
for safety, but in some cases, for example the code is loaded into memory
by hardware debugger, we need to flush D-Cache before disable it in
order to make sure the data is coherent in the system, otherwise it
will report "Synchronous Abort" when D-Cache is disabled.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-04 16:59:43 +02:00
Jiafei Pan
ad0dfc5df8 Revert "arm64: reset: disable cache and MMU for safety"
This reverts commit 573a712bed.

The original patch disable cache and MMU, but in some cases, for example
the code is loaded into memory by hardware debugger, we need to flush
D-Cache before disable it in order to make sure the data is coherent
in the system, otherwise it will report "Synchronous Abort" when D-Cache
is disabled.

This patch revert the old one and the following patch will flush
the cache before disable it.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-04 16:59:43 +02:00
Jiafei Pan
abcdb18568 arch: arm64: cache: optionally enable APIs for operation all dcache
Added new configuration item to optionally enable APIs for operation
all data cache, by default these APIs are disabled.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-04 16:59:43 +02:00
Jiafei Pan
6aba505eaf Revert "arch: arm64: cache: delete arm64_dcache_all"
In order to clean and invalidate all D-Cache, so reverts commit:
867ba172b4.

Although no software broadcast between different CPU Cores for  D-Cache
maintaining operation, but the hardware bus system should make sure it
is safety for all CPU Cores, because it is common for other SMP OS.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-04 16:59:43 +02:00
Martino Facchin
b927659711 portenta_c33: add initial documentation
Will complete the supported peripheral list and description later

Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
2025-06-04 16:59:15 +02:00
Martino Facchin
e7fe269b81 boards: add support for Arduino Portenta C33
Tested:
* GPIO
* UART
* USB (using USB_DEVICE_NEXT)
* BLE

Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
2025-06-04 16:59:15 +02:00
Adrien Ricciardi
2f17465421 ipc: icbmsg: Add a workqueue name
This allows to easily identify the workqueue thread when using the kernel
shell commands.

Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
2025-06-04 16:59:04 +02:00
Johan Lafon
6dbfc8ee02 tests: drivers: adc: add MCP356xR
Add instance of the MCP356xR ADC to the build all tests.

Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
2025-06-04 16:58:52 +02:00
Johan Lafon
cf569036d1 driver: adc: add MCP3561/2/4R driver
Add driver for the microchip MCP3561/2/4R ADC. Registers lock and
CRCCFG protection mecanism is not implemented. Tested on an MCP3564R.

Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
2025-06-04 16:58:52 +02:00
Anas Nashif
1207880355 ci: exclude rust temporarily [REVERT ME]
Compat issues with optional module, exclude for now until issues are
fixed.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-04 08:38:44 -04:00
Sudarsan N
34f5f8d556 drivers: adc: Prevent overflow in max1125x_read_sample
Fix potential integer overflow caused by unsafe shift when computing
ADC mid-scale offset. Applies resolution bounds and uses unsigned
shift to avoid undefined behavior.

Fixes: CID 487740
Signed-off-by: Sudarsan N <sudarsansamy2002@gmail.com>
2025-06-04 10:04:14 +02:00
Andre Morishita
1fbb4e87f2 boards: variscite: Add Variscite VAR-SOM-MX93 board
Add Variscite VAR-SOM-MX93 board support. This SoM is based on NXP's
i.MX93 SoC. It includes Cortex-A55 and Cortex-M33 support.

Signed-off-by: Andre Morishita <andre.m@variscite.com>
2025-06-04 10:04:09 +02:00
Shan Pen
8d55e73808 boards: ruiside: RA8D1 Vision Board: add support
this is another board from ruiside, tested uart,
button, led, sdram, sd card

Signed-off-by: Shan Pen <bricle031@gmail.com>
2025-06-04 10:03:51 +02:00
Miguel Gazquez
783103ebf6 scripts: west_commands: runners: fix dt-flash handling in some runners
In minichlink and spi_burn, the script checks if dt_flash is True by
checking if the value is "y". But dt_flash is a boolean.
Fix these checks.

Also, when dt-flash is True, spi_burn calculate the address in a
convoluted way, by substrating CONFIG_FLASH_LOAD_OFFSET to
itself.
Simplify this computation.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-06-04 10:03:40 +02:00
Miguel Gazquez
8c6a290d4a scripts: west_commands: runners: Fix default value for --dt-flash
The '--dt-flash' parameter accepts a string like "y", "yes", "no", etc,
and is supposed to be converted into a boolean value. This is only the
theory as in practice, the default value is set to 'n' and is never
converted to False afterwards.

Set the default value to False.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-06-04 10:03:40 +02:00
Miguel Gazquez
f0d26a9d02 runners: add '--dt-flash=y' for silabs commander
Due to a bug in scripts/west_commands/runners/core.py, the value of
--dt-flash can currently be True, False, or the default value, 'n'. The
script silabs_commander.py only check the truth value of --dt-flash,
 so the default value is interpreted as a truthy. That means that the
default case was effectively the same as if dt-flash was set to True.

Set this flag to True by default explicitly, in the same
way as done for pyocd or jlink.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
2025-06-04 10:03:40 +02:00
Arunmani Alagarsamy
9da4e8f30f west.yml: Update hal_silabs revision
This commit updates the hal_silabs revision in west.yml

Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
2025-06-04 08:47:53 +02:00
Tom Hughes
60045b5ee0 arch: Add LLVM toolchain to ISR_TABLES_LOCAL_DECLARATION_SUPPORTED
The LLVM toolchain can also compile this code.

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-06-04 08:46:35 +02:00
Derek Snell
6db433bada dt-bindings: adc: mcux-lpadc: add more channel options
Expands the list of macros for more ADC channels needed on MCXN947.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2025-06-04 08:46:25 +02:00
Mike J. Chen
122b14bc68 drivers: gpio_mcux_lpc: fix bug configuring interrupts with GPIO_INT_WAKEUP
If GPIO_INT_WAKEUP is in the trig argument, the selection
of trigger mode breaks because the GPIO_INT_WAKEUP flag
breaks the equal comparisons.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2025-06-04 08:46:15 +02:00
Raffael Rostagno
d8358b29a0 tests: drivers: spi_loopback: Fix NULL rx buff testcase
Fixes setup of TX buffer, which shouldn't be NULL in the RX NULL
tescase.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-06-04 08:46:05 +02:00
Wilkins White
00ee4a5887 drivers: flash: mcux: fix read for LPC55XXX
The LPC55XXX SoC series requires the use of a HAL function to read
from uninitialized flash without triggering a hardfault. This
broadens an existing #ifdef clause so that it is triggered for all
chips in the series instead of only the LPC55S36.

Signed-off-by: Wilkins White <ww@novadynamics.com>
2025-06-04 08:45:56 +02:00
Luis Ubieda
564e7ebd8b tests: gnss: Add F9P node to build-all test
For build-time validation.

Signed-off-by: Luis Ubieda <luisf@croxel.com>
2025-06-04 08:44:59 +02:00
Luis Ubieda
b402a47604 gnss: u_blox_f9p: Introduce High-precision GNSS module
Basic support: initialization for sending/handling UBX messages and
run-time navigation configurability through GNSS API.

Signed-off-by: Luis Ubieda <luisf@croxel.com>
2025-06-04 08:44:59 +02:00
Khoa Nguyen
291860e193 tests: drivers: spi: Add support spi_controller_peripheral for RA
Add support test app support spi_controller_peripheral for Renesas
RA boards: ek_ra6m5, ek_ra6m4, ek_ra6m3, ek_ra6m2, ek_ra6m1,
ek_ra6e2, fpb_ra6e2, ek_ra4m1, ek_ra2a1

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-06-04 08:44:47 +02:00
Alex Ivanov
3aace9520f llext: Do not print symbol resolution messages
If the LLEXT extension is really large, these messages really add up.
Making them debug messages.

Signed-off-by: Alex Ivanov <alexivanov@google.com>
2025-06-03 21:37:26 -07:00
cyliang tw
4a486ce51b drivers: spi: fix the update of spi_context tx & rx length
The unit of spi_context's tx_len and rx_len is byte instead of frame.
Thus, in spi_context_update_tx(), the value of ctx->tx_len should be
reduced by (len * dfs).
Also to fix the update of ctx->tx_len in spi_context_update_rx().

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2025-06-03 21:36:39 -07:00
Ryan McClelland
2bda9ad99b drivers: spi: cdns: fixup spi clk divisor
Remove the auto setting of the external spi clock if its not there,
also fix the calculation of calucation the spi divisor value.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2025-06-03 21:34:25 -07:00
Ryan McClelland
241bb057a0 drivers: spi: cdns: remove pm device call
The PM Device callbacks is rather unimplemented. There currently is
no device agnostic clock management api (yet), and the pinctrl isn't
fully implemented in this driver. Remove it all.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2025-06-03 21:34:25 -07:00
Ryan McClelland
0d61895385 drivers: spi: cdns: fix missing fifo config
This adds the missing fifo config from the dts which was missed in
the initial revision. This also adds the spi rtio fallback api.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2025-06-03 21:34:25 -07:00
Tim Pambor
a760ba76b6 net: ip: 6lo: Fix undefined behavior reported by UBSAN
htonl() and htons() take uint32_t/uint16_t as argument. Add the 'u' suffix
to constants to ensure the correct unsigned type is used and to avoid
undefined behavior if these functions are implemented as macros using
bit shifts.

Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
2025-06-03 21:32:54 -07:00
TOKITA Hiroshi
1e14953480 Revert "modules: hal_rpi_pico: set -std=gnu11 in a toolchain independent way."
This reverts commit 05401b3f44.

Introducing c-std setting with CMake way in the commit,
but the actual command line is below.

```
arm-zephyr-eabi-gcc -DKERNEL ... -std=gnu11 ...  -std=c99 ...
```

The setting `CONFIG_STD_C99` in Kconfig appends the `-std=c99`,
and (At least in gcc,) options are processed last-come-first,
so this setting was meaningless.

This will cause a build error, so we will revert it.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2025-06-03 21:32:02 -07:00
Camille BAUD
1d91c4aecb modules: hal_wch: fix conditional compilation
adds _D8W for CH32V208

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-03 21:30:48 -07:00
Tom Hughes
2c851d998c sw_isr_table: Add braces around subobject
When building with clang, it warns:

subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c:1000:2:
error: suggest braces around initialization of subobject
[-Werror,-Wmissing-braces]

IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), shi_npcx_isr,
            DEVICE_DT_INST_GET(0), 0);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/zephyr/irq.h:49:2: note: expanded from macro 'IRQ_CONNECT'
ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/zephyr/arch/arm/irq.h:124:2: note: expanded from macro
'ARCH_IRQ_CONNECT'
Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/zephyr/sw_isr_table.h:227:2: note: expanded from macro
'Z_ISR_DECLARE'
Z_ISR_DECLARE_C(irq, flags, func, param, __COUNTER__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0
to see all)
include/zephyr/sw_isr_table.h:218:16: note: expanded from macro
'_Z_ISR_DECLARE_C'
{irq, flags, _MK_ISR_ELEMENT_SECTION(counter)}
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/zephyr/sw_isr_table.h:197:42: note: expanded from macro
'_MK_ISR_ELEMENT_SECTION'
#define _MK_ISR_ELEMENT_SECTION(counter) _MK_ISR_SECTION_NAME(irq,
                                         __FILE__, counter)
                                         ^~~~~~~~~~~~~~~~~~~~~~~~~
include/zephyr/sw_isr_table.h:195:2: note: expanded from macro
'_MK_ISR_SECTION_NAME'
"." Z_STRINGIFY(prefix) "." file "." Z_STRINGIFY(counter)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-06-03 20:33:33 +02:00
Ian Morris
e362f14ce0 boards: renesas: ek_ra6m4: added arduino labels
Added arduino_header, arduino_serial, arduino_i2c and arduino_spi node
labels to device tree board definition, allowing compatible shield
boards to be used.

Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
2025-06-03 20:33:05 +02:00
Anas Nashif
67435e394f .github: convert templates to use forms
Convert all templates to use forms.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-03 20:32:59 +02:00
Nirav Agrawal
550f3bb0b9 boards: shields: update document for nxp_m2_wifi_bt shield
- Update hardware rework details require for Bluetooth HCI UART and
 I2S interfaces to work with M.2 module.
- Update west build command for Wi-Fi shell app with extra config
 overlay file.

Signed-off-by: Nirav Agrawal <nirav.agrawal@nxp.com>
2025-06-03 20:32:42 +02:00
Stephan Gatzka
c4c1d92cee drivers: gpio: Use BIT(n) macro to define GPIO constants
This change would also solve that according to the C11 standard,
section 6.5, paragraph 4, the usage of bitwise operators on
signed integers is implementation defined.

Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com>
2025-06-03 20:32:33 +02:00
David Corbeil
068d7ec156 modules/zcbor: Added building of zcbor_print.c to zcbor module
Some utilities function implementations were moved to their own
implementation file in zcbor 0.9.0. This commit is simply to compile
those functions so that users can still have access to them without using
the --output-cmake functionality provided by the zcbor python script

Signed-off-by: David Corbeil <david.corbeil@dynon.com>
2025-06-03 20:31:02 +02:00
Mark Wang
2d4e05afc2 bluetooth: improve the controller address resolution enablement
If the controller resolving list is cleared by HCI_LE_Clear_Resolving_List,
don't need to enable the controller address resolution.

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2025-06-03 17:09:02 +02:00